Datasheet 1 Rev. 1.1, 2007-10-17
Low-Drop Fixed Voltage Regulator TLE 4299
Type Package
TLE 4299 GV33 PG-DSO-8-16
TLE 4299 GMV33 PG-DSO-14-30
P-DSO-8-3
P-DSO-14-3, -8, -9, -11
Features
• Output voltage 3.3V ± 2%
• 150 mA Output current
• Extreme low current consumption in ON state
• Inhibit function: Below 1 µA current consumption
in off mode
• Early warning
• Reset output low down to VQ = 1 V
• Overtemperature protection
• Reverse polarity proof
• Wide temperature range
• Green Product (RoHS compliant)
• AEC Qualified
Functional Description
The TLE 4299 is a monolithic voltage regulator with fixed
5-V (see data sheet TLE4299G/GM) or 3.3 V output,
supplying loads up to 150 mA. It is especially designed
for applications that may not be powered down while the
motor is off. In addition the TLE 4299GMV includes an inhibit function. When the inhibit
signal is removed, the device is switched off and the quiescent current is less than 1 µA.
To achieve proper operation of the µ-controller, the device supplies a reset signal. The
reset delay time is selected application-specific by an external delay capacitor. The reset
threshold is adjustable. An early warning signal supervises the voltage at pin SI. The
TLE 4299 is pin-compatible to the TLE 4269 and functional similar with the additional
inhibit function. The TLE 4299 is designed to supply microcontroller systems even under
automotive environment conditions. Therefore it is protected against overload, short
circuit and over temperature.
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Datasheet 2 Rev. 1.1, 2007-10-17
TLE 4299
Circuit Description
The TLE 4299 is a PNP based very low drop linear voltage regulator. It regulates the
output voltage to VQ = 3.3 V for an input voltage range of 4.4 V ≤ VI ≤ 45 V. The control
circuit protects the device against potential damages caused by overcurrent and
overtemperature.
The internal control circuit achieves a 3.3 V output voltage with a tolerance of ± 2%.
The device includes a power on reset and an under voltage reset function with adjustable
reset delay time and adjustable reset switching threshold as well as a sense control/early
warning function. The device includes an inhibit function to disable it when the ECU is
not used for example while the motor is off.
The reset logic compares the output voltage VQ to an internal threshold. If the output
voltage drops below this level, the external reset delay capacitor CD is discharged. When
VD is lower than VST, the reset output RO is switched Low. If the output voltage drop is
very short, the VST level is not reached and no reset-signal is asserted. This feature
avoids resets at short negative spikes at the output voltage e.g. caused by load changes.
As soon as the output voltage is more positive than the reset threshold, the delay
capacitor is charged with constant current. When the voltage reaches VDT the reset
output RO is set High again.
The reset delay time and the reset reaction time are defined by the external capacitor
CD. The reset function is active down to VI = 1 V.
In addition to the normal reset function, the device gives an early warning. When the SI
voltage drops below VSI,low, the devices asserts the SI output Low to indicate the logic
and the µ-processor that this voltage has dropped. The sense function uses a hysteresis:
When the SI-voltage reaches the VSI,high level, SO is set high again. This feature can be
used as early warning function to notice the µ-controller about a battery voltage drop and
a possible reset in a short time. Of course also any other voltage can be observed by this
feature.
The user defines the threshold by the resistor-values RSI1 and RSI2.
For the exact timing and calculation of the reset and sense timing and thresholds, please
refer to the application section.
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TLE 4299
Datasheet 3 Rev. 1.1, 2007-10-17
Figure 1 Block Diagram TLE 4299 GV33
AEB03103
Current
and
Saturation
Control
Band-
Gap-
Reference
TLE 4299
Reset
Control
Reference
R
SO
R
RO
RO
Q
I
D
SI
SO
GND
RADJ
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Datasheet 4 Rev. 1.1, 2007-10-17
TLE 4299
Figure 2 Block Diagram TLE 4299 GMV33
AEB03104
Current
and
Saturation
Control
Band-
Gap-
Reference
TLE 4299
Reset
Control
Reference
R
SO
Inhibit
Control R
RO
RO
Q
I
D
SI
SO
GND
RADJ
INH
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TLE 4299
Datasheet 5 Rev. 1.1, 2007-10-17
Figure 3 Pin Configuration (top view)
Pin Definitions and Functions (TLE 4299 GV33)
Pin No. Symbol Function
1I Input; block directly to GND on the IC with a ceramic capacitor.
2SISense Input; if not needed connect to Q.
3RADJReset Threshold Adjust; if not needed connect to GND.
4DReset Delay; to select delay time, connect to GND via external
capacitor.
5GNDGround
6ROReset Output; the open-collector output is linked internally to Q
via a 20kΩ pull-up resistor. Keep open, if the pin is not needed.
7SOSense Output; open-collector output. Keep open, if the pin is not
needed.
8QOutput; connect to GND with a 22 µF capacitor, 0.4 Ω <
ESR < 3.7 Ω.1)
1) see characteristic curves
AEP02832
81
IQ
SI 2 7
RADJ 3 6
D4 5
SO
RO
GND
PG-DSO-8-16
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Datasheet 6 Rev. 1.1, 2007-10-17
TLE 4299
Figure 4 Pin Configuration (top view)
Pin Definitions and Functions (TLE 4299 GMV33)
Pin No. Symbol Function
1RADJReset Threshold Adjust; if not needed connect to GND.
2DReset Delay; connect to GND via external delay capacitor for
setting delay time.
3, 4, 5 GND Ground
6INH
Inhibit: If not needed connect to Input pin I; A high signal
switches the regulator ON.
7ROReset Output; the open-collector output is linked internally to Q
via a 20kΩ pull-up resistor. Keep open, if the pin is not needed.
8SOSense Output; open-collector output. Keep open, if the pin is not
needed.
9QOutput; connect to GND with a 22 µF capacitor, 0.4 Ω <
ESR < 3.7 Ω.1)
1) see characteristic curves
10, 11, 12 GND Ground
13 I Input; block to GND directly at the IC by a ceramic capacitor.
14 SI Sense Input; if not needed connect to Q.
AEP02831
141RADJ SI
D2 13
GND 3 12
GND 4 11
10
GND 5
69
INH
RO 7 8
I
GND
GND
GND
Q
SO
PG-DSO-14-30
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TLE 4299
Datasheet 7 Rev. 1.1, 2007-10-17
Absolute Maximum Ratings
Tj=–40 to 150 °C
Parameter Symbol Limit Values Unit Notes
min. max.
Input I
Input voltage VI–40 45 V –
Inhibit Input INH
Input voltage VINH –40 45 V –
Sense Input SI
Input voltage VSI –0.3 45 V –
Input current ISI -1 1 mA –
Reset Threshold Adjust RADJ
Input voltage VRADJ –0.3 7 V –
Input current IRADJ -10 10 mA –
Reset Delay D
Voltage VD–0.3 7 V –
Reset Output RO
Voltage VR–0.3 7 V –
Sense Output SO
Voltage VSO –0.3 7 V –
Output Q
Output voltage VQ–0.3 7 V –
Output current IQ–5 –mA –
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Datasheet 8 Rev. 1.1, 2007-10-17
TLE 4299
Note: Stresses above those listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
In the operating range, the functions given in the circuit description are fulfilled.
Temperature
Junction temperature Tj– 150 °C–
Storage temperature TStg – 50 150 °C–
Operating Range
Input voltage VI4.4 45 V –
Junction temperature Tj– 40 150 °C–
Thermal Data
Junction-ambient for foot
print only1) Rthja – 200
130
K/W
K/W
PG-DSO-8-16
PG-DSO-14-30
Junction-ambient for
300mm2 cooling area2) Rthja – 164
70
K/W
K/W
PG-DSO-8-16
PG-DSO-14-30
Junction-pin Rthjp –60
30
K/W
K/W
PG-DSO-8-163)
PG-DSO-14-30
4)
1) FR4, 80x80x1,5mm; 35µ Cu, 5µ Sn; Footprint only
2) FR4, 80x80x1,5mm; 35µ Cu, 5µ Sn; 300mm2
3) Measured to pin 5
4) Measured to pin 4
Absolute Maximum Ratings (cont’d)
Tj=–40 to 150 °C
Parameter Symbol Limit Values Unit Notes
min. max.
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TLE 4299
Datasheet 9 Rev. 1.1, 2007-10-17
Characteristics
VI=13.5V; Tj=–40 °C<Tj<150 °C
Parameter Symbol Limit Values Unit Measuring Condition
min. typ. max.
Output voltage VQ3.23 3.30 3.37 V 1 mA ≤ IQ≤100 mA;
5.5 V ≤ VI≤16 V
Output voltage VQ3.20 3.30 3.40 V IQ≤150 mA;
5.5 V ≤ VI≤16 V
Current limit IQ250 400 500 mA –
Current consumption;
Iq=II–IQ
Iq– 65 105 µA Inhibit ON;
IQ≤1mA,Tj<85°C
Current consumption;
Iq=II–IQ
Iq– 170 500 µA Inhibit ON;
IQ=10mA
Current consumption;
Iq=II–IQ
Iq– 0.7 2 mA Inhibit ON;
IQ=50mA
Current consumption;
Iq=II–IQ
Iq––1 µAVINH = 0 V;
Tj = 25 °C
Load regulation ∆VQ–530mVIQ= 1 mA to 100 mA
Line regulation ∆VQ–1025mVVI= 6 V to 28 V;
IQ=1mA
Power Supply Ripple
rejection PSRR –66– dBfr = 100 Hz; Vr = 1 VSS;
IQ=100mA
Inhibit (TLE 4299 GMV33 only)
Inhibit OFF voltage range VINH OFF ––0.8VVQ off
Inhibit ON voltage range VINH ON 3.5 - V VQ on
High input current IINH ON –35 µAVINH = 5V
Low input current IINH OFF –0.52 µAVINH = 0.8 V
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Datasheet 10 Rev. 1.1, 2007-10-17
TLE 4299
Reset Generator
Switching threshold Vrt 3.00 3.10 3.20 V –
Reset threshold
headroom
VRTHEAD 50 200 300 mV –
Reset pull up RRO 10 20 40 kΩ–
Reset low voltage VR– 0.17 0.40 V VQ < 3.0 V; internal RRO;
IR=1mA
External reset pull up VR ext 5.6 – – kΩPull up resistor Q
Delay switching threshold VDT 1.6 1.85 2.35 V –
Switching threshold VST 0.35 0.50 0.60 V –
Reset delay low voltage VD––0.1VVQ<VRT
Charge current Ich 2.0 3.5 6.0 µAVD=1V
Power-up Reset delay
time
td36 51 60 ms CD=100nF
Reset reaction time trr 0.5 1.2 3.0 µsCD=100nF
Reset Adjust Switching
Threshold
VRADJ
TH
1.26 1.36 1.44 V VQ<3.5V
Input Voltage Sense
Sense threshold high VSI high 1.34 1.45 1.54 V –
Sense threshold low VSI low 1.26 1.36 1.44 V –
Sense input switching
hysteresis
VSI HYST 50 90 130 mV VSI HYST =VSI high – VSI low
Sense output low voltage VSO low –0.10.4VVSI <1.20V; Vi>4.2V;
ISO = 1mA
External SO pull up
resistor
RSO ext 5.6 – – kΩ–
Sense input current ISI –10.11 µA Si > 1.0V
Characteristics (cont’d)
VI=13.5V; Tj=–40 °C<Tj<150 °C
Parameter Symbol Limit Values Unit Measuring Condition
min. typ. max.
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TLE 4299
Datasheet 11 Rev. 1.1, 2007-10-17
Note: The listed characteristics are ensured over the operating range of the integrated
circuit. Typical characteristics specify mean values expected over the production
spread. If not otherwise specified, typical characteristics apply at TA = 25 °C and
the given supply voltage.
Figure 5 Measurement Circuit
Sense high reaction time tpd SO LH –2.44.0µsRSO ext = 5.6kΩ
Sense low reaction time tpd SO HL –2.56.0µsRSO ext = 5.6kΩ
Characteristics (cont’d)
VI=13.5V; Tj=–40 °C<Tj<150 °C
Parameter Symbol Limit Values Unit Measuring Condition
min. typ. max.
AES02835
TLE 4299
Q1
GND
I
C
D
100 nF I
ch
II
VI
I
Q1
I
GND
V
Q1
D
V
INH
I
INH
INH
V
RADJ
I
RADJ
RADJ
I
S
I
V
SI
SI SO V
SO
V
RO
RO
(TLE4299GMV33
only)
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Datasheet 12 Rev. 1.1, 2007-10-17
TLE 4299
Application Information
Figure 6 Application Diagram TLE 4299 GV33
AES03105
Current
and
Saturation
Control
Band-
Gap-
Reference
TLE 4299
Reset
Control
RO
Q
I
D
CI
1
V
BAT
C
D
GND
R
ADJ1
P
R
SI1
R
SI2
Reference
SI
R
SO
R
RO
R
ADJ2
SO
RADJ
CI
2
C
Q1
22 FC
Q2
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TLE 4299
Datasheet 13 Rev. 1.1, 2007-10-17
Figure 7 Application Diagram with Inhibit Function TLE4299 GMV33
The TLE 4299 supplies a regulated 3.3 V output voltage with an accuracy of 2% for an
input voltage between 4.4 V and 45 V in the temperature range of Tj = – 40 to 150 °C, in
an output current range of 1 mA to 100 mA.
The device is capable to supply 150 mA with an accuracy of 3%. For protection at high
input voltage above 25 V, the output current is reduced (SOA protection).
An input capacitor is necessary for compensating line influences and to limit steep input
edges. A resistor of approx. 1 Ω in series with CI, can damp the LC of the input inductivity
and the input capacitor.
The voltage regulator requires for stability an output capacitor CQ of at least 22 µF with
an 0.4Ω < ESR < 3.7Ω for the whole load- and temperature range. For more detailed
information, refer to the characteristical curves.
AES03106
Current
and
Saturation
Control
Band-
Gap-
Reference
TLE 4299
Reset
Control
RO
Q
I
D
CI
1
V
BAT
C
D
GND
R
ADJ1
P
R
SI1
R
SI2
Reference
SI
R
SO
R
RO
R
ADJ2
SO
RADJ
CI
2
Inhibit
Logic
INH
From
KI. 15
C
Q1
22 FC
Q2
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Datasheet 14 Rev. 1.1, 2007-10-17
TLE 4299
Reset
The power on reset feature is necessary for a defined start of the microprocessor when
switching on the application. For the reset delay time after the output voltage of the
regulator is above the reset threshold, the reset signal is set High again. The reset delay
time is defined by the reset delay capacitor CD at pin D.
The under-voltage reset circuitry supervises the output voltage. In case VQ decreases
below the reset threshold the reset output is set LOW after the reset reaction time. The
reset LOW signal is generated down to an output voltage VQ to 1 V. Both the reset
reaction time and the reset delay time is defined by the capacitor value.
The power on reset delay time is defined by the charging time of an external delay
capacitor CD.
CD = (td × ID) / ∆V[1]
td = CD x ∆V / ID[2]
With CDreset delay capacitor
tdreset delay time
∆V= VDT, typical 1.8 V for power up reset
Ich charge current typical 3.5 µA
For a delay capacitor CD =100 nF the typical power on reset delay time is 51 ms.
The reset reaction time tRR is the time it takes the voltage regulator to set reset output
LOW after the output voltage has dropped below the reset threshold. It is typically 1.2 µs
for delay capacitor of 100 nF. For other values for CD the reaction time can be estimated
using the following equation:
tRR ∼ 10 ns / nF × CD[3]
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TLE 4299
Datasheet 15 Rev. 1.1, 2007-10-17
Figure 8 Reset Timing Diagram
The reset output is an open collector output. An external pull-up can be added with a
resistor value of at least 5.6 kΩ.
In addition the reset switching threshold can be adjusted by an external voltage divider.
The feature is useful for microprocessors which guarantee safe operation down to volt-
ages below the internally set reset threshold of 3.10V typical. If the internal used reset
threshold of typical 3.10V is used, the pin RADJ has to beconnected to GND.
If a lower reset threshold is required by the system, a voltage divider defines the reset
threshold VRth between 2.5V and 3.10V as long as the Input Voltage VI>4.4V
VRth = VRADJ TH * (RADJ1 + RADJ2) / RADJ2 (3)
VRADJ TH is typical 1.36 V.
AED03107
Thermal
td
Power-on-Reset Voltage Dip Secondary Overload
at OutputSpike
t
VST
VRO, SAT
RT
V
tRR
<
RR
t
at Input Undervoltage
Shutdown
V
VRO
D
V
t
t
t
t
Q
V
V
I
VDT
d
d
I
CD
D
=
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Datasheet 16 Rev. 1.1, 2007-10-17
TLE 4299
Early Warning
The early warning function compares a voltage defined by the user to an internal
reference voltage. Therefore the supervised voltage has to be scaled down by an
external voltage divider in order to compare it to the internal sense threshold of typical
1.36 V. The sense output pin is set low, when the voltage at SI falls below this threshold.
A typical example where the circuit can be used is to supervise the input voltage VI to
give the microcontroller a prewarning of low battery condition.
Calculation to the voltage divider can be easily done since the sense input current can
be neglected.
Figure 9 Sense Timing Diagram
VthHL = (RSI1 + RSI2)/RSI2 × VSI low [4]
VthLH = (RSI1 + RSI2)/RSI2 × VSI high [5]
The sense in comparator uses a hysteresis of typical 90 mV. This hysteresis of the
supervised threshold is multiplied by the resistor dividers amplification (RSI1 + RSI2)/RSI1.
The sense in comparator can also be used for receiving data with a threshold of typical
1.36 V and a hysteresis of 90 mV. Of course also the data signal can be scaled down
with a resistive divider as shown above. With a typical delay time of 2.5 µs for positive
transitions and 2.4 µs for negative transitions receiving data of up to 100 kBaud are
possible. The sense output is an open collector output.
t
Sense
t
SI, High
V
SI, Low
V
Input
Voltage
High
Low
Output
Sense t
PD SO LH PD SO HL
t
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Datasheet 17 Rev. 1.1, 2007-10-17
TLE 4299
Current Consumption Iq versus
Junction Temperature Tj
Current Consumption Iq versus Output
Current IQ
1_Iq-Tj.vsd
10
1
0.01
100
Iq [µA]
-40
T
j
[°C]
-20 20 40 80 100
060 140120
VI = 13.5V
IQ = 1mA
080120
2_IQ-IQ.VSD
6
4
2
8
40 160
Tj = -40 °C
12
Tj = 25 °C
IQ [mA]
Iq
[mA]
Tj = 150 °C
Current Consumption Iq versus Input
Voltage VI
0
VI [V]
20 30
Iq [mA]
3_IQ-VI.VSD
1.5
1
0.5
2
10 40
IQ = 1mA
IQ = 10mA
T = 25°C
3
Output Voltage VQ versus Junction
Temperature Tj
AED01671
-40
V
Q
V
04080
120 C 160
2.9
3.0
3.1
3.2
3.3
3.4
Ι
V= 13.5 V
3.5
j
T
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Datasheet 18 Rev. 1.1, 2007-10-17
TLE 4299
Maximum Output Current IQ versus
Junction Temperature Tj
Maximum Output Current IQ versus
Input Voltage VI
Reverse Output Current IQ versus
Output Voltage VQ
Output Voltage VQ at Input Voltage
Extremes
-40
Tj [°C]
-20 20 40 80 100
IQ [mA]
8_IQMAX-TJ.VSD
400
350
300
450
060 140120
VI = 13.5 V
250
550
AED03110
0
Ι
Q
mA
10 20 30 40 V50
0
=25C
Ι
V
50
100
150
200
250
300
350
C125=
j
T
j
T
0
VQ [V]
20 30
IQ [mA]
10_IQ-VQ.vsd
-40
-60
-80
-20
10 40
VI = 0 V
Tj = 25 °C
Tj = -40 °C
10
-100
Tj = 150 °C
AED01808
0
V
Q
[V]
1234V5
0
1
2
3
4
6
Ι
V
R
L
=50
Ω
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Datasheet 19 Rev. 1.1, 2007-10-17
TLE 4299
Region of Stability
Region of Stability
Power Supply Ripple Rejection PSRR
versus Frequency f
Load Transient Response Peak Voltage
DVQ
12_ESR-
IQ_150.VSD
1
0.1
0.01
ESRCQ
[Ω]
0
IQ [mA]
80 120
40 160
CQ = 22µF
Tj = 150 °C
100
10
Stable
Region
VI=25V
VI=6V
VI=25V
VI=6V
12_ESR-IQ_-
40.VSD
1
0.1
0.01
ESRCQ
[Ω]
0
IQ [mA]
80 120
40 160
CQ = 22µF
Tj = -40 °C
100
10
Stable
Region
VI=25V
VI=6V
VI=25V
VI=6V
10
f [Hz]
10k
PSRR
[dB]
13_PSRR.VSD
70
60
100 1k 100k
90
40
50
IQ = 1 mA
VRIPPLE = 0.5 V
VIN = 13.5 V
CQ = 22 µF Tantalum
Tj = 25 °C
IQ = 100 mA
IQ = 0.1 mA
IQ = 10 mA
20_Load Trancient vs time 125.vsd
IQ1:100mA
T=1µs/DIV VQ=100mV/DIV
VQ
Tj=125°C
Vi=13.5V
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Datasheet 20 Rev. 1.1, 2007-10-17
TLE 4299
Line Transient Response Peak Voltage
DVQ
Inhibut Input Current IINH at Inhibit Input
Voltage Extremes
Inhibit Input Current at Input Voltage
Extremes (INH=OFF)
Reset Trigger Threshold VRT versus
Junction Temperature Tj
21_Line Trancient vs time 125.vsd
dVI 2V
T=500µs/DIV VQ=50mV/DIV
VQ
Tj=125°C
Vi=13.5V
IINH
[µA]
24_IINH vs VINH.vsd
30
20
10
40
Tj = 25°C
10
VINH [V]
30 40
20
50
Tj = -40°C
Tj = 150°C
IINH
[µA]
25_IINH vs VIN INH_off.vsd
30
20
10
40
10
VIN [V]
30 40
20
50
Tj = -40...150°C
INH = OFF
-40
Tj [°C]
-20 20 40 80 100
VRT
[V]
26_VRT VS TEMP.VSD
3.10
3.05
3.0
3.15
060 140120
VI = 13.5 V
Reset Trigger
Threshold
3.25
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Datasheet 21 Rev. 1.1, 2007-10-17
TLE 4299
Reset Delay Time TRD versus Junction
Temperature Tj
Delay Capacitor Charge Current versus
Junction Temperature Tj
Sense Threshold High versus Junction
Temperature Tj
Sense Threshold Low versus Junction
Temperature Tj
-40
Tj [°C]
-20 20 40 80 100
TRD
[ms]
27_RESETDELAY VS
TEMP.VSD
45
40
35
50
0 60 140120
VI = 13.5 V
60
CD = 100nF
-40
Tj [°C]
-20 20 40 80 100
ICH
[µA]
27A_ID-TEMP.VSD
3
2
1
4
0 60 140120
VI = 13.5 V
6
-40
Tj [°C]
-20 20 40 80 100
VSI_Hi
[V]
34_VSI_HI VS TEMP.VSD
1.45
1.40
1.35
1.50
060 140120
VI = 13.5 V
1.60
-40
Tj [°C]
-20 20 40 80 100
VSI_Lo
[V]
35_VSI_LO VS TEMP.VSD
1.35
1.30
1.25
1.40
0 60 140120
VI = 13.5 V
1.50
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Datasheet 22 Rev. 1.1, 2007-10-17
TLE 4299
Package Outlines
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products
and to be compliant with government regulations the device is available as a green
product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable
for Pb-free soldering according to IPC/JEDEC J-STD-020).
+0.06
0.19
0.35 x 45˚
1)
-0.2
4C
8 MAX.
0.64
±0.2
6
±0.25
0.2 8x
MC
1.27
+0.1
0.41 0.2 MA
-0.06
1.75 MAX.
(1.45)
±0.07
0.175
B
8x
B
2)
Index Marking
5-0.21)
41
85
A
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Lead width can be 0.61 max. in dambar area
GPS01181
0.1
PG-DSO-8-16 (SMD)
(Plastic Dual Small Outline)
Dimensions in mm
SMD = Surface Mounted Device
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TLE 4299
Datasheet 23 Rev. 1.1, 2007-10-17
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products
and to be compliant with government regulations the device is available as a green
product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable
for Pb-free soldering according to IPC/JEDEC J-STD-020).
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Lead width can be 0.61 max. in dambar area
-0.2
8.75 1)
0.64
0.19 +0.06
Index Marking
1.27
+0.10
0.41
0.1
1
14
2)
7
14x
8
0.175
(1.47)
±
0.07
±0.2
6
0.35 x 45˚
-0.2
1.75 MAX.
41)
±0.25
8˚MAX.
-0.06
0.2 MAB
M
0.2 C
C
B
A
GPS01230
PG-DSO-14-30 (SMD)
(Plastic Dual Small Outline)
Dimensions in mm
SMD = Surface Mounted Device
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TLE 4299
Revision History
Datasheet 24 Rev. 1.1, 2007-10-17
Version Date Changes
Rev. 1.1 2007-10-17 Initial version of RoHS-compliant derivate of TLE 4299
Page 1: AEC certified statement added
Page 1 and Page 22f: RoHS compliance statement and
Green product feature added
Page 1 and Page 22f: Package drawing changed to RoHS
compliant version
Legal Disclaimer updated
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Edition 2007-10-17
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2007 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
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