SYNCHRONOUS
BURST SRAM 32K x 36 SRAM
+3.3V SUPPLY WITH CLOCKED,
REGISTERED INPUTS, BURST COUNTER
GVT7132B36
32K X 36 SYNCHRONOUS BURST SRAM
GALVANTECH, INC.
Pentium is a trademark of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
Galvantech, Inc. reserves the right to change
Rev. 2/98products or specifications without notice.
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051
Tel (408) 566-0688 Fax (408) 566-0699
FEATURES
•Fast access times: 9, 10, and 12ns
•Fast clock speed: 66, and 50 MHz
•Provide high performance 2-1-1-1 access rate
•Fast OE# access times: 5 and 6ns
•Single +3.3V -5% and +10% power supply
•5V tolerant inputs except I/O’s
•Clamp diodes to VSSQ at all inputs and outputs
•Common data inputs and data outputs
•BYTE WRITE ENABLE and GLOBAL WRITE control
•Three chip enables for depth expansion and address
pipeline
•Address, data and control registers
•Internally self-timed WRITE CYCLE
•Burst control pins (interleaved or linear burst sequence)
•Automatic power-down for portable applications
•High density, high speed packages
•Low capacitive bus loading
•High 30pF output drive capability at rated access time
OPTIONSMARKING
•Timing
9ns access/15ns cycle -9
10ns access/15ns cycle -10
12ns access/20ns cycle -12
•Packages
100-pin PQFP Q
100-pin TQFP T
GENERAL DESCRIPTION
The Galvantech Synchronous Burst SRAM family
employs high-speed, low power CMOS designs using
advanced double-layer polysilicon, double-layer metal
technology. Each memory cell consists of four transistors and
two high valued resistors.
The GVT7132B36 SRAM integrates 32768x36 SRAM
cells with advanced synchronous peripheral circuitry and a 2-
bit counter for internal burst operation. All synchronous
inputs are gated by registers controlled by a positive-edge-
triggered clock input (CLK). The synchronous inputs include
all addresses, all data inputs, address-pipelining chip enable
(CE#), depth-expansion chip enables (CE2# and CE2), burst
control inputs (ADSC#, ADSP#, and ADV#), write enables
(BW1#, BW2#, BW3#, BW4#,and BWE#), and global write
(GW#).
Asynchronous inputs include the output enable (OE#),
burst mode control (MODE), and sleep mode control (ZZ).
The data outputs (Q), enabled by OE#, are also asynchronous.
Addresses and chip enables are registered with either
address status processor (ADSP#) or address status controller
(ADSC#) input pins. Subsequent burst addresses can be
internally generated as controlled by the burst advance pin
(ADV#).
Address, data inputs, and write controls are registered on-
chip to initiate self-timed WRITE cycle. WRITE cycles can
be one to four bytes wide as controlled by the write control
inputs. Individual byte write allows individual byte to be
written. BW1# controls DQ1-DQ8 and DQP1. BW2# controls
DQ9-DQ16 and DQP2. BW3# controls DQ17-DQ24 and
DQP3. BW4# controls DQ25-DQ32 and DQP4. BW1#,
BW2# BW3#, and BW4# can be active only with BWE#
being LOW. GW# being LOW causes all bytes to be written.
The GVT7132B36 operates from a +3.3V power supply.
All inputs and outputs are TTL-compatible. The device is
ideally suited for 486, PentiumTM, 680x0, and PowerPCTM
systems and for systems that are benefited from a wide
synchronous data bus.
February 6, 19982Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 2/98
GVT7132B36
32K X 36 SYNCHRONOUS BURST SRAM
GALVANTECH, INC.
FUNCTIONAL BLOCK DIAGRAM
NOTE: The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing
diagrams for detailed information.
DQ
DQ
BW3#
BW4#
CE#
CE2
CE2#
BYTE 3 WRITE
BYTE 4 WRITE
ENABLE
OE#
byte 3 write
ADSP#
ADSC#
Address
Register
Binary
Counter
& Logic
CLR
A14-A2
A1-A0
ADV#
MODE
32K x 9 x 4
SRAM Array
Output Buffers
Input
Register
byte 4 write
DQ1-DQ32,
DQP1, DQP2
DQP3, DQP4
DQ
DQ
DQ
BW1#
BWE#
BW2#
GW#
BYTE 1 WRITE
BYTE 2 WRITE
CLK
byte 2 write
byte 1 write
Power Down LogicZZ
February 6, 19983Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 2/98
GVT7132B36
32K X 36 SYNCHRONOUS BURST SRAM
GALVANTECH, INC.
PIN ASSIGNMENT (Top View)
PIN DESCRIPTIONS
QFP PINSSYMBOLTYPEDESCRIPTION
37, 36, 35, 34, 33,
32, 100, 99, 82, 81,
44, 45, 46, 47, 48
A0-A14Input-
SynchronousAddresses: These inputs are registered and must meet the setup and hold times around
the rising edge of CLK. The burst counter generates internal addresses associated with A0
and A1, during burst cycle and wait cycle.
93,94,95,96BW1#,
BW2#,
BW3#,
BW4#
Input-
SynchronousByte Write: A byte write is LOW for a WRITE cycle and HIGH for a READ cycle. BW1#
controls DQ1-DQ8 and DQP1. BW2# controls DQ9-DQ16 and DQP2. BW3# controls
DQ17-DQ24 and DQP3. BW4# controls DQ25-DQ32 and DQP4. Data I/O are high
impedance if either of these inputs are LOW, conditioned by BWE# being LOW.
87BWE#Input-
SynchronousWrite Enable: This active LOW input gates byte write operations and must meet the setup
and hold times around the rising edge of CLK.
88GW#Input-
SynchronousGlobal Write: This active LOW input allows a full 36-bit WRITE to occur independent of the
BWE# and BWn# lines and must meet the setup and hold times around the rising edge of
CLK.
89CLKInput-
SynchronousClock: This signal registers the addresses, data, chip enables, write control and burst
control inputs on its rising edge. All synchronous inputs must meet setup and hold times
around the clock’s rising edge.
98CE#Input-
SynchronousChip Enable: This active LOW input is used to enable the device and to gate ADSP#.
92CE2#Input-
SynchronousChip Enable: This active LOW input is used to enable the device.
100-pin PQFP
or
100-pin TQFP
100 99 98 97 96 95 94 93 92 91 90 89 88
1
2
3
4
5
6
7
8
9
10
31 32 33 34 35 36 37 38 39 40 41 42 43
87 86 85 84 83 82 81
80
79
78
77
76
75
74
73
72
71
70
69
68
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
44 45 46 47 48 49 50
A6
A7
CE#
ADSC#
ADSP#
ADV#
CLK
OE#
A8
A9
VCC
VSS
GW#
BWE#
CE2#
DQP2
DQ16
DQ15
VSSQ
VCCQ
DQ10
DQ9
DQ8
DQ7
VCCQ
VSSQ
DQ6
DQ5
VSS
NC
VCC
ZZ
A5
A4
A3
A2
A1
A0
VSS
VCC
A10
A14
A13
A12
A11
MODE
NC
NC
NC
NC
NC
NC
CE2
BW4#
BW3#
BW2#
BW1#
VCCQ
VSSQ
DQ14
DQ13
DQ12
DQ11
DQ4
DQ3
DQ2
DQ1
DQP1
VSSQ
VCCQ
DQP3
DQ17
DQ18
VSSQ
VCCQ
DQ23
DQ24
DQ25
DQ26
VCCQ
VSSQ
DQ27
DQ28
VSS
NC
VCC
NC
VCCQ
VSSQ
DQ19
DQ20
DQ21
DQ22
DQ29
DQ30
DQ31
DQ32
DQP4
VSSQ
VCCQ
February 6, 19984Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 2/98
GVT7132B36
32K X 36 SYNCHRONOUS BURST SRAM
GALVANTECH, INC.
PIN DESCRIPTIONS (continued)
BURST ADDRESS TABLE (MODE = NC/VCCQ)
BURST ADDRESS TABLE (MODE = GND)
QFP PINSSYMBOLTYPEDESCRIPTION
97CE2input-
SynchronousChip enable: This active HIGH input is used to enable the device.
86OE#InputOutput Enable: This active LOW asynchronous input enables the data output drivers.
83ADV#Input-
SynchronousAddress Advance: This active LOW input is used to control the internal burst counter. A
HIGH on this pin generates wait cycle (no address advance).
84ADSP#Input-
SynchronousAddress Status Processor: This active LOW input, along with CE# being LOW, causes
a new external address to be registered and a READ cycle is initiated using the new
address.
85ADSC#Input-
SynchronousAddress Status Controller: This active LOW input causes device to be de-selected or
selected along with new external address to be registered. A READ or WRITE cycle is
initiated depending upon write control inputs.
31MODEInput-
StaticMode: This input selects the burst sequence. A LOW on this pin selects LINEAR
BURST. A NC or HIGH on this pin selects INTERLEAVED BURST.
64ZZInput-
AsynchronousSnooze: This active HIGH input puts the device in low power consumption standby
mode. For normal operation, this input has to be either LOW or NC (No Connect).
52, 53, 56, 57, 58, 59,
62, 63, 68, 69, 72-75,
78, 79, 2, 3, 6-9, 12, 13,
18, 19, 22-25, 28, 29
DQ1-DQ32Input/
OutputData Inputs/Outputs: First Byte is DQ1-DQ8. Second Byte is DQ9-DQ16. Third Byte is
DQ17-DQ24. Fourth Byte is DQ25-DQ32. Input data must meet setup and hold times
around the rising edge of CLK.
51, 80, 1, 30DQP1, DQP2,
DQP3, DQP4Input/
OutputParity Inputs/Outputs: DQP1 is parity bit for DQ1-DQ8 and DQP2 is parity bit for DQ9-
DQ16. DQP3 is parity bit for DQ17-DQ24 and DQP4 is parity bit for DQ25-DQ32.
15, 41,65, 91VCCSupplyPower Supply: +3.3V -5% and +10%
17, 40, 67, 90VSSGroundGround: GND
4, 11, 20, 27, 54, 61, 70,
77VCCQI/O SupplyOutput Buffer Supply: +3.3V -5% and +10%
5, 10, 21, 26, 55, 60, 71,
76VSSQI/O GroundOutput Buffer Ground: GND
14, 16, 38, 39, 42, 43,
49, 50, 66NC -No Connect: These signals are not internally connected.
First Address
(external)Second Address
(internal)Third Address
(internal)Fourth Address
(internal)
A...A00A...A01A...A10A...A11
A...A01A...A00A...A11A...A10
A...A10A...A11A...A00A...A01
A...A11A...A10A...A01A...A00
First Address
(external)Second Address
(internal)Third Address
(internal)Fourth Address
(internal)
A...A00A...A01A...A10A...A11
A...A01A...A10A...A11A...A00
A...A10A...A11A...A00A...A01
A...A11A...A00A...A01A...A10
February 6, 19985Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 2/98
GVT7132B36
32K X 36 SYNCHRONOUS BURST SRAM
GALVANTECH, INC.
TRUTH TABLE
Note: 1. X means “don’t care.” H means logic HIGH. L means logic LOW. WRITE# = L means [BWE# +
BW1#*BW2#*BW3#*BW4#]*GW# equals LOW. WRITE# = H means [BWE# + BW1#*BW2#*BW3#*BW4#]*GW# equals
HIGH.
2. BW1# enables write to DQ1-DQ8 and DQP1. BW2# enables write to DQ9-DQ16 and DQP2. BW3# enables write to DQ17-
DQ24 and DQP3. BW4# enables write to DQ25-DQ32 and DQP4.
3. All inputs except OE# must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
4. Suspending burst generates wait cycle.
5. For a write operation following a read operation, OE# must be HIGH before the input data required setup time plus High-Z time
for OE# and staying HIGH throughout the input data hold time.
6. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
7. ADSP# LOW along with chip being selected always initiates an READ cycle at the L-H edge of CLK. A WRITE cycle can be
performed by setting WRITE# LOW for the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for
clarification.
PARTIAL TRUTH TABLE FOR READ/WRITE
OPERATIONADDRESS
USEDCE#CE2#CE2ADSP#ADSC#ADV#WRITE#OE#CLKDQ
Deselected Cycle, Power DownNoneHXXXLX X X L-HHigh-Z
Deselected Cycle, Power DownNoneLXL L X X X X L-HHigh-Z
Deselected Cycle, Power DownNoneLHXLX X X X L-HHigh-Z
Deselected Cycle, Power DownNoneLXLHLX X X L-HHigh-Z
Deselected Cycle, Power DownNoneLHXHLX X X L-HHigh-Z
READ Cycle, Begin BurstExternalL L HLX X X LL-HQ
READ Cycle, Begin BurstExternalL L HLX X X HL-HHigh-Z
WRITE Cycle, Begin BurstExternalL L H H LXLXL-H D
READ Cycle, Begin BurstExternalL L H H LXHLL-HQ
READ Cycle, Begin BurstExternalL L H H LXH H L-HHigh-Z
READ Cycle, Continue BurstNextXXXH H LHLL-HQ
READ Cycle, Continue BurstNextXXXH H LH H L-HHigh-Z
READ Cycle, Continue BurstNextHXXXHLHLL-HQ
READ Cycle, Continue BurstNextHXXXHLH H L-HHigh-Z
WRITE Cycle, Continue BurstNextXXXH H L L XL-H D
WRITE Cycle, Continue BurstNextHXXXHL L XL-H D
READ Cycle, Suspend BurstCurrentXXXH H H H LL-HQ
READ Cycle, Suspend BurstCurrentXXXH H H H H L-HHigh-Z
READ Cycle, Suspend BurstCurrentHXXXH H H LL-HQ
READ Cycle, Suspend BurstCurrentHXXXH H H H L-HHigh-Z
WRITE Cycle, Suspend BurstCurrentXXXH H H LXL-H D
WRITE Cycle, Suspend BurstCurrentHXXXH H LXL-H D
FUNCTIONGW#BWE#BW1#BW2#BW3#BW4#
READ H H XXXX
READ H LHHHH
WRITE one byteHL L HHH
WRITE all bytesHLLLLL
WRITE all bytesLXXXXX
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Supply Relative to VSS...-0.5V to +4.6V
VIN ...........................................................-0.5V to VCC+0.5V
Storage Temperature (plastic) .......................-55oC to +125o
Junction Temperature ....................................................+125o
Power Dissipation ...........................................................1.4W
Short Circuit Output Current ......................................100mA
*Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.This is a stress
rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
February 6, 19986Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 2/98
GVT7132B36
32K X 36 SYNCHRONOUS BURST SRAM
GALVANTECH, INC.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(0oC ≤ Ta ≤ 70°C; VCC = 3.3V -5% and +10% unless otherwise noted)
CAPACITANCE
THERMAL CONSIDERATION
DESCRIPTIONCONDITIONSSYMBOLMINMAXUNITSNOTES
Input High (Logic 1) voltageVIH2.0VCCQ+0.3V1,2
Input Low (Logic 0) VoltageVIl-0.30.8V1, 2
Input Leakage Current0V < VIN < VCCILI-2 2 uA14
Output Leakage CurrentOutput(s) disabled,
0V < VOUT < VCCILO-2 2 uA
Output High VoltageIOH = -4.0mA VOH2.4V1, 11
Output Low VoltageIOL = 8.0mA VOL0.4V1, 11
Supply VoltageVCC3.13.6V1
DESCRIPTIONCONDITIONS SYMTYP-9-10-12UNITSNOTES
Power Supply
Current: OperatingDevice selected; all inputs < VILor >
VIH;cycle time > tKC MIN; VCC =MAX;
outputs open
Icc150240240200mA3, 12, 13
Power Supply
Current: Idle
CMOS Standby
TTL Standby
Clock Running
Device selected; ADSC#, ADSP#, ADV#,
GW#, BWE# >VIH; all other inputs < VILor >
VIH; VCC = MAX;
cycle time > tKC MIN; outputs open
ISB115 40 4030mA12,13
Device deselected; VCC = MAX;
all inputs < VSS +0.2 or >VCC -0.2;
all inputs static; CLK frequency = 0
ISB20.2 2 2 2 mA12,13
Device deselected; all inputs < VIL
or > VIH; all inputs static;
VCC = MAX; CLK frequency = 0
ISB34 10 1010mA12,13
Device deselected;
all inputs < VIL or > VIH; VCC = MAX;
CLK cycle time > tKC MIN
ISB415 40 4030mA12,13
DESCRIPTIONCONDITIONSSYMBOLTYPMAXUNITSNOTES
Input CapacitanceTA = 25oC; f = 1 MHz
VCC = 3.3VCI3 4 pF4
Input/Output Capacitance (DQ)CO6 7 pF4
DESCRIPTIONCONDITIONSSYMBOLPLCC TYPTQFP TYPUNITSNOTES
Thermal Resistance - Junction to AmbientStill air, soldered on 4.25 x
1.125 inch 4-layer PCBΘJATBD20 oC/W
Thermal Resistance - Junction to CaseΘJC3 1 oC/W
February 6, 19987Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 2/98
GVT7132B36
32K X 36 SYNCHRONOUS BURST SRAM
GALVANTECH, INC.
AC ELECTRICAL CHARACTERISTICS
(Note 5) (0oC ≤ TA ≤ 70oC; VCC = 3.3V -5% and +10%)
CAPACITANCE DERATING
DESCRIPTION- 9- 10- 12
SYMMINMAXMINMAXMINMANUNITSNOTES
Clock
Clock cycle timetKC151520 ns
Clock HIGH timetKH4 5 6 ns
Clock LOW timetKL 4 5 6 ns
Output Times
Clock to output validtKQ91012 ns
Clock to output invalidtKQX3 3 3 ns
Clock to output in Low-ZtKQLZ3 3 3 ns6,7
Clock to output in High-ZtKQHZ5 5 6 ns6,7
OE to output validtOEQ5 5 6 ns9
OE to output in Low-ZtOELZ0 0 0 ns6,7
OE to output in High-ZtOEHZ5 5 6 ns6,7
Setup Times
Address, Controls and Data IntS2.52.5 3 ns10
Hold Times
Address, Controls and Data IntH0.50.50.5 ns10
DESCRIPTIONSYMBOLTYPMAXUNITSNOTES
Clock to output valid∆ tKQ0.016ns / pF15
AC TEST CONDITIONS
Input pulse levels0V to 3.0V
Input rise and fall times1.5ns
Input timing reference levels1.5V
Output reference levels1.5V
Output loadSee Figures 1 and 2
OUTPUT LOADS
Vt = 1.5V
30 pF
DQ
Z0 = 50Ω
Fig. 1 OUTPUT LOAD EQUIVALENT
50Ω
DQ
3.3v
317Ω
351Ω
Fig. 2 OUTPUT LOAD EQUIVALENT
5 pF
February 6, 19988Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 2/98
GVT7132B36
32K X 36 SYNCHRONOUS BURST SRAM
GALVANTECH, INC.
NOTES
1. All voltages referenced to VSS (GND).
2. Overshoot: VIH ≤ +6.0V for t ≤ tKC /2.
Undershoot: VIL ≤ -2.0V for t ≤ tKC /2
3. Icc is given with no output current. Icc increases with greater
output loading and faster cycle times.
4. This parameter is sampled.
5. Test conditions as specified with the output loading as shown in
Fig. 1 unless otherwise noted.
6. Output loading is specified with CL=5pF as in Fig. 2.
7. At any given temperature and voltage condition, tKQHZ is less
than tKQLZ and tOEHZ is less than tOELZ.
8. A READ cycle is defined by byte write enables all HIGH or
ADSP# LOW along with chip enables being active for the
required setup and hold times. A WRITE cycle is defined by at
one byte or all byte WRITE per READ/WRITE TRUTH
TABLE.
9. OE# is a “don’t care” when a byte write enable is sampled LOW.
10. This is a synchronous device. All synchronous inputs must meet
specified setup and hold time, except for “don’t care” as defined
in the truth table.
11. AC I/O curves are available upon request.
12. “Device Deselected” means the device is in POWER -DOWN
mode as defined in the truth table. “Device Selected” means the
device is active.
13. Typical values are measured at 3.3V, 25oC and 20ns cycle time.
14. MODE pin has an internal pull-up and ZZ pin has an internal
pull-down. These two pins exhibit an input leakage current of
+30 µA.
15. Capacitance derating applies to capacitance different from the
load capacitance shown in Fig. 1.
February 6, 19989Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 2/98
GVT7132B36
32K X 36 SYNCHRONOUS BURST SRAM
GALVANTECH, INC.
READ TIMING
Note: CE# active in this timing diagram means that all chip enables CE#, CE2, and CE2# are active.
CLK
ADSP#
ADSC#
ADDRESS
BW1#, BW2#,
BW3#, BW4#,
BWE#, GW#
CE#
(See Note)
ADV#
OE#
DQ
A1 A2
Q(A1) Q(A2) Q(A2+1) Q(A2+2) Q(A2+3) Q(A2) Q(A2+1) Q(A2+2)
tKQ
tKQLZ tOELZ
tKQ
tS
tS
tH
tH
tS
tH
tKH
tKL
tKC
tOEQ
SINGLE READ BURST READ
February 6, 199810 Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 2/98
GVT7132B36
32K X 36 SYNCHRONOUS BURST SRAM
GALVANTECH, INC.
WRITE TIMING
Note: CE# active in this timing diagram means that all chip enables CE#, CE2, and CE2# are active.
CLK
ADSP#
ADSC#
ADDRESS
BW1#, BW2#,
BW3#, BW4#,
BWE#
CE#
(See Note)
ADV#
OE#
DQ
A1 A2
D(A2) D(A2+2) D(A2+3) D(A3) D(A3+1) D(A3+2)
tS
tS
tH
tH
tS
tH
GW#
A3
D(A1) D(A2+2)
tKQX
tOEHZ
QD(A2+2)
SINGLE WRITE BURST WRITE BURST WRITE
February 6, 199811Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 2/98
GVT7132B36
32K X 36 SYNCHRONOUS BURST SRAM
GALVANTECH, INC.
READ/WRITE TIMING
Note: CE# active in this timing diagram means that all chip enables CE#, CE2, and CE2# are active.
CLK
ADSP#
ADSC#
ADDRESS
BW1#, BW2#,
BW3#, BW4#,
BWE#, GW#
CE#
(See Note)
ADV#
OE#
DQ
A1 A2 A3
Q(A1) Q(A2)
tS
tH
tS
tH
A4
D(A3) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3) D(A5) D(A5+1)
Single Write Burst Read Burst WriteSingle Reads
A5
February 6, 199812 Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 2/98
GVT7132B36
32K X 36 SYNCHRONOUS BURST SRAM
GALVANTECH, INC.
100 Pin PQFP Package Dimensions
20.00 + 0.10
23.20 +
0.30
14.00 + 0.10
17.20 + 0.30
# 1
Note: All dimensions in Millimeters
0.30 + 0.100.65 Basic
2.80 + 0.25
February 6, 199813 Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 2/98
GVT7132B36
32K X 36 SYNCHRONOUS BURST SRAM
GALVANTECH, INC.
100 Pin TQFP Package Dimensions
20.00 + 0.10
22.00 +
0.10
14.00 + 0.10
16.00 + 0.10
# 1
Note: All dimensions in Millimeters
0.30 + 0.080.65 Basic
1.40 + 0.05
February 6, 199814 Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 2/98
GVT7132B36
32K X 36 SYNCHRONOUS BURST SRAM
GALVANTECH, INC.
Ordering Information
GVT 7132B36 X - XX
Galvantech Prefix
Part Number
Package (Q = 100 PIN PQFP,
Speed (9 = 9ns access/15ns cycle
T = 100 PIN TQFP)
10 = 10ns access/15ns cycle
12 = 12ns access/20ns cycle)
