DS027 (v3.5) June 25, 2008 www.xilinx.com
Product Specification 1
© Copy right 199 8-2008 Xilinx, Inc. XILINX, the Xilinx logo, Virtex , Spartan, ISE and other designat ed brands included herein are trademarks of Xilinx in the United States and
other countries. All other trademarks are the property of their respective owners.
Features
•One-time programmable (OTP) read-only memory
designed to store configuration bitstreams of Xilinx®
FPGAs
•Simple interface to the FPGA; requires only one user
I/O pin
•Cascadable for storing longer or multiple bitstreams
•Programmable reset polarity (act ive High or active
Low) for compatibility with different FPGA solutions
•XC17128E/EL, XC17256E/EL, XC170 1, and XC1 700 L
series support fast configuration
•Low-power CMOS floating-gate process
•XC1700E series are availabl e in 5V and 3.3V versions
•XC1700L series are available in 3.3V only
•Available in compact plastic packages: 8-pin SOIC, 8-
pin VOIC, 8-pin PDIP, 20-pin SOIC, 20-pin PLCC, 44-
pin PLCC or 44-pin VQFP
•Programming support by leading programmer
manufacturers
•Design support using the Xilinx Alliance and
Foundation™ software packages
•Guaranteed 20 year life data retention
•Lead-free (Pb-free) packaging available
Description
The XC1700 family of configuration PROMs provides an
easy-to-use, cost-effective method for storing large Xilinx
FPGA configuration bitstreams. Se e Figure 1 for a
simplified block diagram.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after t he rising clock edge , data appe ars on the PR OM
D ATA output pin that is connected t o the FPGA DIN pin. The
FPGA gener ates the app ropriate num ber of cloc k p ulses to
complete the configur ation. Aft er configu red, it disab les the
PROM . When the FPGA is in Sla ve Serial mode , the PR OM
and the FPGA must both be clo cked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascade d with oth er mem b er s of th e family.
For device programming, either the Xilinx Alliance or
Foundation software compiles the FPGA design file into a
standard Hex format, which is then transferred to most
commercial PROM programmers.
<
B
LXC1700E, XC1700EL, and XC1700L
Series Configuration PROMs
DS027 (v3.5) June 25, 2008 8Product Specification
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X-Ref Target - Figure 1
Figure 1: Simplified Block Diagram (Does Not Show Programming Circuit)
EPROM
Cell
Matrix
Address Counter
CE
DATA
OE
Output
CLK
VCC VPP GND
DS027_01_021500
TC
OE
RESET/
OE/
RESET
or CEO
Product Obsolete or Under Obsolescence
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
DS027 (v3.5) June 25, 2008 www.xilinx.com
Product Specification 2
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Pin Description
DATA
Data output is in a h igh-impedance stat e when either CE or
OE are inactive. During programming, the DATA pin is I/O.
Note that OE can be programmed to be either active High or
active Low.
CLK
Each rising edge on the CLK input increments the int ernal
address counter, if both CE and OE are active.
RESET/OE
When High, this input holds the address counter reset and
puts the DATA output in a high-impedance st ate. The
polarity of this input pin is programmable as either
RESET/OE or OE/RESET. To avoid confusion, this
document describes the pin as RESET/OE, although the
opposite polarity is possible on all de vices. When RESET is
activ e, the address counter is held at "0", and puts the D ATA
output in a high-impedance state. The polarity of this input
is programmable. The def ault is active High RESET, but the
preferred option is active Low RESET, because it can be
driven by the FPGAs INIT pin.
The polarity of this pin is controlled in the programmer
interface. This input pin is easily inverted using the Xilinx
HW-130 Programmer. Third-party programmers have
different methods to invert this pin.
CE
When High, this pin disables the internal address counter,
puts the D ATA outp ut in a high- impedance sta te, a nd f orces
the device into low-ICC standby mode.
CEO
Chip Enable output, to be connected to the CE input of the next
PROM in the daisy chain. This output is Low when the CE and
OE inputs are both active AND the internal address counter
has been incremented beyond its Terminal Count (TC) value .
In other words: when the PROM has been read, CEO follows
CE as long as OE is active. When OE goes inactiv e , CEO
sta ys High until the PROM is reset. Note that OE can be
programmed to be either activ e High or active Lo w.
VPP
Programming voltage . No overshoot above the specified
max v oltage is permitted on this pin. For normal read
operation, this pin must be connected to VCC. Failure to do
so may lead to unpredictable, te mperature-dependent
operation a nd se v ere prob lems in circuit deb ugging. Do not
leave VPP floating!
VCC and GND
Positive supply and ground pins.
PROM Pinouts
Pins not listed are "no connects."
"
Capacity
Pin Name
8-pin
PDIP
(PD8/
PDG8)
SOIC
(SO8/
SOG8)
VOIC
(VO8/
VOG8)
20-pin
SOIC
(SO20)
20-pin
PLCC
(PC20/
PCG20)
44-pin
VQFP
(VQ44)
44-pin
PLCC
(PC44)
DATA 1 1 2 40 2
CLK 2 3 4 43 5
RESET/OE
(OE/RESET)3861319
CE 4 10 8 15 21
GND 5 11 10 18, 41 24, 3
CEO 6 13 14 21 27
VPP 718173541
VCC 820203844
Devices Configuration Bits
XC1704L 4,194,304
XC1702L 2,097,152
XC1701/L 1,048,576
XC17512L 524,288
XC1736E 36,288
XC1765E/EL 65,536
XC17128E/EL 131,072
XC17256E/EL 262,144
Product Obsolete or Under Obsolescence
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
DS027 (v3.5) June 25, 2008 www.xilinx.com
Product Specification 3
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Pinout Diagrams
6
5
4
3
2
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
7
8
9
10
11
12
13
14
15
16
17
PC44
Top Vie w
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
RESET/OE
NC
CE
NC
NC
GND
NC
NC
CEO
NC
NC
CLK
NC
GND
DATA(D0)
NC
VCC
NC
NC
VPP
NC
DS027_05_090602
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
PD8/PDG8
VO8/VOG8
SO8/SOG8
Top View
DS027_06_060705
VCC
VPP
CEO
GND
DATA(D0)
CLK
OE/RESET
CE
8
7
6
5
1
2
3
4
VQ44
Top Vie w
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
RESET/OE
NC
CE
NC
NC
GND
NC
NC
CEO
NC
NC
CLK
NC
GND
DATA(D0)
NC
VCC
NC
NC
VPP
NC
DS027_07_090602
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
DS027_08_110102
SO20
Top
View
VCC
NC
VPP
NC
NC
NC
NC
CEO
NC
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DATA(D0)
NC
CLK
NC
NC
NC
NC
OE/RESET
NC
CE
PC20/PCG20
Top View
DS027_09_060705
3
2
1
20
19
18
17
16
15
14
9
10
11
12
13
4
5
6
7
8
NC
DATA(D0)
NC
VCC
NC
NC
VPP
NC
NC
CEO
NC
GND
NC
NC
NC
CLK
NC
OE/RESET
NC
CE
Pinout Diagrams
6
5
4
3
2
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
7
8
9
10
11
12
13
14
15
16
17
PC44
Top Vie w
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
RESET/OE
NC
CE
NC
NC
GND
NC
NC
CEO
NC
NC
CLK
NC
GND
DATA(D0)
NC
VCC
NC
NC
VPP
NC
DS027_05_090602
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
PD8/PDG8
VO8/VOG8
SO8/SOG8
Top View
DS027_06_060705
VCC
VPP
CEO
GND
DATA(D0)
CLK
OE/RESET
CE
8
7
6
5
1
2
3
4
VQ44
Top Vie w
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
RESET/OE
NC
CE
NC
NC
GND
NC
NC
CEO
NC
NC
CLK
NC
GND
DATA(D0)
NC
VCC
NC
NC
VPP
NC
DS027_07_090602
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
DS027_08_110102
SO20
Top
View
VCC
NC
VPP
NC
NC
NC
NC
CEO
NC
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DATA(D0)
NC
CLK
NC
NC
NC
NC
OE/RESET
NC
CE
PC20/PCG20
Top View
DS027_09_060705
3
2
1
20
19
18
17
16
15
14
9
10
11
12
13
4
5
6
7
8
NC
DATA(D0)
NC
VCC
NC
NC
VPP
NC
NC
CEO
NC
GND
NC
NC
NC
CLK
NC
OE/RESET
NC
CE
Product Obsolete or Under Obsolescence
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
DS027 (v3.5) June 25, 2008 www.xilinx.com
Product Specification 4
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Xilinx FPGAs and Compatible PROMs
Controlling PROMs
Connecting the FPGA de vice with the PROM:
•The DATA output(s) of the of the PROM(s) drives the
DIN input of the lead FPGA device.
•The Master FPGA CCLK out put drives the CLK input(s)
of the PROM(s).
•The CEO output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
•The RESET/OE input of all PROMs is best driven by
the INIT output of the lead FPGA device. This
connection assures that the PROM address counter is
reset before the start of any (re)configuration, even
when a reconfiguration is initiated by a VCC glitch.
Other methods—such as driving RESET/OE from LDC
or system reset—assume the PROM internal power-
on-reset is always in step with the FPGA’s internal
power-on-reset. This may not be a safe assumption.
•The PROM CE inpu t can be driven from eit her the LDC
or DONE pins. Using LDC avoids potenti al contention
on the DIN pin.
•The CE input of the lead (or only) PROM is driven by
the DONE output of the lead FPGA device, provided
that DONE is not permanently grounded. Otherwise,
LDC can be used to drive CE, but must then be
unconditionally High during user operation. CE can
also be permanently tied Low, but this keeps the DATA
output active and causes an unnecessary supply
current of 10 mA maximum.
Device Configuration
Bits PROM
XC4003E 53,984 XC17128E(1)
XC4005E 95,008 XC17128E
XC4006E 119,840 XC17128E
XC4008E 147,552 XC17256E
XC4010E 178,144 XC17256E
XC4013E 247,968 XC17256E
XC4020E 329,312 XC1701
XC4025E 422,176 XC1701
XC4002XL 61,100 XC17128EL(1)
XC4005XL 151,960 XC17256EL
XC4010XL 283,424 XC17512L
XC4013XL/XLA 393,632 XC17512L
XC4020XL/XLA 521,880 XC17512L
XC4028XL/XLA 668,184 XC1701L
XC4028EX 668,184 XC1701
XC4036EX/XL/XLA 832,528 XC1701L
XC4036EX 832,528 XC1701
XC4044XL/XLA 1,014,928 XC1701L
XC4052XL/XLA 1,215,368 XC1702L
XC4062XL/XLA 1,433,864 XC1702L
XC4085XL/XLA 1,924,992 XC1702L
XC40110XV 2,686,136 XC1704L
XC40150XV 3,373,448 XC1704L
XC40200XV 4,551,056 XC1704L +
XC17512L
XC40250XV 5,433,888 XC1704L+
XC1702L
XC5202 42,416 XC1765E
XC5204 70,704 XC17128E
XC5206 106,288 XC17128E
XC5210 165,488 XC17256E
XC5215 237,744 XC17256E
XCV50 559,200 XC1701L
XCV100 781,216 XC1701L
XCV150 1,040,096 XC1701L
XCV200 1,335,840 XC1702L
XCV300 1,751,808 XC1702L
XCV400 2,546,048 XC1704L
XCV600 3,607,968 XC1704L
XCV800 4,715,616 XC1704L +
XC1701L
XCV1000 6,127,744 XC1704L +
XC1702L
XCV50E 630,048 XC1701L
XCV100E 863,840 XC1701L
XCV200E 1,442,016 XC1702L
XCV300E 1,875,648 XC1702L
XCV400E 2,693,440 XC1704L
XCV405E 3,340,400 XC1704L
XCV600E 3,961,632 XC1704L
XCV812E 6,519,648 2 of XC1704L
XCV1000E 6,587,520 2 of XC1704L
XCV1600E 8,308,992 2 of XC1704L
XCV2000E 10,159,648 3 of XC1704L
XCV2600E 12,922,336 4 of XC1704L
XCV3200E 16,283,712 4 of XC1704L
Notes:
1. The suggested PROM is determined by compatibility with the
higher configuration frequency of the Xilinx FPGA CCLK.
Designers using the default slow configuration frequency (CCLK)
can use the XC1 765E or XC1765EL f or the noted FPGA de vices .
Device Configuration
Bits PROM
Product Obsolete or Under Obsolescence
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
DS027 (v3.5) June 25, 2008 www.xilinx.com
Product Specification 5
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FPGA Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block
(CLB) and their associated interconnections are established
by a configur ation prog r am. The prog ram is loaded either
automatically upon pow er up, or on command, depending on
the state of the th ree FPGA mode pins. In Master Serial
mode, the FPGA automat ically load s the con figuration
program from an external memory. The Xilinx PROMs ha v e
been designed for compatibility with the Master Serial mode.
Upon pow er-up or reconfigur ation, an FPGA enters th e
Master Serial mode whenever all three of the FPGA mode -
select pins are Low (M0=0, M1=0, M2=0). Data is read from
the PROM sequentially on a single data line. Synchronization
is provided b y the rising edge of the temporary signal CCLK,
which is generated during configuration.
Master Serial Mode provides a simple configuration interface.
Only a serial data line and two control lines are required to
configure an FPGA. Data from the PROM is read sequentially,
accessed via the internal address and bit counters which are
incremented on every valid rising edge of CCLK.
If the user-programmable, dual-function DIN pin on the
FPGA is used only for configur ation, it must still be held at a
defined level during normal operation. The Xilinx FPGA
fa milies take care of this automatically with an on-chip
default pull-up resistor.
Programming the FPGA With Counters
Unchanged upon Completion
When multiple FPGA-configurations for a single FPGA are
stored in a PROM, the OE pin should be tied Low. Upon
power-up , the internal address counters are reset and
configuration begins with the first program stored in
memory. Since the OE pin is held Low, the address
counters are left unchange d after configuration is complete .
Therefore, to re program the FPGA with another program,
the DONE line is pulled Lo w and configuration begins at the
last value of the address counters.
This method f ails if a user applies RESET during the FPGA
configuration process. The FPGA aborts the configuration
and then restarts a new configuration, as intended, but the
PROM does not reset its address counter, since it never
saw a High level on its OE input . The new conf iguration,
therefore, reads the remaining data in the PROM and
interprets it as preamble, length count etc. Since the FPGA
is the master, it issues th e necessary number of CCLK
pulses, up to 16 million (224) and DONE goes High.
Howe ver , the FPGA configuration is then completely wrong,
with potential contentions inside the FPGA and on its output
pins. This method must, therefore, never be used when
there is an y chance of external reset during configuration.
Cascading Configuration PROMs
For multiple FPGAs configured as a daisy-ch ain, or for
future FPGAs requiring larger configuration memories,
cascaded PROMs pr ovide additiona l memory. After the last
bit from the first PROM is read, the next clock signal to the
PROM asserts its CEO output Low and disables its DATA
line. The second PR OM recogniz es the Lo w le vel on its CE
input and enables its DATA output. See Figure 2, page 6.
After configuration is complete, the address counters of
all cascaded PROMs are reset if the FPGA RESET pin
goes Low, assuming the PROM reset polarity option has
been inver ted.
To reprogram the FPGA with another program, the DONE
line goes Low and configuration begins where the address
counters had stopped. In this case, avoid contention
between DATA and the configured I/O use of DIN.
Standby Mode
The PROM enters a low-power standby mode whenever CE
is asserted High. The output remains in a high-impedance
state regardless of the state of the OE input.
Programming
The devices can be programmed on programmers supplied
by Xilinx or qualified third-party vendors. The user must
ensure that t he appropriate progr amming algorithm and the
latest version of the programmer software are used. The
wrong choice can permanently damage the device.
Table 1: Truth Table for XC1700 Control Inputs
Control Inputs Internal Address Outputs
RESET CE DATA CEO ICC
Inactive Low If address < TC(1): increment
If address > TC(2): don’t change Active
High-Z High
Low Active
Reduced
Active Low Held reset High-Z High Active
Inactive High Not changing High-Z(3) High Standby
Active High Held reset High-Z(3) High Standby
Notes:
1. The XC1700 RESET input has programmable polarity.
2. TC = Terminal Count = highest address value. TC + 1 = address 0.
3. Pull DATA pin to GND or VCC to meet ICCS standby current.
Product Obsolete or Under Obsolescence
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
DS027 (v3.5) June 25, 2008 www.xilinx.com
Product Specification 6
R
X-Ref Target - Figure 2
Figure 2: Master Serial Mode
Product Obsolete or Under Obsolescence
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
DS027 (v3.5) June 25, 2008 www.xilinx.com
Product Specification 7
R
XC1701, XC1736E, XC1765E, XC17128E and XC17256E
Absolute Maximum Ratings
Operating Conditions (5V Supply)
DC Characteristics Over Operating Condition
Symbol Description Conditions Units
VCC Supply voltage relative to GND –0.5 to +7.0 V
VPP Supply voltage relative to GND –0.5 to +12.5 V
VIN Input voltage relative to GND –0.5 to VCC +0.5 V
VTS Voltage applied to High -Z output –0.5 to VCC +0.5 V
TSTG Storage temperature (ambient) –65 to +150 °C
TJJunction temperature +125 °C
Notes:
1. Stresses be yond those li sted under Absolute Max imum Ratings ma y cause permanent damage to the de vice . These are stress ra tings only,
and functional operation of th e device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Symbol Description Min Max Units
VCC(1) Supply vo ltage relative to GND (TA = 0°C to +70°C) Commercial 4.750 5.25 V
Supply voltage relative to GND (TA = –40°C to +85°C) Industrial 4.50 5.50 V
Notes:
1. During normal read operation VPP must be connect to VCC.
Symbol Description Min Max Units
VIH High-level input voltage 2 VCC V
VIL Low-level input voltage 0 0.8 V
VOH High-level output voltage (IOH = –4 mA) Commercial 3.86 – V
VOL Low-level output voltage (IOL = +4 mA) – 0.32 V
VOH High-level output voltage (IOH = –4 mA) Industrial 3.76 – V
VOL Low-level output voltage (IOL = +4 mA) – 0.37 V
ICCA Supply current, active mode at maximum frequency
(XC1736E, XC1765E, XC17128E, and XC17256E) –10mA
ICCA Supply current, active mode at maximum frequency
(XC1701) –20mA
ICCS Supply current, standby mode
(XC1736E, XC1765E, XC17128E, and XC17256E) –50
(1) μA
ICCS Supply current, standby mode
(XC1701) –100
(1) μA
ILInput or output leakage current –10 10 μA
CIN Input capacitance (VIN = GND, f = 1.0 MHz) – 10 pF
COUT Output capacitance (VIN = GND, f = 1.0 MHz) – 10 pF
Notes:
1. ICCS standby current is specified for DATA pin that is pulled to VCC or GND.
Product Obsolete or Under Obsolescence
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
DS027 (v3.5) June 25, 2008 www.xilinx.com
Product Specification 8
R
XC1704L, XC1702L, XC1701L, XC17512L, XC1765EL, XC17128EL and XC17256EL
Absolute Maximum Ratings
Operating Conditions (3V Supply)
DC Characteristics Over Operating Condition
Symbol Description Conditions Units
VCC Supply voltage relative to GND –0.5 to +7.0 V
VPP Supply voltage relative to GND –0.5 to +12.5 V
VIN Input voltage relative to GND –0.5 to VCC +0.5 V
VTS Voltage applied to High -Z output –0.5 to VCC +0.5 V
TSTG Storage temperature (ambient) –65 to +150 °C
Notes:
1. Stresses be yond those li sted under Absolute Max imum Ratings ma y cause permanent damage to the de vice . These are stress ra tings only,
and functional operation of th e device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Symbol Description Min Max Units
VCC(1) Supply vo ltage relative to GND (TA = 0°C to +70°C) Commercial 3.0 3.6 V
Supply voltage relative to GND (TA = –40°C to +85°C) Industrial 3.0 3.6 V
Notes:
1. During normal read operation VPP must be connect to VCC.
Symbol Description Min Max Units
VIH High-level input voltage 2 VCC V
VIL Low-level input voltage 0 0.8 V
VOH High-level output voltage (IOH = –3 mA) 2.4 – V
VOL Low-level output voltage (IOL = +3 mA) – 0.4 V
ICCA Supply current, active mode (at maximum frequency) (XC1700L) – 10 mA
ICCA Supply current, active mode (at maximum frequency)
(XC1765EL, XC17128EL, XC17256EL) –5mA
ICCS Supply current, standby mode
(XC1701L, XC17512L, XC17256L, X1765EL, XC17128EL) –50
(1) μA
ICCS Supply current, standby mode (XC1702L, XC1704L) – 350(1) μA
ILInput or output leakage current –10 10 μA
CIN Input capacitance (VIN = GND, f = 1.0 MHz) – 10 pF
COUT Output capacitance (VIN = GND, f = 1.0 MHz) – 10 pF
Notes:
1. ICCS standby current is specified for DATA pin that is pulled to VCC or GND.
Product Obsolete or Under Obsolescence
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
DS027 (v3.5) June 25, 2008 www.xilinx.com
Product Specification 9
R
AC Characteristics Over Operating Condition
Symbol Description
XC1701,
XC17128E,
XC17256E
XC17128EL,
XC17256EL,
XC1704L,
XC1702L,
XC1701L,
XC17512L
XC1736E,
XC1765E XC1765EL Units
Min Max Min Max Min Max Min Max
TOE OE to data delay – 25 – 30 – 45 – 40 ns
TCE CE to data delay – 45 – 45 – 60 – 60 ns
TCAC CLK to data delay – 45 – 45 – 80 – 200 ns
TDF CE or OE to data float delay(2,3) –50– 50–50–50ns
TOH Data ho ld from CE, OE, or CLK(3) 0–0 –0–0–ns
TCYC Clock periods 67 – 67 – 100 – 400 – ns
TLC CLK Low time(3) 20 – 25 – 50 – 100 – ns
THC CLK High time(3) 20 – 25 – 50 – 100 – ns
TSCE CE setup time to CLK
(to guarantee proper counting) 20 – 25 – 25 – 40 – ns
THCE CE hold time to CLK
(to guarantee proper counting) 0–0 –0–0–ns
THOE OE hold time
(guarantees counters are reset) 20 – 25 – 100 – 100 – ns
Notes:
1. AC test load = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
RESET/OE
CE
CLK
DATA TCE
TOE
TLC
TSCE TSCE THCE
THOE
TCAC TOH TDF
TOH
THC
DS027_03_021500
TCYC
Product Obsolete or Under Obsolescence
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
DS027 (v3.5) June 25, 2008 www.xilinx.com
Product Specification 10
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AC Characteristics Over Operating Condition When Cascading
Symbol Description
XC1701,
XC17128E,
XC17256E,
XC1704L,
XC1702L
XC17128EL,
XC17256EL,
XC1701L,
XC17512L
XC1736E,
XC1765E XC1765EL Units
Min Max Min Max Min Max Min Max
TCDF CLK to data float delay(2,3) –50–50–50–50ns
TOCK CLK to CEO delay(3) –30–30–30–30ns
TOCE CE to CEO delay(3) –35–35–35–35ns
TOOE RESET/OE to CEO delay(3) –30–30–30–30ns
TCCE CE to data delay when cascading – 45 – 90 – 60 – 110 ns
Notes:
1. AC test load = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
5. For cascaded PROMs:
- TCYC min = TOCK + TCCE + FPGA data setup time (TDCC/TDSCK).
Example: If the XC1701L is cascaded to configure an FPGA TDCC = 5 sec, then the actual TCYC min = 30 ns + 90 ns + 5 ns = 125 ns,
or max CLK frequency = 8 MHz.
- TCAC max = TOCK + TCCE.
Example: For the XC1701L when cascading, the actual TCAC max = 30 ns + 90 ns = 120 ns.
RESET/OE
CLK
DATA
(First PROM)
DATA
(Cascaded
PROM)
CE
CEO
(First PROM)
CE
(Cascaded
PROM)
Last
Bit
Last
Bit
First
Bit
First
Bit
DS027_04_071204
nnn
+1
n
–1
TCDF
TOOE TOCK TOCE TOCE
TCCE
TCCE
Product Obsolete or Under Obsolescence
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
DS027 (v3.5) June 25, 2008 www.xilinx.com
Product Specification 11
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Ordering Information
Valid Ordering Combinations
XC1736EPD8C XC1765EPD8C XC17128EPD8C XC17256EPD8C XC1701PD8C XC1702LVQ44C
XC1736EPDG8C XC1765EPDG8C XC17128EPDG8C XC17256EPDG8C XC1701PC20C XC1702LPC44C
XC1736ESO8C XC1765ESO8C XC17128EVO8C XC17256EVO8C XC1701SO20C XC1704LVQ44C
XC1736ESOG8C XC1765ESOG8C XC17128EVOG8C XC17256EPC20C XC1701PD8I XC1704LPC44C
XC1736EVO8C XC1765EVO8C XC17128EPC20C XC17256EPCG20C
XC1736EVOG8C XC1765EPC20C XC17128EPCG20C
XC1736EPC20C XC17128EPD8I
XC1736EPD8I XC1765EPD8I XC17128EVO8I XC17256EPD8I XC1701PC20I XC1702LVQ44I
XC1736ESO8I XC1765ESO8I XC17128EPC20I XC17256EVO8I XC1701SO20I XC1702LPC44I
XC1736EVO8I XC1765EVO8I XC17256EPC20I XC1704LVQ44I
XC1736EPC20I XC1765EPC20I XC1704LPC44I
XC1765ELPD8C XC17128ELPD8C XC17256ELPD8C XC1701LPD8C XC17512LPD8C
XC1765ELSO8C XC17128ELVO8C XC17256ELVO8C XC1701LPDG8C XC17512LPC20C
XC1765ELSOG8C XC17128ELPC20C XC17256ELPC20C XC1701LPC20C XC17512LSO20C
XC1765ELVO8C XC17128ELPD8I XC17256ELPD8I XC1701LPCG20C XC17512LPD8I
XC1765ELVOG8C XC17128ELVO8I XC17256ELVO8I XC1701LSO20C XC17512LPC20I
XC1765ELPC20C XC17128ELPC20I XC17256ELPC20I XC1701LPD8I XC17512LSO20I
XC1765ELPD8I XC1701LPDG8I
XC1765ELSO8I XC1701LPC20I
XC1765ELVO8I XC1701LPCG20I
XC1765ELPC20I XC1701LSO20I
XC1701L PC20 C
Operating Range/Processing
C = Commercial (TA = 0° to +70°C)
I = Industrial (TA = –40° to +85°C)
Package Type(1)
PD8/PDG8 = 8-pin Plastic DIP
SO8/SOG8 = 8-pin Plastic Small-Outline Package
V O8/VOG8 = 8-pin Plastic Small -Outline Thin Pack age
SO20 = 20-pin Plastic Small-Outline Package
PC20/PCG20 = 20-pin Plastic Leaded Chip Carrier
VQ44 = 44-pin Plastic Quad Flat Package
PC44 = 44-pin Plastic Chip Carrier
Device Number
XC1736E
XC1765E
XC1765EL
XC17128E
XC17128EL
XC17256E
XC17256EL
XC17512L
XC1701
XC1701L
XC1704L
XC1702L
Notes:
1. G in the package-type codes designates Pb-free packaging.
Product Obsolete or Under Obsolescence
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
DS027 (v3.5) June 25, 2008 www.xilinx.com
Product Specification 12
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Marking Information
Due to the small size of the commerc ial s erial PROM packages, the complete ordering part number cannot be m arked on
the package. The XC prefix is deleted and t he package code is simplified. Device marking is as follows:
Revision History
The following tab le shows the revision history for this document.
.Date Version Revision
7/14/98 1.1 Major revisions to include the XC1704L, XC1702L, and the XQ1701L devices, pac kages and operating
conditions. Also revised the timing specifications under "AC Characteristics Over Operating Condition,"
page 9.
9/8/98 2.0 Re vised the marking information for the VQ44. Updated "DC Characteristics Over Operating Condition,"
page 7. Added references to the XC4000XLA and XC4000XV families in "Xilinx FPGAs and Compatible
PROMs , " page 4 and Figure 2, page 6.
12/18/98 2.1 Added Virtex® FPGAs to "Xilinx FPGAs and Compatible PROMs," page 4. Added the PC44 package f or
the XC1702L and XC1704L products.
1/27/99 2.2 Changed Military ICCS.
7/8/99 2.3 Changed ICCS standby on XC1702/XC1704 from 50 μA to 300 μA.
3/30/00 3.0 Combined data sheets XC1700E and XC1700L. Added DS027, removed Military Specs. Added Virtex-
E and EM references.
07/05/00 3.1 Added 4.7K resistor to Figure 2, updated format.
09/07/04 3.2 •Updated "Xilinx FPGAs and Compatible PR OMs," page 4 and "Absolute Maximum Ratings," page 7.
Added "Pinout Diagrams," page 3.
•Added footnote to table in "AC Characteristics Over Operating Condition When Cascading," page 10,
defining TCCE when cascading, and redrew associated timing diagram.
Notes:
1. When marking the device number on the EL parts, an X is used in place of an EL.
2. For XC1700E/EL only.
3. For XC1700L only.
1701L J C
Operating Range/Processing
C=Commercial (T
A = 0° to +70°C)
I = Industrial (TA = –40° to +85°C)
Package Type
P = 8-pin Plastic DIP
H = 8-pin Plastic DIP, Pb-Free
S(2) = 8-pin Plastic Small-Outline Package
O = 8-pin Plastic Small-Outline Package, Pb-Free
V = 8-pin Plastic Small-Outline Thin Package
G = 8-pin Plastic Small-Outlin e Th i n Pac kag e, Pb-Free
S(3) = 20-pin Plastic Small-Outline Package
J = 20-pin Plastic Leaded Chip Carrier
E = 20-pin Plastic Leaded Chip Carrier, Pb-Free
VQ44 = 44-pin Plastic Quad Flat Package
PC44 = 44-pin Plastic Chip Carrier
Device Number
1736E
1765E
1765X(1)
17128E
17128X(1)
17256E
17256X(1)
1704L
1702L
1701
1701L
17512L
Product Obsolete or Under Obsolescence
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
DS027 (v3.5) June 25, 2008 www.xilinx.com
Product Specification 13
R
Notice of Disclaimer
THE XILINX HARD WARE FPGA AND CPLD DEVICES REFERRED T O HEREIN (“PR O DUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
W ARRANTY DOES NO T EXTEND T O ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NO T WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
06/13/05 3.3 •Changed pinout diagrams to include Pb-free packages on "Pinout Diagrams," page 3.
•Deleted TSOL from the under "Absolute Maximum Ratings," page 7.
•Added V OG8 and PCG20 to "Ordering Information," page 11. Added XC1765ELV OG8C and
XC17256EPCG20 to "Valid Ordering Combinations," page 11. Added new packages types under
"Marking Information," page 12.
07/09/07 3.4 •Added Pb-free packages to "PROM Pinouts," page 2.
•Note added to Table 1, page 5.
•Under "XC1701, XC1736E, XC1765E, XC17128E and XC17256E", note added to "DC
Characteristics Over Operating Condition," page 7 and corrected XC1701 ICCA value.
•Under "XC1704L, XC1702L, XC1701L, XC17512L, XC1765EL, XC17128EL and XC17256EL", note
added to "DC Characteristics Over Operating Condition," page 8.
•Added SOG package to "Ordering Information," page 11.
•Added Pb-free order codes to "Valid Ordering Combinations," page 11.
•Added package type E to "Marking Information," page 12.
06/25/08 3.5 •Updated "Absolute Maximum Ratings," page 7, added juncti on temperature rating.
•Updated document template.
•Updated copyright statement.
•Added "Notice of Disclaimer," page 13.
Product Obsolete or Under Obsolescence