Rev 1.0/ Aug. 2010 1
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
64Gb Flash
H27UCG8T2M
Rev 1.0 / Aug. 2010 2
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
Document Title
64Gbit (8192 M x 8 bit) NAND Flash Memory
Revision History
Revision
No. History Draft Date Remark
0.0 Initial Draft. Apr. 27. 2010 Preliminary
1.0 Finalize Aug. 17. 2010 Advanced
Rev 1.0 / Aug. 2010 3
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
Product Feature
■ Open NAND Flash Interface (ONFI) 1.0
Compliant
■ Supports only asynchronous interface
■ Multilevel Cell(MLC) technology
■ Device size
- 64 Gbit = 4,096 blocks
■ Organization
- Page size : 8,640 Bytes(8,192+448 bytes)
- Block size : 256 pages(2M+112K bytes)
- Plane size : 2,048 blocks
- Chip size : 2 planes (4,096 blocks)
■ Supply Voltage
- 3.3V device : Vcc = 2.7 V ~ 3.6 V
■ Read Time
- Random Access (tR): 200 ㎲ (Max.)
- Sequential Access : 20 ㎱ (Min.)
■ Write Time
- Page program : 1600 ㎲ (Typ.)
- Block erase : 3.5 ㎳ (Typ.)
■ Package Information
- Package type : VLGA
- Chip count : SDP(1CE, Single) = 1 stack
- Ball(Pin) Count : 52 ball
- size : 14mm x 18mm x 1mm
■ Endurance:
- 1,000 PROGRAM/ERASE cycles
- Data Retention: 10 years
■ Operating Temperature:
- 0°C to +70°C (Commercial)
- -25°C to +85°C (Extended)
- -40°C to +85°C (Industrial)
Rev 1.0 / Aug. 2010 4
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
1. SUMMARY DESCRIPTION
The product part NO.H27UCG8T2YR-BC is a single 3.3V 64Gbit NAND flash memory. The Device contains 2 planes in a sin-
gle die. Each plane is made up of the 2,048 blocks. Each block consists of 256 programmable pages. Each page contains
8,640 bytes. The pages are subdivided into an 8,192-byte main data storage area with a spare 448-byte district.
Page program operation can be performed in typical 1,600us, and a single block can be erased in typical 3.5ms.
1.1. Product List
Table 1
PART NUMBER DENSITY # of CE#
And R/B# PACKAGE Device ID
H27UCG8T2MYR 64Gb 1 52-LGA AD-DE-94-D2-04-43
Rev 1.0 / Aug. 2010 5
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
1.2. PIN DESCRIPTION
Note:
A 0.1uF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple the
current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during pro
gram and erase operations.
Pin Name Description
I/O0-I/O7
DATA INPUTS/OUTPUTS
The I/O pins is used to COMMAND LATCH cycle, ADDRESS INPUT cycle, and DATA in-out cycles during
read / write operations. The I/O pins float to High-Z when the device is deselected or the outputs are
disabled.
CLE
COMMAND LATCH ENABLE
This input activates the latching of the I/O inputs inside the Command Register on the Rising edge of Write
Enable (WE#).
ALE
ADDRESS LATCH ENABLE
This input activates the latching of the I/O inputs inside the Address Register on the Rising edge of Write
Enable (WE#).
CE#
CHIP ENABLE
This input controls the selection of the device. When the device is busy, CE# low does not deselect the
memory. The device goes into Stand-by mode when CE# goes High during the device is in Ready state.
The CE# signal is ignored when device is in Busy state, and will not enter Standby mode even if the CE#
goes high.
WE#
WRITE ENABLE
This input acts as clock to latch Command, Address and Data. The I/O inputs are latched on the rise edge
of WE#.
RE#
READ ENABLE
The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data is
valid tREA after the falling edge of RE# which also increments the internal column address counter by one.
WP#
WRITE PROTECT
The WP# pin, when Low, provides a hardware protection against undesired write operations. Hardware
Write Protection is activated when the Write Protect pin is low. In this condition modify operation do not
start and the content of the memory is not altered. Write Protect pin is not latched by Write Enable to
ensure the protection even during the power up phases.
R/B# READY / BUSY
The Ready/Busy output is an Open Drain pin that signals the state of the memory.
VccQ SUPPLY VOLTAGE FOR I/O BUFFER
VssQ GROUND FOR I/O BUFFER
Vcc SUPPLY VOLTAGE
The VCC supplies the power for all the operations. (Read, Write, and Erase).
Vss GROUND
NC NO CONNECTED
Rev 1.0 / Aug. 2010 6
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
VCC
VSS
WP#
CLE
ALE
RE#
WE#
CE# I/O0~I/O7
R/B#
VCCQ
VSSQ
Pin Diagram
■Figure 1. Pin Diagram (SDP)
Rev 1.0 / Aug. 2010 7
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
A B C D E F G H J K L M N
OA OB OC OD OE OF
NC NC NC NC NC NC
NC RE# NC NC Vcc
NC
NC
Vcc NC IO7 Vcc
IO5
Vss
NC ALE NC NC VccQ
NC
NC
Vss NC IO1 Vss
IO3
WP#
CLE NC WE# IO2 NC
Vss
IO0
CE# NC R/B IO6 NC
IO4
NC
8
7
6
5
4
3
2
1
0
NC NC NC NC VssQ NC
Ball MAP(52-VLGA)
- RAW NAND PKG (Single channel)
Rev 1.0 / Aug. 2010 8
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
RAW NAND PKG (52-VLGA)
Rev 1.0 / Aug. 2010 9
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
X Decoder
Address
register
ALE
CLE
CE#
WE#
RE#
WP#
Command
Interface Logic
Program/Erase
Controller
HV generation
Y Decoder
Address
register
Command
register
IO Buffer & latch
X
D
E
C
O
D
E
R
NAND FLASH
Memory Array
1 Device =
(8,192 + 448) bytes x 256pages x 4096 blocks
= 70,778,880 kbits
Data Register & Sense Amp
Column Decoder
Vcc
Vss
Global data
buffer Output Driver
A14-A33
A0-A13
I/O<7:0>
1.3. Block Diagram
■Figure 2. Block diagram
Rev 1.0 / Aug. 2010 10
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
1.4. Array Organization
■Figure 3. Array organization
1.5. Addressing
Notes:
1. L must be set to Low.
2. The device ignores any additional address input cycle than required.
3. The Address consists of column address (A0~A13), page address (A14 ~ A21), plane address (A22), and
block address (A23 ~ the last address).
Bus cycle I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
1st Cycle A0 A1 A2 A3 A4 A5 A6 A7
2nd Cycle A8 A9 A10 A11 A12 A13 L(1) L(1)
3rd Cycle A14 A15 A16 A17 A18 A19 A20 A21
4th Cycle A22 A23 A24 A25 A26 A27 A28 A29
5th Cycle A30 A31 A32 A33 L(1) L(1) L(1) L(1)
Rev 1.0 / Aug. 2010 11
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
1.6. Command Set
FUNCTION 1st
Cycle
Number of
Address
cycles
Data
input
cycles
2nd
Cycle
Number
of
Address
cycles
Data
input
cycles
3rd
Cycle
Acceptable
command
during busy
PAGE READ 00h 5 - 30h - - - No
READ FOR COPY-BACK 00h 5 - 35h - - - No
RANDOM DATA OUTPUT1) 05h 2 - E0h - - - No
SINGLE/multi plane CACHE READ5) 31h - - - - - - No
SINGLE/multi plane CACHE READ END5) 3Fh - - - - - - No
READ ID 90h 1 - - - - - No
READ STATUS REGISTER 70h - - - - - - Yes
PAGE PGM (start) / CACHE PGM 5)(end) 80h 5 Yes 10h - - - No
RANDOM DATA INPUT 1) 85h 2 Yes - - - - No
COPY-BACK PGM 85h 5 option 10h - - - No
CACHE PGM (start) 5) 80h 5 Yes 15h - - - No
BLOCK ERASE 60h 3 - D0h - - - No
RESET FFh - - - - - Yes
multi plane PAGE READ 60h 3 - 60h 3 - 30h No
multi plane CACHE READ START5) 6) 60h 3 - 60h 3 - 33h No
multi plane READ FOR COPY-BACK 60h 3 - 60h 3 - 35h No
multi plane BLOCK ERASE 60h 3 - 60h 3 - D0h No
multi plane DATA OUTPUT 1) 3) 00h 5 - 05h 2 - E0h No
multi plane READ STATUS REGISTER 78h 3 - - - - - Yes
MULTI-PLANE READ STATUS REGISTER
(legacy) 75h - - ----Yes
multi plane PAGE PGM / multi plane
CACHE PGM (end) 80h 5 Yes 11h~81h2) 5 Yes 10h No
multi plane COPY-BACK PGM 85h 5 option 11h~81h2) 5 option 10h No
MULTI PLANE CACHE PGM (start) 5) 80h 5 Yes 11h~81h2) 5 Yes 15h No
CACHE READ ENHANCED 00h 5 - 31h - - - No
MULTI-PLANE CACHE READ ENHANCED 60h 3 - 60h 3 - 31h No
Rev 1.0 / Aug. 2010 12
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
Notes:
1. Random Data Input/Output must be performed in a selected page.
2. Any command between 11h and 81h is prohibited except 70h, 78h, 75h and FFh.
3. Multi Plane Random data-out must be used after Multi Plane read operations (Multi Plane Page Read, Multi Plane
Cache Read and Multi Plane Read for Copy Back).
4. Do not change Plane address order when using all Multi Plane operations.
5. All cache operation (cache program, cache read) is available only within a block.
6. It's possible to confirm the multi-plane cache read first step using both 30h and 33h.
Caution:
1. Any undefined command inputs are prohibited except for above command set.
2. Multi Plane page read, Multi Plane cache read, and Multi Plane read for copy-back must be used after Multi Plane
pro grammed page, Multi Plane cache program, and Multi Plane copy-back program.
1.7. Mode Selection
Notes:
1. X can be VIL or VIH. H = Logic level HIGH. L = Logic level LOW.
2. WP# should be biased to CMOS high or CMOS low for stand-by mode.
3. WE# and RE# during Read Busy must be keep on high to prevent unplanned command/address/data input or to
avert unintended data out. In this time, only Reset, Read Status, and Multi Plane Read Status can be inputted to
the device.
CLE ALE CE# WE# RE# WP# MODE
H L L H X
Read Mode
Command Input
L H L H X Address Input ( 5 Cycles )
H L L H H
Write Mode
Command Input
LH1) L H H Address Input ( 5 Cycles )
L L L H H Data Input
LL1) L H X Sequential Read and Data Output
X X X H3) H3) XDuring Read (Busy)
XX1) X X X H During Program (Busy)
X X X X X H During Erase (Busy)
X X X X X L Write Protect
X X H X X OV/Vcc2) Stand-By
Rev 1.0 / Aug. 2010 13
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
Start
Block No = 0
Read FFh
check column 8192
of the 1 st page
Last Block
End
Entry Bad Block
Fail
Fail
Pass
Yes
Block No. = Block No. + 1 Pass
No
Read FFh
check col. 8192
of the last page
1.8. Bad Block Management
Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the
blocks are valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit line and
common source line by a select transistor. The devices are supplied with all the locations inside valid blocks erased (FFh).
The Bad Block Information is written prior to shipping. Any block where the 1st Byte in the spare area of the First and
Last page does not contain FFh is a Bad Block. The Bad Block Information must be read before any erase is attempted as
the Bad Block Information may be erased. For the system to be able to recognize the Bad Blocks based on the original
information it is recommended to create a Bad Block table following the flowchart shown in Flow chart 1. The 1st block,
which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment.
■Flow chart 1. Bad block management flow chart
Notes:
1. Do not try to erase the detected bad blocks, because the bad block information will be lost.
2. Do not perform program and erase operation in invalid block, it is impossible to guarantee the input data
and to ensure that the function is normal.
Rev 1.0 / Aug. 2010 14
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
Block A Block B
Data Data
Failure
FFh FFh
Buffer memory
Controller
1 Page
st 1 Page
st
Nth Page Nth Page
(2)
(3)
1.9. Bad Block Replacement
This device may have the invalid blocks when shipped from factory. An invalid block is one that contains one or more
bad bits. Over the lifetime of the device additional Bad Blocks may develop. In this case, the block has to be replaced
by copying the data to a valid block. These additional Bad Blocks can be identified as attempts to program or erase
them will give errors in the Status Register.
The failure of a page program operation does not affect the data in other pages in the same block. Bad block can be
replaced by re-programming the current data and copying the rest of the replaced block to an available valid block.
Refer to Table 2 and Figure 4 for the recommended procedure to follow if an error occurs during an operation.
Table 2. Block failure
■Figure 4. Block replacement
Notes:
1. An error occurs on nth page of the Block A during Program or Erase operation.
2. Data in Block A is copied to same location in Block B which is valid block.
3. Nth page of block A which is in controller buffer memory is copied into nth page of Block B.
4. Bad block table should be updated to prevent from erasing or programming Block A.
Operation Recommended Procedure
Erase Block Replacement
Program Block Replacement
Read ECC
Rev 1.0 / Aug. 2010 15
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
2. Electrical Characteristics
2.1. Valid Blocks
Notes:
1. The 1st block is guaranteed to be a valid block at the time of shipment.
2. This single device has a maximum of 96 invalid blocks.
3. Invalid blocks are one that contains one or more bad bits. The device may contain bad blocks upon shipment.
2.2. Absolute Maximum Rating
Notes:
1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute
Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or any other conditions above those indicated in the Operating sections of this
specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may
affect device reliability.
Refer also to the Hynix SURE Program and other relevant quality documents.
2. Minimum Voltage may undershoot to -2V during transition and for less than 20ns during transitions.
Symbol Min Typ Max Unit
Valid Block
Number NVB 4000 4096 Blocks
Symbol Parameter
Value
Unit
Min
TA
Ambient Operating Temperature
(Commercial Temperature Range) 0 to 70 °C
Ambient Operating Temperature
(Extended Temperature Range) -25 to 85 °C
Ambient Operating Temperature
(Industrial Temperature Range) -40 to 85 °C
TBIAS Temperature Under Bias -50 to 125 °C
TSTG Storage Temperature -65 to 150 °C
VIO Input or Output Voltage -0.6 to 4.6 V
VCC Supply Voltage -0.6 to 4.6 V
Rev 1.0 / Aug. 2010 16
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
2.3. DC and Operating Characteristics
Parameter Symbol Test
Conditions
HY27UCG8T2A
Unit3.3V
Min Typ Max
Power on reset current ICC0 FFh command input
after power on --
50per
device mA
Operating
Current
Read ICC1
tRC= tRC(min),
CE#=VIL,
IOUT=0 ㎃
--50
mA
Program ICC2 ---50
mA
Erase ICC3 ---50
mA
Stand-by Current (TTL) ICC4
CE#=VIH,
WP#=0V/VCC
-- 1
mA
Stand-by Current (CMOS) ICC5
CE#=VCC-0.2,
WP#=0V/VCC -1050
uA
Input Leakage Current ILI VIN=0 to VCC(MAX) --
±10 uA
Output Leakage Current ILO VOUT=0 to VCC(MAX) --
±10 uA
Input High Voltage VIH - Vccx0.8 - Vcc+0.3 V
Input Low Voltage VIL - -0.3 - 0.2x Vcc V
Output High Voltage VOH IOH=-400 ㎂2.4 - - V
Output Low Voltage VOL IOL=2.1 ㎃--0.4V
Output Low Current (R/B#) IOL(R/B#) VOL=0.4V 810 -mA
Rev 1.0 / Aug. 2010 17
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
2.4. AC Test Conditions
Notes:
1.These parameters are verified device characterization and are not 100% tested.
2.5. Pin Capacitance (TA=25°C, F=1.0㎒)
2.6. Program/ Read / Erase Characteristics
Notes:
1. Typical value is measured at VCC=3.3V, TA=25℃. Not 100% tested.
Parameter
Value
2.7V ≤ Vcc ≤ 3.6V
Input Pulse Levels 0 V to Vcc
Input Rise and Fall Times 5 ns
Input and Output Timing Levels Vcc /2
Output Load (2.7V-3.6V) 1 TTL GATE and CL=50pF
Symbol Parameter Test
Condition Min Max Unit
CIN Input Capacitance VIN = 0V -10
pF
CI/O Input/Output Capacitance VIN = 0V -10
pF
Parameter Symbol Min Typ Max Unit
Program (following 10h) tPROG - 1600 3500 uS
Cache Program (following 15h) tCBSYW -- - uS
multi plane Program / multi plane Cache
Program / multi plane Copy-Back Program
(following 11h)
tDBSY -3 5 uS
Cache Read / multi plane Cache Read
(following 31h/3Fh) tCBSYR - 3 200 uS
Block Erase / multi plane Block Erase tBERS -3.510 mS
Number of partial Program Cycles in the
same page NOP - - 1 cycles
Rev 1.0 / Aug. 2010 18
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
2.7. AC Timing Characteristics
Parameter Symbol 3.3V Unit
Min Max
CLE setup time tCLS 12 ns
CLE Hold time tCLH 5ns
CE# setup time tCS 20 ns
CE# hold time tCH 5ns
WE# pulse width tWP 8ns
ALE setup time tALS 10 ns
ALE hold time tALH 5ns
Data setup time tDS 10 ns
Data hold time tDH 5ns
Write cycle time tWC 20 ns
WE# high hold time tWH 10 ns
Data transfer from cell to register tR200 us
ALE to RE# delay tAR 10 ns
CLE to RE# delay tCLR 10 ns
Ready to RE# low tRR 20 ns
RE# pulse width tRP 10 ns
WE# high to busy tWB 100 ns
Read cycle time tRC 20 ns
RE# access time tREA 16 ns
RE# high to output high Z tRHZ 100 ns
CE# high to output high Z tCHZ 50 ns
RE# high to output hold tRHOH 15 ns
RE# low to output hold tRLOH 5ns
RE# or CE# high to output hold tCOH 15 ns
RE# high hold time tREH 8ns
WE# high to RE# low tWHR 80 ns
RE# high to WE# low tRHW 100 ns
Output high Z to RE# low tIR 0ns
CE# low to RE# low tCR 10 ns
Address to data loading time tALD 200 ns
Rev 1.0 / Aug. 2010 19
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
Notes:
1. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us.
2. Program / Erase Enable Operation: WP# high to WE# High.
Program / Erase Disable Operation: WP# Low to WE# High.
3. The transition of the corresponding control pins must occur only while WE# is held low.
4. tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle.
Device resetting time
(Read/Program/Erase) tRST 20/30/500 us
Write protection time tWW 100 ns
Rev 1.0 / Aug. 2010 20
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
2.8. Status Register Coding
2.8.1. Status Register Coding For 70h/78h command
Notes:
1. I/O0: This bit is only valid for Program and Erase operations. During Cache Program operations,
this bit is only valid when I/O5 is set to one.
2. I/O1: This bit is only valid for cache program operations. This bit is not valid until after the
second 15h command or the 10h command has been transferred in a Cache program sequence.
When Cache program is not supported, this bit is not used.
3. I/O5: If set to one, then there is no array operation in progress. If cleared to zero, then there is a
command being processed (I/O6 is cleared to zero) or an array operation in progress. When
overlapped interleaved operations or cache commands are not supported, this bit is not used.
4. I/O6: If set to one, then the device or interleaved address is ready for another command and
all other bits in the status value are valid. If cleared to zero, then the last command issued
is not yet complete and Status Register bits<5:0> are invalid value. When cache operations
are in use, then this bit indicates whether another command can be accepted, and I/O5
indicates whether the last operation is complete.
I/O Page
Program
Block
Erase Read Cache
Read
Cache
Program
Coding
70h/ 78h
0 Pass/ Fail Pass/ Fail N/A N/A Pass/ Fail (N) N page
Pass : '0' Fail : '1'
1 N/A N/A N/A N/A Pass/ Fail (N-1) N-1 page
Pass : '0' Fail : '1'
2 N/A N/A N/A N/A N/A '0'
3 N/A N/A N/A N/A N/A '0'
4 N/A N/A N/A N/A N/A '0'
5 N/A N/A N/A Ready / Busy Ready / Busy Ready / Busy
Busy : '0' Ready : '1'
6 Ready / Busy Ready / Busy Ready / Busy Ready / Busy Ready / Busy Data Cache Ready /
Busy : '0' Ready : '1'
7 Write Protect Write Protect Write Protect Write Protect Write Protect Protected : '0'
Not Protected : '1'
Rev 1.0 / Aug. 2010 21
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
2.8.2. Status Register Coding For 75h command
2.9. Device Identifier Coding
I/O Page
Program
Block
Erase Read Cache
Read
Cache
Program
Coding
70h/ 78h
0 Chip Pass/ Fail Chip Pass/ Fail N/A N/A Chip
Pass/ Fail (N)
N page
Pass : '0' Fail : '1'
1Plane 0
Pass/ Fail
Plane 0
Pass/ Fail N/A N/A Plane 0
Pass/ Fail (N)
N page
Pass : '0' Fail : '1'
2Plane 1
Pass/ Fail
Plane 1
Pass/ Fail N/A N/A Plane 1
Pass/ Fail (N)
N page
Pass : '0' Fail : '1'
3 N/A N/A N/A N/A Plane 0
Pass/ Fail (N-1)
N page
Pass : '0' Fail : '1'
4 N/A N/A N/A N/A Plane 1
Pass/ Fail (N-1)
N page
Pass : '0' Fail : '1'
5 N/A N/A N/A Ready / Busy Ready / Busy Ready / Busy
Busy : '0' Ready : '1'
6 Ready / Busy Ready / Busy Ready / Busy Ready / Busy Ready / Busy Data Cache Ready /
Busy : '0' Ready : '1'
7 Write Protect Write Protect Write Protect Write Protect Write Protect Protected : '0'
Not Protected : '1'
Parameter Symbol
Device Identifier Byte Description
1st Manufacturer Code
2nd Device Identifier
3rd Internal chip number, cell Type, Number of Simultaneously
Programmed Pages, Interleaved Program, Write Cache.
4th Page size, Block size, Redundant area size
5th Plane Number, ECC Level
6th Technology (Design Rule), EDO, Interface
Rev 1.0 / Aug. 2010 22
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
2.10. Read ID Data Table
2.10.1. 3rd Byte of Device Identifier Description
Part Number Voltage Bus
Width
Manufacture
Code
Device
Code 3rd 4th 5th 6th
H27UCG8T2MYR-BC 3.3V X8 ADh DEh 94h D2h 04h 43h
3rd cycle Description I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
I/O
0
Internal Chip Number
1
2
4
Reserved
0
0
1
1
0
1
0
1
Cell Type
2 Level Cell
4 Level Cell
8 Level Cell
16 Level Cell
0
0
1
1
0
1
0
1
Number of Simultaneously
Programmed Pages
1
2
4
8
0
0
1
1
0
1
0
1
Interleaved Program
between Multiple dice
Not Support
Support
0
1
Write Cache Not Support
Support
0
1
Rev 1.0 / Aug. 2010 23
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
2.10.2. 4th Byte of Device Identifier Description
2.10.3. 5th Byte of Device Identifier Description
4th cycle Description I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
I/O
0
Page Size
(Without Spare Area)
2KB
4KB
8KB
Reserved
0
0
1
1
0
1
0
1
Block Size
(Without Spare area)
128KB
256KB
512KB
768KB
1MB
2MB
Reserved
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Redundant Area Size
128B
224B
448B
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
5th cycle Description I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
I/O
0
Plane Number
1
2
4
8
0
0
1
1
0
1
0
1
ECC Level
1bit/512Bytes
2bit/512Bytes
4bit/512Bytes
8bit/512Bytes
16bit/512Bytes
24bit/2048Bytes
24bit/1024Bytes
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved 0 0 0
Rev 1.0 / Aug. 2010 24
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
2.10.4. 6th Byte of Device Identifier Description
6th cycle Description I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
I/O
0
NAND Technology
48nm
41nm
32nm
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
EDO Support Not Support
Support
0
1
NAND Interface SDR
DDR
0
1
Reserved 0 0 0
Rev 1.0 / Aug. 2010 25
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
CL
S
CS
WP
Command
CLE
CE#
WE#
ALE
I/Ox
DH DS
ALS
CLH
CH
: Don’t care
tt
tt
t
t
tt
ALH
t
3. Timing Diagram
Bus Operation
There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input,
Data Output, Write Protect, and Standby.
3.1. Command Latch Cycle Timings
■Figure 5. Command latch timings
Note:
All command except Reset, Read Status, and Multi Plane Read Status is issued to command register on the rising edge
of WE#, when CLE is high, CE# and ALE is low, and device is not busy state
Rev 1.0 / Aug. 2010 26
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
WC
CLH
CH
WP WH
DIN 1 DIN final
DH DH DH
DS DS DS
WP WP
CLE
ALE
CE#
I/Ox
WE#
ALS
DIN 0
t
t
t
t
t
t
t
t
t
t
t
t
t
t
: Don’t care
tCLS
tCS
tWC
tALS tALS tALS tALS tALS tALHtALHtALHtALHtALH
tWC tWC tWC
tWP tWP
tWH
tWP tWP
tWH
tWH tWH
tDS
Col.Add1
CLE
CE
WE
ALE
I/Ox Col.Add2 Row Add1 Row Add2 Row Add3
tDS tDS tDS tDS
tDHtDHtDHtDHtDH
: Don’t care
3.2. Address Latch Cycle Timings
■Figure 6. Address latch timings
3.3. Input Data Latch Cycle Timings
■Figure 7. Input data cycle timings
Note:
Data Input cycle is accepted to data register on the rising edge of WE#, when CLE and CE# and ALE are low,
and device is not Busy state.
Rev 1.0 / Aug. 2010 27
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
RR
CHZ
RHZ
RHOH
Dout
CE#
RE#
I/Ox
R/B#
REA
Dout
RLOH
REA
RP REH
RC
t
tt
t
t
t
t
t
t
t
: Don’t care
CR
t
REH
REA
RC
RR
CHZ
RHZ
RHOH
Dout
Dout
CE#
RE#
I/Ox
R/B#
Dout
REA
RHZ
REA
t
t
t
t
t
t
t
t
t
t
3.4. Data Output Cycle Timings (CLE=L, WE#=H, ALE=L, WP#=H)
■Figure 8. Data output cycle timings
Notes:
1. Transition is measured +/-200mV from steady state voltage with load.
This parameter is sampled and not 100% tested. ( tCHZ, tRHZ)
2. tRLOH is valid when frequency is higher than 10 MHz.
tRHOH starts to be valid when frequency is lower than 10 MHz.
3.5. Data Output Cycle Timings (EDO type, CLE=L, WE#=H, ALE=L)
■Figure 9. Data output cycle timings (EDO)
Notes:
1. Transition is measured +/-200mV from steady state voltage with load.
This parameter is sampled and not 100% tested. ( tCHZ, tRHZ)
2. tRLOH is valid when frequency is higher than 10 MHz.
tRHOH starts to be valid when frequency is lower than 10 MHz.
Rev 1.0 / Aug. 2010 28
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
tCLS tCLH
tCS
tWP
tCH tCR
tCHZ
tCOH
tWHR
tALH tAR
tREA tRHZ
tRHOH
tDS tDH
tALH tALS
WC
tWP
tWH
t
: Don’t care
CLE
CE#
WE#
ALE
RE#
I/Ox
78h Row.Add1 Row.Add2 Row.Add3 Status
CLE
CE#
RE#
I/Ox
WE#
70h Status output
CLS
t
CLH
t
CS
t
CLR
t
CH
t
CR
t
CHZ
t
RHZ
t
RHOH
t
WP
t
WHR
t
DS
t
DH
t
IR
t
REA
t
: Don’t care
3.6. Read Status Cycle Timings
■Figure 10. Read status timings
3.7. Multi Plane Read Status Timings
■Figure 11. Multi plane read status timings
Rev 1.0 / Aug. 2010 29
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
CE#
CLE
ALE
WE#
RE#
I/Ox 00h
Col.
Add1
Col.
Add2
Row.
Add1
Row.
Add2
Row.
Add3
30h
Dout
N
Dout
N+1
Dout
N+2
R/B#
tAR
tRC
tR
tWB
tRR
t
WC
: Don’t care
tRHZ
Dout
M
CE#
CLE
ALE
WE#
RE#
I/Ox 00h
Col.
Add1
Col.
Add2
Row.
Add1
Row.
Add2
Row.
Add3
30h
Dout
N
Dout
N+1
Dout
N+2
R/B#
tAR
tRC
tR
tWB
tRR
t
WC
: Don’t care
tCLR
tCHZ
tCOH
t
CS
t
CH
t
CLS
t
CLH
3.8. Page Read Operation Timings (Read One Page)
■Figure 12. Page read operation timings
3.9. Page Read Operation Timings (Intercepted by CE#)
■Figure 13. Page read operation timings
Rev 1.0 / Aug. 2010 30
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
3.10. Page Read Operation Timings with CE# don't care
■Figure 14. Page read operation timings with CE# don't care
3.11. Random Data Output Timings
■Figure 15. Random data output timings
Note:
Random data output is available within a page.
Rev 1.0 / Aug. 2010 31
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
3.12. Multi Plane Page Read Operation with Random Data output Timings
■Figure 16. Multi plane page read operation timings with random data output
Notes:
1. Multi Plane Page addresses are required to be the same.
2. Multi Plane Random data-out must be used after multi plane read operations.
3. Multi Plane page read must be used after Multi plane programmed page, Multi Plane cache program,
and Multi Plane copy-back program.
Rev 1.0 / Aug. 2010 32
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
3.13. Cache Read Operation Timings
■Figure 17. Cache read operation timings
Notes:
1. The column address will be reset to 0 by the 31h/3Fh command input.
2. Cache read operation is available only within a block.
Rev 1.0 / Aug. 2010 33
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
3.14. Multi Plane Cache Read Operation Timings
■Figure 18. Multi plane cache read operation Timings
Notes:
1. The column address will be reset to 0 by the 31h/3Fh command input.
2. Cache read operation is available only within a block.
3. Make sure to terminate the operation with 3Fh command. If the page read operation is completed,
issue FFh reset before next operation.
4. Multi Plane Page addresses are required to be the same.
5. Multi Plane cache read must be used after Multi plane programmed page, multi plane cache program,
and multi plane copy-back program
Rev 1.0 / Aug. 2010 34
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
Device
code
3rd
cyc.
4th
cyc.
90h
CE#
CLE
WE#
ALE
RE#
I/Ox
00h ADh
AR
WHR
REA
5th
cyc.
6th
cyc.
Maker code
t
t
t
3.15. Read ID Operation Timings
■Figure 19. Read ID operation timings
3.16. Page Program Operation Timings
■Figure 20. Page program operation timings
Note:
tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle.
Rev 1.0 / Aug. 2010 35
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
3.17. Page Program Operation Timings with CE# don't care
■Figure 21. Page program operation timings with CE# don't care
Note:
tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle.
3.18. Random Data Input Timings
■Figure 22. Random data input timings
Notes:
1. tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle.
2. Random data input can be performed in a page.
Rev 1.0 / Aug. 2010 36
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
3.19. Multi Plane Page Program Operation Timings
■Figure 23. Multi plane page program operation timing
Notes:
1. Any command between 11h and 81h is prohibited except 70h, 78h, 75h and FFh
2. tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle.
3. Multi Plane Page addresses are required to be the same.
Rev 1.0 / Aug. 2010 37
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
3.20. Copy-Back Program Operation Timings with Random Date Input
■Figure 24. Copyback program operation timing with random data input
Note:
Copy back operation is allowed only within the same memory plane.
3.21. Cache Program Operation Timings
■Figure 25. Cache program operation timings
Note:
tPROG = Program time for the last page + Program time for the (last -1)th page - (command input cycle
time + address input cycle time + Last page data loading time
Rev 1.0 / Aug. 2010 38
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
3.22. Multi Plane Cache Program Operation Timings
■Figure 26. Multi plane cache program operation timings
Notes:
1. tPROG = Program time for the last page + Program time for the (last -1)th page - (command input cycle
time + address input cycle time + Last page data loading time)
2. Make sure to terminate the operation with 80h-10h- command sequence. If the operation is terminated
by 80h-15h command sequences, monitor I/O5 (Ready/Busy) and I/O6 (Data Cache Ready/Busy) by
issuing Read Status Command (70h) and make sure the previous and current Cache Page Program
operation is completed. If the page program operation is completed, issue FFh reset before next operation.
3. Selected Page address except A22 within two blocks must be same.
Rev 1.0 / Aug. 2010 39
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
3.23. Block Erase Operation Timings
■Figure 27. Block erase operation timings
3.24. Multi Plane Erase Operation Timings
■Figure 28. Multi plane erase operation timings
Rev 1.0 / Aug. 2010 40
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
FFh
tRST
CE#
CLE
WE#
I/Ox
R/B#
tWB
3.25. Reset Timings
■Figure 29. Reset timings
Rev 1.0 / Aug. 2010 41
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
CLE
ALE
CE#
I/Ox
WE#
R/B#
RE#
00h Address (5 cycle) 30h Data Output (Serial Access)
tR
4. DEVICE OPERATION
4.1. Page Read
This operation is initialized by 00h-30h to the command register along with followed by five address input cycles. The
8,640 bytes of data within the selected page are transferred to the data registers in less than 200㎲(tR). The system
controller may detect the completion of this data transfer 200㎲(tR) by analyzing the output of R/B# pin. Once the
data in a page is loaded into the data registers, they may be read out in 25㎱ cycle time by sequentially pulsing RE#.
The repetitive high to low transitions of the RE# clock make the device output the data starting from the selected col-
umn address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random data out-
put command. The column address of next data, which is going to be out, may be changed to the address, which fol-
lows random data output command. Random data output can be operated multiple times, regardless of how many
times it is done in a page.
■Figure 30. Page read
Random data output
Random data output operation changes the column address from which data is being read in the page register. Ran-
dom data output only is issued in Ready state. Refer to Figure 31.
Rev 1.0 / Aug. 2010 42
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
I/Ox
R/B#
RE#
00h Data
tR
Output
Address
(5 cycle) 30h Data Output 05h Address
(2 cycle) E0h
30h 31h D0 ... Dn 31h D0 ... Dn 3Fh D0 ... Dn
CLE
WE#
RE#
I/Ox
R/B#
As defined for Read
t
R
t
CBSYR
Column 0
t
CBSYR
Column 0
t
CBSYR
Column 0
■Figure 31. Random data output
4.2. Cache Read (available only within a block)
To improve page read throughput, cache read operation is used within a block. First step is same as normal page read,
issuing a page read sequence (00-30h). After random access (R/B# returns to high), 31h command is latched into the com-
mand register. Data is being transferred from the data register to the cache register. While cache register data is outputted,
next page is transferred from memory cell to data register. R/B# will stay low during present page random accessing and
previous page transferring to cache register. Because it is not necessary to output a whole page data before issuing another
31h command, if serial data output time exceeds random access time (tR), the random access time can be hidden. The sub-
sequent pages are issued additional 31h commands. To terminate cache read, 3Fh command should be issued. This com-
mand transfer data from data register to the cache register without issuing next page read. During the Cache Read Opera-
tion, device doesn?t allow any other command except Cache Read command (31h), Read Status (70h, 78h, 75h), Read
(00h), and Reset (FFh). To carry out other operations after cache operation, cache read must be ended by 3Fh command
or issue reset (FFh) before next operation.
■Figure 32. Cache read
Rev 1.0 / Aug. 2010 43
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
60h
tR
A
I/Ox
R/B#
A
Address
(3 Cycle)
Page address : Page M
Plane address : Fixed “Low”
Block address : Block J
Column address : Fixed “Low
Page address : Page M
Plane address : Fixed ‘Low’
Block address : Block J Column address : Valid
Address
(3 Cycle)
60h 30h
Page address : Page M
Plane address : Fixed “High”
Block address : Block K
B
I/Ox
R/B#
00h Address
(5 Cycle)
Address
(2 Cycle)
05h E0h Data output
I/Ox
R/B#
B
Column address : Fixed “Low
Page address : Page M
Plane address : Fixed ‘High’
Block address : Block K Column address : Valid
00h Address
(5 Cycle)
Address
(2 Cycle)
05h E0h Data output
4.3. Cache Read Enhanced (available only within a block)
This command extends the Cache Read command. While, by issuing a Cache Read command, the next page address of
the next page is automatically incremented by 1, the next page address of the next page is given arbitrarily by the user.
The Cache Read Enhanced command sequence consists of a 00h command, five address cycles and a 31h command,
which replaces the single 31h command of the Cache Read command sequence.
4.4. Multi Plane Page Read
Multi-Plane Page Read is an extension of Page Read, for a single plane with 8,640byte page registers. Since the device
is equipped with two memory planes, activating the two sets of 8,640byte page resisters enables a random read of two
pages. Multi-Plane Page Read is initiated by repeating command 60h followed by three address cycles twice. In this case,
only same page of each block can be selected from each plane.
After Read Confirm command (30h) the 17,280bytes of data within the selected two pages are transferred to the data
registers in less than 200㎲ (tR). The system controller can detect the completion of data transfer (tR) by monitoring the
output of R/B# pin.
Once the data is loaded into the data registers, the data output of first plane can be read out by issuing command 00h
with Five Address Cycles, command 05h with two column address and finally E0h. The data output of second plane can
be read out using the identical command sequences. The restrictions for Multi-Plane Page Read are shown in Figure 33.
Multi-Plane Page Read must be used in the block which has been programmed with Multi-Plane Page Program.
■Figure 33. Multi plane page read
Rev 1.0 / Aug. 2010 44
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
60h
tR
A
I/Ox
R/B#
A
Address
(3 Cycle)
Page address : Page M
Plane address : Fixed “Low”
Block address : Block J
Column address : Fixed “Low”
Page address : Page M
Plane address : Fixed “Low”
Block address : Block J Column address : Valid
Address
(3 Cycle)
60h 33h
Page address : Page M
Plane address : Fixed “High”
Block address : Block K
B
tCBSYR
I/Ox
R/B#
00h Address
(5 Cycle)
Address
(2 Cycle)
05h E0h Data output
I/Ox
R/B#
B
Column address : Fixed “Low”
Page address : Page M
Plane address : Fixed “High”
Block address : Block K Column address : Valid
00h Address
(5 Cycle)
Address
(2 Cycle)
05h E0h Data output
31h
4.5. Multi Plane Cache Read (available only within a block)
The device supports multi-plane cache read, which enables high read throughput by reading two pages in parallel. Figure
34 shows the command sequence for the multi-plane cache read operation. Both confirm commands, 30h and 33h, are
valid for the first page read sequence.
■Figure 34. Multi plane cache read
Notes:
1. plane 0 and plane 1 should be selected within the same chip
2. Only one block should be selected from the each plane.
3. Multi plane cache read is available only within a block per plane.
4. Selected Page address except A22 within two blocks must be same.
5. The operation has to be terminated with “3Fh” command.
4.6. Multi Plane Cache Read Enhanced (available only within a block)
This command is a multi-plane extension of the Cache Read Enhanced command.
4.7. Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an ad-
dress input of 00h. Six read cycles sequentially output the manufacturer code (ADh), and the device code and 3rd, 4th,
5th, 6th cycle ID, respectively. The command register remains in Read ID mode until further commands are issued to it.
Figure 35 shows the operation sequence, while 2.10 READ ID data tables explain the byte meaning.
Rev 1.0 / Aug. 2010 45
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
CLE
ALE
WE#
RE#
I/Ox 78h Row.Add1 Row.Add3
Row.Add2 Status
70h Status
CLE
WE#
RE#
I/Ox
90h
CLE
WE#
ALE
RE#
I/Ox
00h ADh DE 04 43
D2
WHR
94h
t
■Figure 35. Read ID
4.8. Read Status Register
The device contains a Status Register which may be read to find out whether read, program or erase operation is com-
pleted, and whether the program or erase operation is completed successfully. After writing Read Status (70h) or Multi
Plane Read Status (78h,75h) command to the command register, a read cycle outputs the content of the Status Register
to the I/O pins only if CE# and RE# are low, whichever occurs last. This two line control allows the system to poll the
progress of each device in multiple memory connections even when R/B# pins are common-wired. Refer to 2.8. STATUS
REGISTER CODINGS for specific Status Register definitions and Figure 36, Figure 37 for Read Status. The command reg-
ister remains in Read Status mode until further commands are issued to it. Therefore, if the status register is read during
a random read cycle, the read command (00h) should be given before starting read cycles.
■Figure 36. Read status
■Figure 37. Multi plane read status
Rev 1.0 / Aug. 2010 46
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
80h Address 5 cycle Data Input Status
70h10h
CLE
PROG
t
I/O 0 = 0 PROGRAM Pass
I/O 0 = 1 PROGRAM Fail
CE#
ALE
WE#
RE#
I/Ox
R/B#
4.9. Page Program
The device is programmed as a page unit. The number of consecutive partial page programming operation within the
same page without an intervening erase operation must not exceed 1 times. The program addressing should be done in
sequential order in a block. A page program cycle consists of a serial data loading period in which up to 8,640bytes of
data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is pro-
grammed into the appropriate cell. The serial data-loading period begins by inputting the Serial Data Input command
(80h), followed by the five cycle address inputs and then serial data. The words other than those to be programmed do
not need to be loaded. The device supports random data input in a page. The column address of next data, which will be
entered, may be changed to the address which follows random data input command (85h). Random data input may be
operated multiple times, regardless of how many times it is done in a page. The Page Program Confirm command (10h)
initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the pro-
gramming process. The internal write state controller automatically executes the algorithms and timings necessary for
program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read
Status Register command may be entered to read the status register.
The system controller can detect the completion of a program cycle by monitoring the R/B# output, or the Status bit (I/
O6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in
progress. The Write Status Bit (I/O 0) is valid, when all internal operations are complete (status bit I/O 6 = high).
The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s.
The command register remains in Read Status command mode until another valid command is written to the command
register. Figure 38 and Figure 39 details the sequence.
■ Figure 38. Page Program
■Figure 39. Random data input
I/Ox
R/B#
Column address
80h Address
(5 Cycle)
Address
(2 Cycle)
Data
Input 85h Data
Input 70h Status
10h
PROG
t
Rev 1.0 / Aug. 2010 47
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
80h Address (5 cycle) 11h
t
DBSY
Data Input
A
81h Address (5 cycle) 10h
t
PROG
Data Input
I/Ox
R/B#
70h Status
1 plane address
st
2 plane address
nd
A
I/Ox
R/B#
4.10. Multi Plane Program
Device supports multiple plane program. It is possible to program in parallel 2 pages, one per each plane.
A multiple plane program cycle consists of a double serial data loading period in which up to 17,280bytes of data may
be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed
into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command (80h), fol-
lowed by the five cycle address inputs and then serial data for the 1st page. Address for this page must be within first
plane (A<22>=0). The data of first page other than those to be programmed do not need to be loaded. The device
supports random data input exactly like page program operation. The Dummy Page Program Confirm command (11h)
stops 1st page data input and the device becomes busy for a short time (tDBSY). Once it has become ready again, 81h
command must be issued, followed by second page address (5 cycles) and its serial data input. Address for this page
must be within second plane (A<22>=1). The data of second page other than those to be programmed do not need
to be loaded. Program Confirm command (10h) makes parallel programming of both pages start. User can check oper-
ation status by R/B# pin or read status register command, as if it were a normal page program; status register command
is also available during Dummy Busy time (tDBSY). In case of fail in first plane or second plane page program, fail bit of
status register will be set: Pass/Fail status of each plane can be checked by Multi Plane Read Status. Figure 40 details
the sequence.
■Figure 40. Multi plane page program
Notes:
1. Plane 0 and Plane 1 should be selected within the same chip
2. Only one block should be selected from the each Plane.
3. Selected Page address except for A22 within two blocks must be same.
4. Any command between 11h and 81h is prohibited except 70h/78h/75h and FFh.
5. Read Status command can be 70h or 78h or 75h.
Rev 1.0 / Aug. 2010 48
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
4.11. Cache Program (available only within a block)
Cache Program is an extension of the standard page program, which is executed with 8,640 bytes cache registers and
same bytes data register. After the serial data input command (80h) is loaded to the command register, followed by 5
cycles of address, a full or partial page of data is latched into the cache register, and then the cache write command
(15h) is loaded to the command register. After that sequence, the data in the cache register is transferred into the data
register for cell programming. At this time, the device remains in busy state. After all data of the cache register is trans-
ferred into the data register, the device goes to the Ready state to load the next data into the cache register by issuing
another cache program command sequence (80h-15h).
There are some restrictions for cache program operation.
1. The cache program command is available only within a block.
2. User must give address and data after 80h command.
The Busy time of first sequence equals the time it takes to transfer the data of cache register to the data register. Cell
programming of the data of data register and loading of the next data into the cache register is consequently processed
as a pipeline method. On the second and cascading sequence, transfer from the cache register to the data register is
held off until cell programming of current data register contents has been done.
Read Status command (70h) may be issued to find out when the cache register is ready by polling the Cache-Busy sta-
tus bit (I/O 6). In addition, the status bit (I/O 5) can be used to determine when the cell programming of the current
data register contents is complete. Pass/fail status of only the previous page (I/O 1) is available upon the return to
Ready state.
If the system monitors the progress of programming only with R/B#, the last page of the target programming sequence
must be programmed with actual Page Program command (10h). If the Cache Program command (15h) is used instead,
status bit (I/O5) must be polled to find out when the last programming is actually finished before starting other opera-
tions such as read. Pass/fail status is available in two steps. I/O 1 returns with the status of the previous page upon
Ready or I/O6 status bit changing to "1", and later I/O 0 with the status of current page upon true Ready (returning
from internal programming) or I/O 5 status bit changing to "1". I/O 1 may be read together when I/O 0 is checked.
Refer to 2.8. Status Register Coding and Figure 41 for more details.
Rev 1.0 / Aug. 2010 49
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
80h Address (5 cycle) 15h
t
CBSYW
Data Input
A
80h Address (5 cycle) 15h
t
CBSYW
Data Input
B
I/Ox
R/B#
80h Address (5 cycle) 10h
t
PROG
Data Input
I/Ox
R/B#
70h Status
A
B
I/Ox
R/B#
R/B# Pin
Data Cache Ready /Bysy
(I/O6)
I/O 1 =>
I/O 0 =>
Invalid
Invalid
Page1
Invalid
Page1
Page2
Page N-2
Invalid
Invalid
Invalid
Page N-1
Page N
Data Cache Ready /Bysy
(I/O5)
70h
SR
OUT
70h
SR
OUT
80h-add-data-15h 80h-add-data-15h 70h
SR
OUT
80h-add-data-15h 70h
SR
OUT
80h-add-data-15h 70h
SR
OUT
70h
SR
OUT
Page 1 Page 2 Page N-1 Page N
Page 1 Page 2 Page N-1 Page N
During both I/O6 and I/O5 return to high, the Pass/Fail for previous page and current page
can be shown through I/O1 and I/O0 concurrently.
PROG
t
CBSYW
t
CBSYW
t
CBSYW
t
Pass / Fail status for each page programmed by the Cache Program operation can be detected by the Read Status operation.
I/O 0 : Pass / Fail of the current page program operation.
I/O 1 : Pass / Fail of the previous page program operation.
The Pass / Fail status on I/O 0 and I/O 1 are valid under the following conditions.
Status on I/O 0 : Ready / Busy is Ready state.
The Ready/ Busy is output on I/O 5 by Read Status operation or R/B pin after the 10h command.
Status on I/O 1 : Data Cache Ready / Busy is Ready State.
The Data Cache Ready / Busy is output on I/O 6 by Read Status operation or R/B pin after the 15h command.
■ Figure 41. Cache program
Rev 1.0 / Aug. 2010 50
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
4.12. Multi Plane Cache Program (available only within a block)
The device supports multi plane cache program, which enables high program throughput by programming two pages.
The serial data-loading period begins by inputting the Serial Data Input command (80h), followed by the five cycle
address inputs and then serial data for the first page. Address for this page must be within first plane (A<22>=0). The
data of first page other than those to be programmed do not need to be loaded. The device supports random data
input exactly like page program operation. The Dummy Page Program Confirm command (11h) stops 1st page data
input and the device becomes busy for a short time (tDBSY). Once it has become ready again, 81h command must be
issued, followed by 2nd page address (5 cycles) and its serial data input. Address for this page must be within second
plane (A<22>=1). The data of second page other than those to be programmed do not need to be loaded. Cache
Program Confirm command (15h) makes parallel programming of both pages start. And last page inputs Program
confirm command (10h). the last page of the target programming sequence must be programmed with actual Page
Program command (10h). If the operation is terminated, Issue FFh reset before next operation. If multiplane
cache program begins, multiplane sequence should be used until multiplane cache program is ended.
Figure 44 shows the command sequence for Multi Plane Cache Program operation. After the "15h"or"10h"
command, the result per plane of the operation is shown through the "78h" Multi Plane Read Status command.
■Figure 42. Multi plane cache program
Notes:
1. Plane 0 and Plane 1 should be selected within the same chip
2. Only one block should be selected from the each Plane.
3. Multi Plane cache program is available only within a block per Plane.
4. Selected Page address except for A22 within two blocks must be same.
5. The operation has to be terminated with “10h” command.”
6. Any command between 11h and 81h is prohibited except 70h/78h/75h and FFh.
7. Read Status command can be 70h or 78h or 75h. Reading the Status per Plane is available only 78h.
80h
tCBSYW
A
80h 81h
I/Ox
R/B#
A
Address
(5 Cycle)
Data
Input 11h
Address
(5 Cycle)
Data
Input 11h 81h Address
(5 Cycle)
Data
Input 15h
tDBSY
Address
(5 Cycle)
Data
Input 10h 78h Address
(3 Cycle)
Status
per plane
Column address : Valid
Page address : Page M
Plane address : Fixed ‘Low’
Block address : block J
Column address : Valid
Page address : Page M
Plane address : Fixed ‘High’
Block address : block K
Column address : Valid
Page address : Page M+n
Plane address : Fixed ‘Low’
Block address : block J
Column address : Valid
Page address : Page M+n
Plane address : Fixed ‘High’
Block address : block K
I/Ox
R/B#
tPROG
tDBSY
Rev 1.0 / Aug. 2010 51
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
4.13. Copy-Back Program
Copy-Back program with Read for Copy-Back is configured to quickly and efficiently rewrite data stored in one page
without data reloading when the bit error is not in data stored. Since the time-consuming re-loading cycles are
removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated
and the rest of the block needs to be copied to the newly assigned free block. Copy-Back operation is a sequential exe-
cution of Read for Copy-Back and of copy-back program with the destination page address. A read operation with
"35h" command and the address of the source page moves the whole 8,640-byte data into the internal data buffer. A
bit error is checked by sequential reading the data output. In the case where there is no bit error, the data do not
need to be reloaded. Therefore, Copy-Back program operation is initiated by issuing Page-Copy Data-Input command
(85h) with destination page address. Actual programming operation begins after Program Confirm command (10h) is
issued. Once the program process starts, the Read Status Register command (70h) may be entered to read the status
register. The system controller can detect the completion of a program cycle by monitoring the R/B# output, or the
Status bit (I/O 6) of the Status Register. When the Copy-Back Program is complete, the Write Status Bit (I/O 0) may
be checked. The command register remains in Read Status command mode until another valid command is written to
the command register. During copy-back program, data modification is possible using random data input command
(85h) as shown in Figure 43.
■Figure 43. Copyback program
00h Address
(5 cycle) 35h Data output
tR
85h Address
(5 cycle) Data
tPROG
I/Ox
R/B#
Target Address
85h Address
(2 cycle) Data 10h 70h Status
Column
address 1,2
I/Ox
R/B#
Source Address A
A
Rev 1.0 / Aug. 2010 52
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
60h
tR
A
I/Ox
R/B#
A
Address
(3 Cycle)
Page address : Page M
Plane address : Fixed “Low”
Block address : Block J
Column address : Fixed “Low
Page address : Page M
Plane address : Fixed ‘Low’
Block address : Block J Column address 1,2 : Valid
Address
(3 Cycle)
60h 35h
Page address : Page M
Plane address : Fixed “High”
Block address : Block K
B
I/Ox
R/B#
00h Address
(5 Cycle)
Address
(2 Cycle)
05h E0h Data output
I/Ox
R/B#
B
Column address : Valid
Page address : Page N
Plane address : Fixed ‘Low’
Block address : Block P Column address 1,2 : Valid
C
85h Address
(5 Cycle)
Address
(2 Cycle)
Data 11h
I/Ox
R/B#
DColumn address 1,2 : Valid
81h Address
(5 Cycle) Data 10h
Data
85h
Address
(2 Cycle)
85h Data
tPROG
I/Ox
R/B#
C
Column address : Fixed “Low
Page address : Page M
Plane address : Fixed ‘High’
Block address : Block K Column address 1,2 : Valid
D
00h Address
(5 Cycle)
Address
(2 Cycle)
05h E0h Data output
Column address : Valid
Page address : Page N
Plane address : Fixed ‘High’
Block address : Block Q
tDBSY
4.14. Multi Plane Copy-Back Program
Multi-Plane Copy-Back Program is an extension of Copy-Back Program, for a single plane with 8,640 byte page registers.
Since the device is equipped with two memory planes, activating the two sets of 8,640-byte page registers enables a si-
multaneous programming of two pages. Figure 44 and Figure 45 show command sequence for the multi-plane copy-back
operation. First case, Figure 44, shows random data input of two planes that started right after finishing random data out-
put of previous two planes. Second case, Figure 45, shows the random data input of each plane which started right after
finishing the random data output of each plane.
■Figure 44. Multi plane Copyback program
Rev 1.0 / Aug. 2010 53
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
60h
tR
A
I/Ox
R/B#
A
Address
(3 Cycle)
Page address : Page M
Plane address : Fixed “Low”
Block address : Block J
Column address : Fixed “Low”
Page address : Page M
Plane address : Fixed “Low”
Block address : Block J Column address 1,2 : Valid
Address
(3 Cycle)
60h 35h
Page address : Page M
Plane address : Fixed “High”
Block address : Block K
B
I/Ox
R/B#
00h Address
(5 Cycle)
Address
(2 Cycle)
05h E0h Data output
I/Ox
R/B#
B
Column address : Valid
Page address : Page M
Plane address : Fixed “Low”
Block address : Block P Column address 1,2 : Valid C
85h Address
(5 Cycle)
Address
(2 Cycle)
Data Data
I/Ox
R/B#
C
Column address : Fixed “Low”
Page address : Page M
Plane address : Fixed “High”
Block address : Block K Column address 1,2 : Valid D
00h Address
(5 Cycle)
Address
(2 Cycle)
I/Ox
R/B#
D
Column address : Valid
Page address : Page M
Plane address : Fixed “High”
Block address : Block Q Column address 1,2 : Valid
81h Address
(5 Cycle) Data 10h
E0h
05h
Address
(2 Cycle)
85h Data
tPROG
85h 11h
tDBSY
Data output
■Figure 45. Multi plane Copyback program
4.15. Block Erase
The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase
Setup command (60h). Only address A22 to A33 is valid while A14 to A21 is ignored. The Erase Confirm command (D0h)
following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by
execution command ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE# after the erase confirm command input, the internal write controller handles erase and erase
verify.
Once the erase process starts, the Read Status Register command may be entered to read the status register. The system
controller can detect the completion of an erase by monitoring the R/B# output, or the Status bit (I/O 6) of the Status
Register. Only the Read Status command and Reset command are valid while erasing is in progress. When the erase op-
eration is completed, the Write Status Bit (I/O 0) may be checked. Figure 46 details the sequence.
Rev 1.0 / Aug. 2010 54
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
60h 70h
Address
(3 cycle) D0h Status
tBERS
I/Ox
R/B#
Row Add 1,2,3
60h 70h
Address
(3 cycle) 60h Status
t
BERS
Address
(3 cycle) D0h
Page address : Fixed “Low”
Plane address : Fixed “Low”
Block address : Block N
I/Ox
R/B#
Page address : Fixed “Low”
Plane address : Fixed “High”
Block address : Block M
■Figure 46. Block Erase
4.16. Multi Plane Block Erase.
Multiple plane erase, allows parallel erase of two blocks, one per each memory plane.
Block erase setup command (60h) must be repeated two times, each time followed by first block and second block ad-
dress respectively (3 cycles each). As for block erase, D0h command makes embedded operation start. Multi plane erase
does not need any Dummy Busy Time between first and second block address insertion. Address limitation required for
Multiple Plane Program applies also to multiple plane erase, as well as operation progress can be checked like for Multiple
Plane Program. Refer to the detail sequence as shown below.
■Figure 47. Multi plane Block Erase
4.17. Reset
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state
during random read, program or erase mode, the reset operation will abort these operations. The contents of memory
cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is
cleared to wait for the next command, and the Status Register is cleared to value E0h when WP# is high. Refer to 2.8.
Status Register Coding for device status after reset operation. If the device is already in reset state, the command reg-
ister will not accept a new reset command. The R/B# pin goes low for tRST after the Reset command is written. Refer
to Figure 48.
Rev 1.0 / Aug. 2010 55
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
I/Ox
R/B#
FFh
RST
t
■Figure 48. Reset
Rev 1.0 / Aug. 2010 56
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
3V device = 2.7V
tCS
FFh
2.7V
1 (max)
ms
༕
༕
10
(max)
50
(min)
2
(max)
ms
Vcc ramp
starts
: Don’t care : Undefined
VCC
0V
CE#
WP#
CLE
WE#
ALE
RE#
I/Ox
R/B#
5. OTHER FEATURES
5.1. Data Protection & Power on/off Sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal volt-
age detector disables all functions whenever VCC is below about 2.0V (3.3V device). WP# pin provides hardware pro-
tection and is recommended to be kept at VIL during power-up and power-down.
The reset command (FFh) must be issued to all dies as the first command after device is power up. Each R/B# will be
busy for maximum of 2ms after reset command is issued. In this time, the acceptable command is 70h or 78h or 75h.
■Figure 49. Data protection and power on / off
Rev 1.0 / Aug. 2010 57
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
Rp value guidence
Rp (min) = =
where IL is the sum of the input current of all devices tied to the R/B# pin.
Rp(max) is determined by maximum permissible limit of tr
@ Vcc = 3.3V, Ta = 25°C, C
L
=50pF
Fig. Rp vs tr, tf & Rp vs ibusy
Vcc (Max.) - V
OL
(Max.) 3.2V
P$,
L
I
OL +
,
L
Rp ibusy
Rp (ohm)
ibusy
ibusy [A]
tr, tf [s]
tf
3.3 381
290
1.65
96
189 1.1
0.825
4.2 4.2 4.2 4.2
Busy
Ready Vcc
V
OH
trtf
V
OL
V
OL
: 0.4V, V
OH
: 2.4V
Vcc
300n 3m
1k 2k 3k 4k
200n 2m
100n 1m
GND
Device
open drain output
R/B#
5.2. Ready / Busy
The device has a Ready/Busy output that provides method of indicating the completion of a page program, erase, copy-
back and random read completion. The R/B# pin is normally high and goes to low when the device is busy (after a reset,
read, program, and erase operation). It returns to high when the internal controller has finished the operation. The pin
is an open-drain driver thereby allowing two or more R/B# outputs to be Or-tied. Because pull-up resistor value is re-
lated to tR (R/B#) and current drain during busy (Ibusy), an appropriate value can be obtained with the following refer-
ence chart (Figure 50). Its value can be determined by the following guidance.
■Figure 50. Ready / Busy
Rev 1.0 / Aug. 2010 58
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
80h 10h
WE#
I/Ox
WP#
R/B#
WW
t
80h 10h
WE#
I/Ox
WP#
R/B#
WW
t
60h D0h
WE#
I/Ox
WP#
R/B#
WW
t
60h D0h
WE#
I/Ox
WP#
R/B#
WW
t
5.3. Write Protect Operation
The Erase and Program Operations are automatically reset when WP# goes Low (tWW = 100ns, min). The operations
are enabled and disabled as follows (Figure 51 ~ 64).
Figure 51. Enable Programming
Figure 54. Disable Erasing
Figure 52. Disable Programming
Figure 53. Enable Erasing
Rev 1.0 / Aug. 2010 59
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
6. Application Notes and Comments
6.1. Paired Page Address Information
Paired page address Paired page address
0415
2839
6C7D
A10B11
E14F15
12 18 13 19
16 1C 17 1D
1A 20 1B 21
1E 24 1F 25
22 28 23 29
26 2C 27 2D
2A 30 2B 31
2E 34 2F 35
32 38 33 39
36 3C 37 3D
3A 40 3B 41
3E 44 3F 45
42 48 43 49
46 4C 47 4D
4A 50 4B 51
4E 54 4F 55
52 58 53 59
56 5C 57 5D
5A 60 5B 61
5E 64 5F 65
62 68 63 69
66 6C 67 6D
6A 70 6B 71
6E 74 6F 75
72 78 73 79
76 7C 77 7D
7A 80 7B 81
7E 84 7F 85
82 88 83 89
86 8C 87 8D
8A 90 8B 91
8E 94 8F 95
92 98 93 99
Rev 1.0 / Aug. 2010 60
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
96 9C 97 9D
9A A0 9B A1
9E A4 9F A5
A2 A8 A3 A9
A6 AC A7 AD
AA B0 AB B1
AE B4 AF B5
B2 B8 B3 B9
B6 BC B7 BD
BA C0 BB C1
BE C4 BF C5
C2 C8 C3 C9
C6 CC C7 CD
CA D0 CB D1
CE D4 CF D5
D2 D8 D3 D9
D6 DC D7 DD
DA E0 DB E1
DE E4 DF E5
E2 E8 E3 E9
E6 EC E7 ED
EA F0 EB F1
EE F4 EF F5
F2 F8 F3 F9
F6 FC F7 FD
FA FE FB FF
When program operation is abnormally aborted (ex. power-down, reset), not only page data under program but also a
coupled row paired page data may be damaged. For example, during Page Program operation of page address 05h is
aborted by reset or power down, the data of 00h, 01h, 04h, and 05h page address may be spoiled.
Rev 1.0 / Aug. 2010 61
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
6.2. Acceptable Command after 80h
After Program Start Command (80h) is inputted, do not input any command except 85h, 10h, 11h, 15h, and FFh. If a
command is inputted except these commands, the program operation cannot be executed.
6.3. Acceptable Command between Start command and Confirm command
Only Reset Command is available between start commands and confirm commands set (start command-address-confirm
command style) that is mentioned in 1.7 Command Set. If other command is inputted, the operation cannot be executed.
Do not input any commands except FFh. For instance, it is impossible to perform a normal Page Read operation, if any
command is inputted between Page Read Command Set (00h - 5 address cycle - 30h).
6.4. Restriction of Read Status Value in Multi Plane Operation
During Multi plane operation, only 70h, 78h,75h and FFh are available between 11h-81h. But, the pass/fail output infor-
mation of 70h and 78h and 75h is not valid. During this time, only ready / busy (I/O6 and I/O5) state can be checked.
Refer to Figure 55.
■Figure 55. Restriction read status in multi plane operation
6.5. Page Program Failure
If the Page Program operation for page address N is fail, remain data in data register may be different to input data by
host. Therefore, do not attempt to program the page address N in another block without the data input sequence. The
same input sequence of 80h command, address and data is necessary.
6.6. Restriction Multi Plane Operation
To prevent abnormal multi plane operation, do not input bad block address to all Multi Plane Operation. Otherwise, the
input data of valid block could be lost and the operation could be abnormally stopped.
80h
I/Ox
R/B#
Address Data
I/O6 =>
I/O5 =>
I/O1 =>
I/O0 =>
Valid
Invalid
Invalid
Invalid
11h 70h SR
out 81h Address Data 10h 70h SR
out
Valid
Invalid
Invalid
Invalid
Valid
Invalid
Invalid
Valid
70h SR
out
tPROG
tDBSY
IO 0 = 0, Pass
IO 0 = 1, Fail
Rev 1.0 / Aug. 2010 62
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
7. Hynix NAND Flash Part Number
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1CE,SDP H 2 7 U C G 8 T 2 M Y R - B x
No. Code Description
1Hynix H : Hynix
2 Product Family 2 : Flash
3Product Mode 7 : NAND Flash
4 Power Supply
U : 2.7~3.6V L : 2.7V
S : 1.8V / 1.8V
J : 2.7~3.6V / 1.2V Q : 2.7~3.6V / 1.8V
5,6 Density
64 : 64Mb 12 : 128Mb
25 : 256Mb 51 : 512Mb
1G : 1Gb 2G : 2Gb
4G : 4Gb 8G : 8Gb
AG : 16Gb BG : 32Gb
CG : 64Gb DG : 128Gb
EG : 256Gb FG : 512Gb
1T : 1Tb 2T : 2Tb
PG : 192Gb RG : 384Gb
VG : 768Gb
7 Organization 8 : x8 6 : x16
8NAND
Classification
S : SLC + Single Die + Small Block
A : SLC + Double Die + Small Block
B : SLC + Quadruple Die + Small Block
F : SLC + Single Die + Large Block
G : SLC + Double Die + Large Block
H : SLC + Quadruple Die + Large Block
J : SLC + ODP + Large Block
K : SLC + DSP + Large Block
T : MLC + Single Die + Large Block
U : MLC + Double Die + Large Block
V : MLC + Quadruple Die + Large Block
W : MLC + DSP + Large Block
Y : MLC + ODP + Large Block
R : MLC + 6Die + Large Block
Z : MLC + 12Die + Large Block
C : MLC + 16Die + Large Block
M : TLC + SDP + Large Block
N : TLC + DDP + Large Block
P : TLC + QDP + Large Block
Q : TLC + ODP + Large Block
Rev 1.0 / Aug. 2010 63
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
Note
- Capital Letter : Fixed Item
- Small Letter : Non-fixed Item
9 Function Mode
1 : 1CE & 1R/B, Sequential Row Read Enable
2 : 1CE & 1R/B, Sequential Row Read Disable
4 : 2CE & 2R/B, Sequential Row Read Enable
5 : 2CE & 2R/B, Sequential Row Read Disable
F : 4CE & 4R/B, Sequential Row Read Disable
T: 5CE & 5R/B, Sequential Row Read Disable
U: 6CE & 6R/B, Sequential Row Read Disable
V: 8CE & 8R/B, Sequential Row Read Disable
D : 2CE&2R/B, Dual Interface
10 Generation
M : 1st Generation
B : 3rd Generation
D : 5th Generation
A : 2nd Generation
C : 4th Generation
E : 6th Generation
11 Package Type
T : TSOP1
V : WSOP
S : USOP
N : LSOP
F : FBGA-63(9x11x1.0)
I : VFBGA-100(12x18x1.0)
J : LFBGA-100(12x18x1.4)
X : LLGA (14x18-1.47T)
Y : VLGA (14x18-1.0T)
M : WLGA (14x18-0.75T)
U : ULGA (12x17-0.75T)
H : XLGA (10x7.5)
W : Wafer
C : PGD1 (chip)
D : PGD2
K : KGD
12 Package
Material
A : Wafer
P : Lead Free
L : Leaded
R : Lead & Halogen Free
13 - -
14 Bad Block B : Included Bad Block
P : All Good Block S : 1~5 Bad Block Included
15 Temperature C : 0 ~ 70 °C
M : -30 ~ 85 °C
E : -25 ~ 85 °C
I : -40 ~ 85 °C
