PIC18FX220/X320 Flash Microcontroller Programming Specification 1.0 DEVICE OVERVIEW 2.1.1 This document includes the programming specifications for the following devices: * * * * * * In Low-Voltage ICSP mode, these devices can be programmed using a VDD source in the operating range. This only means that MCLR/VPP does not have to be brought to a different voltage, but can instead be left at the normal operating voltage. Refer to Section 6.0 "AC/DC Characteristics" for additional hardware parameters. PIC18F1220 PIC18F1320 PIC18F2220 PIC18F2320 PIC18F4220 PIC18F4320 2.0 2.1.2 2.2 Pin Diagrams The programming pin descriptions for these devices are shown in Table 2-1 and the pin diagrams are shown in Figure 2-1 through Figure 2-6. The pin descriptions of these diagrams do not represent the complete functionality of the device types. Refer to the appropriate device data sheet for complete pin descriptions. Hardware Requirements In High-Voltage ICSP mode, these devices require two programmable power supplies: one for VDD and one for MCLR/VPP. Both supplies should have a minimum resolution of 0.25V. Refer to Section 6.0 "AC/DC Characteristics" for additional hardware parameters. TABLE 2-1: VDD POWER SUPPLY It is recommended that the power supply decoupling capacitance be added at the programmer socket. Capacitance in the range of 0.1 F to 10 F should be connected from VDD to VSS, and located as close to the programming socket as possible. PROGRAMMING OVERVIEW These devices can be programmed using the highvoltage In-Circuit Serial ProgrammingTM (ICSPTM) method, or the low-voltage ICSP method, both while in the user's system. The low-voltage ICSP method is slightly different than the high-voltage method and these differences are noted where applicable. This programming specification applies to these devices in all package types. 2.1 LOW-VOLTAGE ICSP PROGRAMMING PIN DESCRIPTIONS (DURING PROGRAMMING) During Programming Pin Name Function Pin Type VPP P High-Voltage Programming Enable VDD VDD P Power Supply VSS VSS P Ground RB5 PGM I Low-Voltage ICSPTM Input when LVP Configuration bit equals `1'(1) RB6 PGC I Serial Clock RB7 PGD I/O Serial Data MCLR/VPP/RA5 (2) Pin Description Legend: I = Input, O = Output, P = Power Note 1: See Section 5.3 "Single-Supply ICSP Programming" for more detail. 2: RA5 is only available on the PIC18F1X20. 2010 Microchip Technology Inc. DS39592F-page 1 PIC18FX220/X320 FIGURE 2-2: PIC18F1X20 18-PIN PDIP, SOIC 1 18 RB3/CCP1A/P1A RA1/AN1/LVDIN 2 17 RB2/P1B/INT2 RA4/T0CKI 3 16 OSC1/CLKI/RA7 MCLR/VPP/RA5 4 15 OSC2/CLKO/RA6 VSS/AVSS 5 14 VDD/AVDD RA2/AN2/VREF- 6 13 RB7/PGD/T1OSI/P1D/KBI3 RA3/AN3/VREF+ 7 12 RB6/PGC/T1OSO/T13CKI/P1C/KBI2 RB0/AN4/INT0 8 11 RB5/PGM/KBI1 RB1/AN5/TX/CK/INT1 9 10 RB4/AN6/RX/DT/KBI0 PIC18F1X20 20-PIN SSOP RA0/AN0 1 20 RB3/CCP1A/P1A RA1/AN1/LVDIN 2 19 RB2/P1B/INT2 RA4/T0CKI 3 18 OSC1/CLKI/RA7 MCLR/VPP/RA5 4 17 OSC2/CLKO/RA6 VSS 5 16 VDD AVSS 6 15 AVDD RA2/AN2/VREF- 7 14 RB7/PGD/T1OSI/P1D/KBI3 RA3/AN3/VREF+ 8 13 RB6/PGC/T1OSO/T13CKI/P1C/KBI2 9 12 RB5/PGM/KBI1 10 11 RB4/AN6/RX/DT/KBI0 RB0/AN4/INT0 RB1/AN5/TX/CK/INT1 DS39592F-page 2 PIC18F1X20 RA0/AN0 PIC18F1X20 FIGURE 2-1: 2010 Microchip Technology Inc. PIC18FX220/X320 RA1/AN1/LVDIN RA0/AN0 NC RB3/CCP1A RB2/P1B/INT2 NC 26 25 24 23 22 RA4/T0CKI 27 28 MCLR/VPP/RA5 1 21 OSC1/CLKI/RA7 NC VSS 2 20 OSC2/CLKO/RA6 3 19 VDD NC 4 18 NC AVSS 5 17 AVDD NC 6 16 RB7/PGD/T1OSI/P1D/KBI3 RA2/AN2/VREF- 7 15 RB6/PGC/T1OSO/T13CKI/P1C/KBI2 12 13 14 RB5/PGM/KBI1 NC 11 NC RB4/AN6/RX/DT/KBI0 10 9 RB1/AN5/TX/CK/INT1 8 RB0/AN4/INT0 PIC18F1X20 PIC18F2X20 28-PIN SDIP (300 MIL), SOIC MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/LVDIN/C2OUT VSS OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T1CKI RC1/T1OSI/CCP2* RC2/CCP1 RC3/SCK/SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIC18F2X20 FIGURE 2-4: PIC18F1X20 28-PIN QFN RA3/AN3/VREF+ FIGURE 2-3: 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/AN11/KBI0 RB3/AN9/CCP2* RB2/AN8/INT2 RB1/AN10/INT1 RB0/AN12/INT0 VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA * Alternate pinout for CCP2 is enabled by a fuse. 2010 Microchip Technology Inc. DS39592F-page 3 PIC18FX220/X320 PIC18F4X20 40-PIN PDIP (600 MIL) MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/LVDIN RE0/AN5/RD RE1/AN6/WR RE2/AN7/CS VDD VSS OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T1CKI RC1/T1OSI/CCP2* RC2/CCP1/P1A RC3/SCK/SCL RD0/PSP0 RD1/PSP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 PIC18F4X20 FIGURE 2-5: RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/AN11/KBI0 RB3/AN9/CCP2* RB2/AN8/INT2 RB1/AN10/INT1 RB0/AN12/INT0 VDD VSS RD7/PSP7/P1D RD6/PSP6/P1C RD5/PSP5/P1B RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 * Alternate pinout for CCP2 is enabled by a fuse. PIC18F4X20 44-PIN TQFP 44 43 42 41 40 39 38 37 36 35 34 RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1/P1A RC1/T1OSI/CCP2* NC FIGURE 2-6: PIC18F4X20 33 32 31 30 29 28 27 26 25 24 23 NC RC0/T1OSO/T1CKI OSC2/CLKO/RA6 OSC1/CLKI/RA7 VSS VDD RE2/AN7/CS RE1/AN6/WR RE0/AN5/RD RA5/AN4/SS/LVDIN/C2OUT RA4/T0CKI/C1OUT 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 NC NC RB4/AN11/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREFRA3/AN3/VREF+ RC7/RX/DT RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D VSS VDD RB0/AN12/INT0 RB1/AN10/INT1 RB2/AN8/INT2 RB3/AN9/CCP2* * Alternate pinout for CCP2 is enabled by a fuse. DS39592F-page 4 2010 Microchip Technology Inc. PIC18FX220/X320 2.3 Memory Map Locations 300001h through 30000Dh are reserved for the Configuration Words. These Words may be set to select various device options and are described in Section 5.0 "Configuration Word". These Configuration Words read out normally, even after code protection. The code memory space extends from 0000h to 1FFFh (8 Kbytes) in a single 8-Kbyte panel. Addresses 0000h through 01FFh, however, define a "Boot Block" region that is treated separately from Panel 1. All code memory is on-chip. Locations 3FFFFEh and 3FFFFFh are reserved for the Device ID Words. These Words may be used by the programmer to identify what device type is being programmed and are described in Section 5.0 "Configuration Word". These Configuration Words read out normally, even after code protection. A user may store identification information (ID) in eight ID registers. These ID registers are mapped in addresses 200000h through 200007h. The ID locations read out normally, even after code protection is applied. TABLE 2-2: IMPLEMENTATION OF CODE MEMORY Device Code Memory Size (Bytes) Data EEPROM Size (Bytes) PIC18F1220 0000h-0FFFh (4K) 000-0FFh (256) PIC18F2220 0000h-0FFFh (4K) 000-0FFh (256) PIC18F4220 0000h-0FFFh (4K) 000-0FFh (256) PIC18F1320 0000h-1FFFh (8K) 000-0FFh (256) PIC18F2320 0000h-1FFFh (8K) 000-0FFh (256) PIC18F4320 0000h-1FFFh (8K) 000-0FFh (256) FIGURE 2-7: MEMORY MAP FOR PIC18FX220/X320 200000h 200001h 200002h 200003h 200004h 200005h 200006h 200007h ID Location 1 ID Location 2 ID Location 3 ID Location 4 ID Location 5 ID Location 6 ID Location 7 ID Location 8 300000h 300001h 300002h 300003h CONFIG1L CONFIG1H CONFIG2L CONFIG2H 3FFFFEh 3FFFFFh Device ID 1 Device ID 2 0000h 200h PIC18FX320 8 Kbytes PIC18FX220 4 Kbytes Boot Block Boot Block Block 0 Block 0 Block 1 Block 1 07FFh 0FFFh 17FFh Block 2 Block 3 1FFFh Unimplemented Read as `0's Unimplemented Read as `0's 200000h 3FFFFFh 2010 Microchip Technology Inc. DS39592F-page 5 PIC18FX220/X320 FIGURE 2-8: 200000h 200001h 200002h 200003h 200004h 200005h 200006h 200007h MEMORY MAP FOR PIC18F1X20 ID Location 1 ID Location 2 ID Location 3 ID Location 4 ID Location 5 ID Location 6 ID Location 7 ID Location 8 8 Kbytes 4 Kbytes 0000h 200h Boot Block Boot Block 07FFh Block 0 Block 0 Block 1 0FFFh 17FFh Block 1 1FFFh Unimplemented 300000h 300001h 300002h 300003h CONFIG1L CONFIG1H CONFIG2L CONFIG2H 3FFFFEh 3FFFFFh Device ID 1 Device ID 2 Unimplemented Read as `0's Read as `0's 200000h 3FFFFFh 2.3.1 MEMORY ADDRESS POINTER Memory in the address space, 000000h to 3FFFFFh, is addressed via the Table Pointer, which is comprised of three pointer registers: TBLPTRU TBLPTRH TBLPTRL Addr[21:16] Addr[15:8] Addr[7:0] * TBLPTRU at address 0FF8h * TBLPTRH at address 0FF7h * TBLPTRL at address 0FF6h DS39592F-page 6 2010 Microchip Technology Inc. PIC18FX220/X320 2.4 High-Level Overview of the Programming Process Figure 2-9 shows the high-level overview of the programming process. The device is first checked to see if it is blank; if it is not, a Bulk Erase is performed. Next, the program memory, ID locations and data EEPROM are written. These memories are then verified to ensure that programming was successful. If no errors are detected, the Configuration bits are then written and verified. FIGURE 2-9: HIGH-LEVEL PROGRAMMING FLOW Start Blank Check Is part blank? No Perform Bulk Erase Yes Write Program Memory Write ID Locations Write EEPROM Verify Program Verify IDs Verify EEPROM Write Configuration Bits Verify Configuration Bits Done 2010 Microchip Technology Inc. DS39592F-page 7 PIC18FX220/X320 2.5 Entering High-Voltage ICSP Program/Verify Mode The High-Voltage ICSP Program/Verify mode is entered by holding PGC and PGD low, and then raising MCLR/VPP to VIHH (high voltage). Once in this mode, the code memory, data EEPROM, ID locations and Configuration bits can be accessed and written in serial fashion. The sequence that enters the device into the Programming/Verify mode places all unused I/Os in the high-impedance state. FIGURE 2-10: ENTERING HIGH-VOLTAGE PROGRAM/VERIFY MODE P13 2.7 Serial Program/Verify Operation The PGC pin is used as a clock input pin and the PGD pin is used for entering command bits and data input/ output during serial operation. Commands and data are transmitted on the rising edge of PGC, latched on the falling edge of PGC and are sent Least Significant bit (LSb) first. 2.7.1 4-BIT COMMANDS All instructions are 20 bits, consisting of a leading 4-bit command, followed by a 16-bit operand which depends on the type of command being executed. To input a command, PGC is cycled four times. The commands needed for programming and verification are shown in Table 2-3. P12 TABLE 2-3: D110 MCLR/VPP 4-Bit Command Description VDD PGD PGC PGD = Input 2.6 COMMANDS FOR PROGRAMMING Entering Low-Voltage ICSP Program/Verify Mode When the LVP Configuration bit is `1' (see Section 5.3 "Single-Supply ICSP Programming"), the LowVoltage ICSP mode is enabled. Low-Voltage ICSP Program/Verify mode is entered by holding PGC and PGD low, placing a logic high on PGM and then raising MCLR/VPP to VIH. In this mode, the RB5/PGM pin is dedicated to the programming function and ceases to be a general purpose I/O pin. The sequence that enters the device into the Programming/Verify mode places all unused I/Os in the high-impedance state. FIGURE 2-11: ENTERING LOW-VOLTAGE PROGRAM/VERIFY MODE P15 P12 Core Instruction (Shift in 16-bit instruction) 0000 Shift Out TABLAT Register 0010 Table Read 1000 Table Read, Post-Increment 1001 Table Read, Post-Decrement 1010 Table Read, Pre-Increment 1011 Table Write 1100 Table Write, Post-Increment by 2 1101 Table Write, Post-Decrement by 2 1110 Table Write, Start Programming 1111 Depending on the 4-bit command, the 16-bit operand represents 16 bits or 8 bits of data. Throughout this specification, commands and data are presented as illustrated in Table 2-4. The 4-bit command is shown MSb first. The command operand or "Data Payload" is shown <MSB:LSB>. Figure 2-12 demonstrates how to serially present a 20-bit command/operand to the device. TABLE 2-4: SAMPLE COMMAND SEQUENCE VIH MCLR/VPP VDD VIH 4-Bit Command Data Payload 1101 3C 40 Core Instruction Table Write, post-increment by 2 PGM PGD PGC PGD = Input DS39592F-page 8 2010 Microchip Technology Inc. PIC18FX220/X320 FIGURE 2-12: TABLE WRITE, POST-INCREMENT TIMING (1101) P2 1 2 3 4 P2A P2B 1 2 3 4 5 6 7 8 10 9 11 12 13 14 15 16 2 1 3 4 PGC P5 P5A P4 P3 PGD 1 0 1 1 0 0 0 0 4-Bit Command (LSb first) 0 0 0 1 0 0 0 1 1 4 C 16-Bit Data Payload (LSb first) 1 1 0 0 n n n n 3 Fetch Next 4-Bit Command PGD = Input 2.7.2 CORE INSTRUCTION The core instruction passes a 16-bit instruction to the CPU core for execution. This is needed to set up registers, as appropriate for use with other commands. If the instruction is a 2-word, 2-cycle instruction, another core instruction command is required with the second word of the instruction. The instruction will complete when a third 4-bit command has been loaded. If the instruction is a 1-word, 1-cycle instruction, it will be executed while the next command is clocked in. 2010 Microchip Technology Inc. DS39592F-page 9 PIC18FX220/X320 3.0 DEVICE PROGRAMMING 3.1 Blank Check The term "Blank Check" means to verify that the device has no programmed memory cells. All memories must be verified: code memory, data EEPROM, ID locations and Configuration bits. The Device ID registers (3FFFFEh:3FFFFFh) should be ignored. 3.2 High-Voltage ICSP Bulk Erase Erasing code or data EEPROM is accomplished by writing an "erase option" to address 3C0004h. Code memory may be erased, portions at a time, or the user may erase the entire device in one action. "Bulk Erase" operations will also clear any code-protect settings associated with the memory block erased. Erase options are detailed in Table 3-1. A "blank" or "erased" memory cell will read as `1'. So, "Blank Checking" a device merely means to verify that all bytes read as FFh except the Configuration bits. Unused (reserved) Configuration bits will read as `0' (programmed). Refer to Table 5-2 for blank configuration expected data for the various devices. TABLE 3-1: If it is determined that the device is not blank, then the device should be Bulk Erased (see Section 3.2 "HighVoltage ICSP Bulk Erase") before any attempt to program is made. Given that "Blank Checking" is merely code and data EEPROM verification, with FFh as the expected data, refer to Section 4.1 "Read Data EEPROM Memory" and Section 4.3 "Verify Code Memory and ID Locations" for implementation details. FIGURE 3-1: BLANK CHECK FLOW Description Chip Erase 80h Erase Data EEPROM 81h Erase Boot Block 83h Erase Block 0 88h Erase Block 1 89h Erase Block 2 8Ah Erase Block 3 8Bh The actual Bulk Erase function is a self-timed operation. Once the erase has started (falling edge of the 4th PGC after the write command), serial execution will cease until the erase completes (parameter P11). During this time, PGC may continue to toggle, but PGD must be held low. Note: Blank Check Device A Bulk Erase is the only way to reprogram code-protect bits from an ON state to an OFF state. TABLE 3-2: Yes BULK ERASE COMMAND SEQUENCE Continue 4-Bit Data Command Payload No Bulk Erase Device Blank Check Device Is device blank? Data The code sequence to erase the entire device is shown in Table 3-2 and the flowchart is shown in Figure 3-2. Start Is device blank? BULK ERASE OPTIONS Yes Continue 0000 0000 0000 0000 0000 0000 1100 0E 6E 0E 6E 0E 6E 00 0000 0000 00 00 00 00 3C F8 00 F7 04 F6 80 Core Instruction MOVLW 3Ch MOVWF TBLPTRU MOVLW 00h MOVWF TBLPTRH MOVLW 04h MOVWF TBLPTRL Write 80h TO 3C0004h to erase entire device. NOP Hold PGD low until erase completes. No Abort DS39592F-page 10 2010 Microchip Technology Inc. PIC18FX220/X320 FIGURE 3-2: BULK ERASE FLOW 3.2.1 LOW-VOLTAGE ICSP BULK ERASE When using low-voltage ICSP, the part must be supplied by the voltage specified in parameter D111 if a Bulk Erase is to be executed. All other Bulk Erase details as described above apply. Start Load Address Pointer to 3C0004h If it is determined that a program memory erase must be performed at a supply voltage below the Bulk Erase limit, refer to the erase methodology described in Section 3.3.1 "Modifying Code Memory". Write 80h to Erase Entire Device If it is determined that a data EEPROM erase must be performed at a supply voltage below the Bulk Erase limit, follow the methodology described in Section 3.4 "Data EEPROM Programming" and write zeros to the array. Delay P11 + P10 Time Done FIGURE 3-3: BULK ERASE TIMING P10 1 2 3 4 1 2 15 16 1 2 3 4 1 2 15 16 1 2 3 1 4 2 PGC PGD 0 0 1 1 4-Bit Command 0 0 0 16-Bit Data Payload 0 P5A P5 P5A P5 0 0 0 0 0 4-Bit Command 0 0 0 P11 0 0 0 0 4-Bit Command NOP n Erase Time n 16-Bit Data Payload PGD = Input 3.3 Code Memory Programming Programming code memory is accomplished by first loading data into the appropriate write buffers and then initiating a programming sequence. Each panel in the code memory space (see Figure 2-7 and Figure 2-8) has an 8-byte deep write buffer that must be loaded prior to initiating a write sequence. The actual memory write sequence takes the contents of these buffers and programs the associated EEPROM code memory. The programming duration is externally timed and is controlled by PGC. After a "Start Programming" command is issued (4-bit command, `1111'), a NOP is issued, where the 4th PGC is held high for the duration of the programming time, P9 (see Figure 3-6). 2010 Microchip Technology Inc. After PGC is brought low, the programming sequence is terminated. PGC must be held low for the time specified by parameter P10 to allow high-voltage discharge of the memory array. The code sequence to program a device is shown in Table 3-3. The flowchart shown in Figure 3-5 depicts the logic necessary to completely write a device. Note: The TBLPTR register must contain the same offset value when initiating the programming sequence as it did when the write buffers were loaded. DS39592F-page 11 PIC18FX220/X320 FIGURE 3-4: ERASE AND WRITE BOUNDARIES Unimplemented Read as `0' 8-Byte Write Buffer Panel 1 TBLPTR<21:13> = 0 Erase Region (64 bytes) TBLPTR<2:0> = 7 TBLPTR<2:0> = 6 TBLPTR<2:0> = 5 TBLPTR<2:0> = 4 TBLPTR<2:0> = 3 TBLPTR<2:0> = 2 TBLPTR<2:0> = 1 TBLPTR<2:0> = 0 Offset = TBLPTR<12:3> Offset = TBLPTR<12:6> Note: TBLPTR = TBLPTRU:TBLPTRH:TBLPTRL. DS39592F-page 12 2010 Microchip Technology Inc. PIC18FX220/X320 TABLE 3-3: 4-Bit Command WRITE CODE MEMORY CODE SEQUENCE Data Payload Core Instruction Step 1: Direct access to code memory. 0000 0000 8E A6 9C A6 BSF BCF EECON1, EEPGD EECON1, CFGS MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF Write Write Write Write NOP - <Addr[21:16]> TBLPTRU <Addr[15:8]> TBLPTRH <Addr[7:0]> TBLPTRL 2 bytes and post-increment address by 2 2 bytes and post-increment address by 2 2 bytes and post-increment address by 2 2 bytes and start programming hold PGC high for time P9 Step 2: Load write buffer for Panel 1. 0000 0000 0000 0000 0000 0000 1101 1101 1101 1111 0000 0E <Addr[21:16]> 6E F8 0E <Addr[15:8]> 6E F7 0E <Addr[7:0]> 6E F6 <LSB><MSB> <LSB><MSB> <LSB><MSB> <LSB><MSB> 00 00 To continue writing data, repeat step 2, where the Address Pointer is incremented by 8 at each iteration of the loop. FIGURE 3-5: PROGRAM CODE MEMORY FLOW Start LoopCount = 0 Load 8 Bytes to Panel Write Buffer at <Addr> Start Write Sequence and Hold PGC High Until Done LoopCount = LoopCount + 1 Delay P9 + P10 Time for Write to Occur No All locations done? Yes Done 2010 Microchip Technology Inc. DS39592F-page 13 PIC18FX220/X320 FIGURE 3-6: TABLE WRITE AND START PROGRAMMING INSTRUCTION TIMING (1111) P10 1 2 3 4 1 2 3 4 5 6 15 16 1 2 3 4 PGC 3 2 P9 P5A P5 PGD 1 1 1 1 1 4-Bit Command n n n n n n n n 0 16-Bit Data Payload 0 0 0 4-Bit Command 0 Programming Time 0 0 16-Bit Data Payload PGD = Input 3.3.1 MODIFYING CODE MEMORY All of the programming examples, up to this point, have assumed that the device is blank prior to programming. In fact, if the device is not blank, the direction has been to completely erase the device via a Bulk Erase operation (see Section 3.2 "High-Voltage ICSP Bulk Erase"). It may be the case, however, that the user wishes to modify only a section of an already programmed device. In such a situation, erasing the entire device is not a realistic option. The minimum amount of data that can be written to the device is 8 bytes. This is accomplished by loading the 8-byte write buffer for the panel and then initiating a write sequence. In this case, however, it is assumed that the address space to be written already has data in it (i.e., it is not blank). The minimum amount of code memory that may be erased at a given time is one row of 64 bytes and it is selected using the TBLPTR registers. The sixth LSb of the TBLPTR address is ignored. The EECON1 register must then be used to erase the 64-byte target space prior to writing the data. This is known as a "Row Erase". DS39592F-page 14 When using the EECON1 register to act on code memory, the EEPGD bit must be set (EECON1<7> = 1) and the CFGS bit must be cleared (EECON1<6> = 0). The WREN bit must be set (EECON1<2> = 1) to enable writes of any sort (e.g., erases), and this must be done prior to initiating a write sequence. The FREE bit must be set (EECON1<4> = 1) in order to erase the program space being pointed to by the Table Pointer. The erase sequence is initiated by the setting the WR bit (EECON1<1> = 1). It is strongly recommended that the WREN bit be set only when absolutely necessary. To help prevent inadvertent writes when using the EECON1 register, EECON2 is used to "enable" the WR bit. This register must be sequentially loaded with 55h, and then 0AAh, immediately prior to asserting the WR bit in order for the write to occur. The erase will begin on the falling edge of the 4th PGC after the WR bit is set. After the erase sequence terminates, PGC must still be held low for the time specified by parameter P10 to allow high-voltage discharge of the memory array. 2010 Microchip Technology Inc. PIC18FX220/X320 TABLE 3-4: MODIFYING CODE MEMORY 4-Bit Command Data Payload Core Instruction Step 1: Direct access to code memory. 0000 0000 8E A6 9C A6 BSF BCF EECON1, EEPGD EECON1, CFGS Step 2: Set the Table Pointer for the block to be erased. 0000 0000 0000 0000 0000 0000 0E 6E 0E 6E 0E 6E <Addr[21:16]> F8 <Addr[15:8]> F7 <Addr[7:0]> F6 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF <Addr[21:16]> TBLPTRU <Addr[15:8]> TBLPTRH <Addr[7:0]> TBLPTRL Step 3: Enable memory writes and set up an erase. 0000 0000 84 A6 88 A6 BSF BSF EECON1, WREN EECON1, FREE MOVLW MOVWF MOVLW MOVWF 0X55 EECON2 0XAA EECON2 BSF NOP EECON1, WR Step 4: Perform Flash unlock sequence. 0000 0000 0000 0000 0E 6E 0E 6E 55 A7 AA A7 Step 5: Initiate erase. 0000 0000 82 A6 00 00 Step 6: Wait for P11 + P10 and then disable writes. 0000 94 A6 BCF EECON1, WREN Write Write Write Write NOP - 2 bytes and post-increment address by 2 2 bytes and post-increment address by 2 2 bytes and post-increment address by 2 2 bytes and start programming hold PGC high for time P9 at the end of 4-bit command Step 7: Load write buffer for panel. 1101 1101 1101 1111 0000 <LSB><MSB> <LSB><MSB> <LSB><MSB> <LSB><MSB> 00 00 To continue writing data, repeat step 7, where the Address Pointer is incremented by 8 at each iteration of the loop. 2010 Microchip Technology Inc. DS39592F-page 15 PIC18FX220/X320 3.4 FIGURE 3-7: Data EEPROM Programming PROGRAM DATA FLOW Data EEPROM is accessed one byte at a time via an Address Pointer, EEADR, and a Data Latch, EEDATA. Data EEPROM is written by loading EEADR with the desired memory location, loading EEDATA with the data to be written and initiating a memory write by appropriately configuring the EECON1 and EECON2 registers. A byte write automatically erases the location and writes the new data (erase-before-write). Start Set Address Set Data When using the EECON1 register to perform a data EEPROM write, the EEPGD bit must be cleared (EECON1<7> = 0) and the CFGS bit must be cleared (EECON1<6> = 0). The WREN bit must be set (EECON1<2> = 1) to enable writes of any sort and this must be done prior to initiating a write sequence. Enable Write Unlock Sequence 55h - EECON2 0AAh - EECON2 To help prevent inadvertent writes when using the EECON1 register, EECON2 is used to "enable" the WR bit. This register must be sequentially loaded with 55h, and then 0AAh, immediately prior to asserting the WR bit in order for the write to occur. The write sequence is initiated by setting the WR bit (EECON1<1> = 1). It is strongly recommended that the WREN bit be set only when absolutely necessary. Start Write Sequence Delay P11 + P10 for Write to Occur The write will begin on the falling edge of the 4th PGC after the WR bit is set. No Done? Yes After the programming sequence terminates, PGC must still be held low for the time specified by parameter P10 to allow high-voltage discharge of the memory array. FIGURE 3-8: Done DATA EEPROM WRITE TIMING P11 1 2 3 4 1 2 15 16 1 2 3 4 1 2 15 16 1 2 3 1 4 2 PGC P5A P5 PGD 0 0 0 0 4-Bit Command 0 BSF EECON1, WR P5A P5 0 0 0 0 4-Bit Command 0 0 16-Bit Data Payload 0 P11 0 0 0 n 0 4-Bit Command Data EEPROM Write Time n 16-Bit Data Payload PGD = Input DS39592F-page 16 2010 Microchip Technology Inc. PIC18FX220/X320 TABLE 3-5: PROGRAMMING DATA MEMORY 4-Bit Command Data Payload Core Instruction Step 1: Direct access to data EEPROM. 0000 0000 9E A6 9C A6 BCF BCF EECON1, EEPGD EECON1, CFGS Step 2: Set the data EEPROM Address Pointer. 0000 0000 0E <Addr> 6E A9 MOVLW <Addr> MOVWF EEADR Step 3: Load the data to be written. 0000 0000 0E <Data> 6E A8 MOVLW <Data> MOVWF EEDATA Step 4: Enable memory writes. 0000 84 A6 BSF EECON1, WREN Step 5: Perform data EEPROM unlock sequence. 0000 0000 0000 0000 0E 6E 0E 6E 55 A7 AA A7 MOVLW MOVWF MOVLW MOVWF 0X55 EECON2 0XAA EECON2 BSF NOP NOP EECON1, WR BCF EECON1, WREN Step 6: Initiate write. 0000 0000 0000 82 A6 00 00 00 00 Step 7: Wait for P11 and then disable writes. 0000 94 A6 Repeat steps 2 through 7 to write more data. 2010 Microchip Technology Inc. DS39592F-page 17 PIC18FX220/X320 3.5 ID Location Programming The ID locations are programmed much like the code memory. The single panel that will be written will automatically be enabled, based on the value of the Table Pointer. The ID registers are mapped in addresses 200000h through 200007h. These locations read out normally, even after code protection. Note: Table 3-6 demonstrates the code sequence required to write the ID locations. The Table Pointer must be manually set to 200000h (base address of the ID locations). The post-increment feature of the table read 4-bit command may not be used to increment the Table Pointer to 200000h. The post-increment feature may then be used to increment to 200001h, 200002h, etc. The user must fill the 8-byte data buffer for the panel. TABLE 3-6: WRITE ID SEQUENCE 4-Bit Command Data Payload Core Instruction Step 1: Direct access to code memory. 0000 0000 8E A6 9C A6 BSF BCF EECON1, EEPGD EECON1, CFGS MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF Write Write Write Write NOP - 20h TBLPTRU 00h TBLPTRH 00h TBLPTRL 2 bytes and post-increment address by 2 2 bytes and post-increment address by 2 2 bytes and post-increment address by 2 2 bytes and start programming hold PGC high for time P9 Step 2: Load write buffer. 0000 0000 0000 0000 0000 0000 1101 1101 1101 1111 0000 0E 20 6E F8 0E 00 6E F7 0E 00 6E F6 <LSB><MSB> <LSB><MSB> <LSB><MSB> <LSB><MSB> 00 00 DS39592F-page 18 2010 Microchip Technology Inc. PIC18FX220/X320 3.6 Boot Block Programming 3.7 The Boot Block segment is programmed in exactly the same manner as the ID locations (see Section 3.5 "ID Location Programming"). The code sequence detailed in Table 3-6 should be used, except that the address data used in "Step 2" will be in the range of 000000h to 0001FFh. TABLE 3-7: 4-Bit Command Configuration Bits Programming Unlike code memory, the Configuration bits are programmed a byte at a time. The "Table Write, Begin Programming" 4-bit command (1111) is used, but only 8 bits of the following 16-bit payload will be written. The LSB of the payload will be written to even addresses and the MSB will be written to odd addresses. The code sequence to program two consecutive configuration locations is shown in Table 3-7. SET ADDRESS POINTER TO CONFIGURATION LOCATION Data Payload Core Instruction Step 1: Direct access to configuration memory. 8E A6 8C A6 0000 0000 BSF BSF EECON1, EEPGD EECON1, CFGS GOTO 0x100000 Step 2: Position the program counter.(1) 0000 0000 EF 00 F8 00 Step 3: Set Table Pointer for Configuration Word to be written. Write even/odd addresses. 0000 0000 0000 0000 0000 0000 1111 0000 0000 1111 0000 Note 1: 2: 0E 30 6E F8 0E 00 6E F7 0E 00 6E F6 <LSB><MSB ignored> 00 00 2A F6 <LSB ignored><MSB> 00 00 MOVLW 30h MOVWF TBLPTRU MOVLW 00h MOVWF TBLPRTH MOVLW 00h MOVWF TBLPTRL Load 2 bytes and start programming NOP - hold PGC high for time P9 INCF TBLPTRL Load 2 bytes and start programming NOP - hold PGC high for time P9 If the code protection bits are programmed while the program counter resides in the same block, then the interaction of code protection logic may prevent further table writes. To avoid this situation, move the program counter outside the code protection area (e.g., GOTO 0x100000). Enabling the write protection of Configuration bits (WRTC = 0 in CONFIG6H) will prevent further writing of Configuration bits. Always write all the Configuration bits before enabling the write protection for Configuration bits. FIGURE 3-9: CONFIGURATION PROGRAMMING FLOW Start Start Load Even Configuration Address Load Odd Configuration Address Program LSB Program MSB Delay P9 Time for Write Delay P9 Time for Write Done Done 2010 Microchip Technology Inc. DS39592F-page 19 PIC18FX220/X320 4.0 READING THE DEVICE 4.1 Read Data EEPROM Memory FIGURE 4-1: READ DATA EEPROM FLOW Start Data EEPROM is accessed one byte at a time via an Address Pointer, EEADR, and a Data Latch, EEDATA. Data EEPROM is read by loading EEADR with the desired memory location and initiating a memory read by appropriately configuring the EECON1 register. The data will be loaded into EEDATA, where it may be serially output on PGD via the 4-bit command, `0010' (Shift Out Data Holding register). A delay of P6 must be introduced after the falling edge of the 8th PGC of the operand to allow PGD to transition from an input to an output. During this time, PGC must be held low (see Figure 4-2). Set Address Read Byte Move to TABLAT Shift Out Data The command sequence to read a single byte of data is shown in Table 4-1. No Done? Yes Done TABLE 4-1: READ DATA EEPROM MEMORY 4-Bit Command Data Payload Core Instruction Step 1: Direct access to data EEPROM. 0000 0000 9E A6 9C A6 BCF BCF EECON1, EEPGD EECON1, CFGS Step 2: Set the data EEPROM Address Pointer. 0000 0000 0E <Addr> 6E A9 MOVLW <Addr> MOVWF EEADR Step 3: Initiate a memory read. 0000 80 A6 BSF EECON1, RD Step 4: Load data into the Serial Data Holding register. 0000 0000 0010 Note 1: 50 A8 6E F5 <LSB><MSB> MOVF EEDATA, W, 0 MOVWF TABLAT Shift Out Data(1) The <LSB> is undefined. The <MSB> is the data. FIGURE 4-2: 1 SHIFT OUT DATA HOLDING REGISTER TIMING (0010) 2 3 4 1 2 3 4 5 6 7 9 8 10 11 12 13 14 15 16 1 2 3 4 PGC P5 P5A P6 P14 PGD 0 1 0 LSb 1 0 2 3 4 5 Shift Data Out PGD = Input DS39592F-page 20 PGD = Output 6 MSb n n n n Fetch Next 4-Bit Command PGD = Input 2010 Microchip Technology Inc. PIC18FX220/X320 4.2 Read Code Memory, ID Locations and Configuration Bits P6 must be introduced after the falling edge of the 8th PGC of the operand to allow PGD to transition from an input to an output. During this time, PGC must be held low (see Table 4-2). This operation also increments the Table Pointer by one, pointing to the next byte in code memory for the next read. Code memory is accessed one byte at a time via the 4-bit command, `1001' (table read, post-increment). The contents of memory pointed to by the Table Pointer (TBLPTRU:TBLPTRH:TBLPTRL) are loaded into the Table Latch and then serially output on PGD. This technique will work to read any memory in the 000000h to 3FFFFFh address space, so it also applies to the reading of the ID and Configuration registers. The 4-bit command is shifted in LSb first. The read is executed during the next 8 clocks, then shifted out on PGD during the last 8 clocks, LSb to MSb. A delay of TABLE 4-2: READ CODE MEMORY SEQUENCE 4-Bit Command Data Payload Core Instruction Step 1: Set Table Pointer. 0000 0000 0000 0000 0000 0000 0E 6E 0E 6E 0E 6E <Addr[21:16]> F8 <Addr[15:8]> F7 <Addr[7:0]> F6 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF Addr[21:16] TBLPTRU <Addr[15:8]> TBLPTRH <Addr[7:0]> TBLPTRL Step 2: Read memory into Table Latch and then shift out on PGD, LSb to MSb. 1001 00 00 FIGURE 4-3: 1 TBLRD *+ TABLE READ, POST-INCREMENT INSTRUCTION TIMING (1001) 2 3 1 4 2 3 4 5 6 7 9 8 1 10 11 12 13 14 15 16 2 3 4 PGC P5 P5A P6 P14 PGD 1 0 0 LSb 1 1 2 3 4 5 Shift Data Out PGD = Input 2010 Microchip Technology Inc. PGD = Output 6 MSb n n n n Fetch Next 4-Bit Command PGD = Input DS39592F-page 21 PIC18FX220/X320 4.3 Verify Code Memory and ID Locations The verify step involves reading back the code memory space and comparing it against the copy held in the programmer's buffer. Memory reads occur a single byte at a time, so two bytes must be read to compare against the word in the programmer's buffer. Refer to Section 4.2 "Read Code Memory, ID Locations and Configuration Bits" for implementation details of reading code memory. FIGURE 4-4: The Table Pointer must be manually set to 200000h (base address of the ID locations). The post-increment feature of the table read 4-bit command may not be used to increment the Table Pointer to 200000h. The post-increment feature may then be used to increment to 200001h, 200002h, etc. VERIFY CODE MEMORY FLOW Start Set Pointer = 0 Set Pointer = 200000h Read Low Byte Read Low Byte Read High Byte Read High Byte Does word = expect data? No Does word = expect data? Failure, Report Error Yes No No Failure, Report Error Yes All code memory verified? No All ID locations verified? Yes Yes Done 4.4 Verify Configuration Bits A configuration address may be read and output on PGD via the 4-bit command, `1001'. Configuration data is read and written in a byte-wise fashion, so it is not necessary to merge two bytes into a word prior to a compare. The result may then be immediately compared to the appropriate configuration data in the programmer's memory for verification. Refer to Section 4.2 "Read Code Memory, ID Locations and Configuration Bits" for implementation details of reading configuration data. DS39592F-page 22 4.5 Verify Data EEPROM A data EEPROM address may be read via a sequence of core instructions (4-bit command, `0000') and then output on PGD via the 4-bit command, `0010' (Shift Out Data Holding register). The result may then be immediately compared to the appropriate data in the programmer's memory for verification. Refer to Section 4.1 "Read Data EEPROM Memory" for implementation details of reading data EEPROM. 2010 Microchip Technology Inc. PIC18FX220/X320 5.0 CONFIGURATION WORD 5.3 The LVP bit in Configuration register, CONFIG4L, enables Single-Supply (Low-Voltage) ICSP Programming mode. The LVP bit defaults to a `1' (enabled) following an erase. The devices have several Configuration Words. Bits in these registers can be set or cleared to select various device configurations. All other memory areas should be programmed and verified prior to setting Configuration Words. These bits may be read out normally, even after read or code-protected. Tables 5-2, 5-3 and 5-4 provide information on various Configuration bits. 5.1 If Single-Supply Programming mode is not used, the LVP bit can be programmed to a `0' and RB5/PGM becomes a digital I/O pin. However, the LVP bit may only be programmed by entering the High-Voltage ICSP mode, where MCLR/VPP is raised to VIHH. Once the LVP bit is programmed to a `0', only the High-Voltage ICSP mode is available and only the High-Voltage ICSP mode can be used to program the device. ID Locations A user may store identification information (ID) in eight ID locations mapped in 200000h:200007h. It is recommended that the most significant nibble of each ID be 0Fh. In doing so, if the user code inadvertently tries to execute from the ID space, the ID data will execute as a NOP. 5.2 Note 1: The normal High-Voltage ICSP mode is always available, regardless of the state of the LVP bit, by applying VIHH to the MCLR/VPP pin. Device ID Word 2: While in Low-Voltage ICSP mode, the RB5 pin can no longer be used as a general purpose I/O. The Device ID Word for the devices is located at 3FFFFEh:3FFFFFh. These bits may be used by the programmer to identify what device type is being programmed and read out normally, even after code or read protection. TABLE 5-1: Single-Supply ICSP Programming DEVICE ID VALUE Device ID Value Device DEVID2 DEVID1 PIC18F1220 07 111x xxxx PIC18F2220 05 100x xxxx PIC18F4220 05 101x xxxx PIC18F1320 07 110x xxxx PIC18F2320 05 000x xxxx PIC18F4320 05 001x xxxx 2010 Microchip Technology Inc. DS39592F-page 23 PIC18FX220/X320 TABLE 5-2: PIC18F2X20/4X20 CONFIGURATION BITS AND DEVICE IDs File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Erased or "Blank" Value ---- ---- 300000h CONFIG1L -- -- -- -- -- -- -- -- 300001h CONFIG1H IESO FSCM -- -- FOSC3 FOSC2 FOSC1 FOSC0 11-- 1111 300002h CONFIG2L -- -- -- -- BORV1 BORV0 BOR PWRT ---- 1111 300003h CONFIG2H -- -- -- WDT ---1 1111 300004h CONFIG3L -- -- -- -- -- -- -- -- ---- ---- 300005h CONFIG3H MCLRE -- -- -- -- -- PBAD CCP2MX 1--- --11 300006h CONFIG4L DEBUG -- -- -- -- LVP -- STVR 1--- -1-1 300007h CONFIG4H -- -- -- -- -- -- -- -- ---- ---- 300008h CONFIG5L -- -- -- -- CP3(1) CP2(1) CP1 CP0 ---- 1111 300009h CONFIG5H CPD CPB -- -- -- -- -- -- 11-- ---- 30000Ah CONFIG6L -- -- -- -- WRT3(1) WRT2(1) WRT1 WRT0 ---- 1111 30000Bh CONFIG6H WRTD WRTB WRTC -- -- -- -- -- 111- ---- 30000Ch CONFIG7L -- -- -- -- EBTR1 EBTR0 ---- 1111 30000Dh CONFIG7H -- EBTRB -- -- -- -- -1-- ---- WDTPS3 WDTPS2 WDTPS1 WDTPS0 EBTR3(1) EBTR2(1) -- -- 3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 Table 5-1 3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 Table 5-1 Bit 1 Bit 0 Erased or "Blank" Value Legend: Note 1: - = unimplemented. Shaded cells are unimplemented, read as `0'. Unimplemented in PIC18F2220 and PIC18F4220 devices, read as `0'. TABLE 5-3: PIC18F1X20 CONFIGURATION BITS AND DEVICE IDs File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 300000h CONFIG1L -- -- -- -- -- -- -- -- ---- ---- 300001h CONFIG1H IESO FSCM -- -- FOSC3 FOSC2 FOSC1 FOSC0 11-- 1111 300002h CONFIG2L -- -- -- -- BORV1 BORV0 BOR PWRTEN ---- 1111 300003h CONFIG2H -- -- -- WDTPS3 300004h CONFIG3L -- -- -- -- -- -- 300005h CONFIG3H MCLRE -- -- -- -- 300006h CONFIG4L DEBUG -- -- -- 300007h CONFIG4H -- -- -- -- 300008h CONFIG5L -- -- -- WDTPS2 WDTPS1 WDTPS0 WDT ---1 1111 -- -- ---- ---- -- -- -- 1--- ---- -- LVP -- STVR 1--- -1-1 -- -- -- -- ---- ---- -- -- -- CP1 CP0 ---- --11 11-- ---- 300009h CONFIG5H CPD CPB -- -- -- -- -- -- 30000Ah CONFIG6L -- -- -- -- -- -- WRT1 WRT0 ---- --11 30000Bh CONFIG6H WRTD WRTB WRTC -- -- -- -- -- 111- ---- 30000Ch CONFIG7L -- -- -- -- -- -- EBTR1 EBTR0 ---- --11 -1-- ---- -- EBTRB -- -- -- -- -- -- 3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 Table 5-1 3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 Table 5-1 30000Dh CONFIG7H Legend: - = Unimplemented. Shaded cells are unimplemented, read as `0'. DS39592F-page 24 2010 Microchip Technology Inc. PIC18FX220/X320 TABLE 5-4: Bit Name PIC18FX220/X320 BIT DESCRIPTIONS Configuration Words Description IESO CONFIG1H Internal External Switchover bit 1 = Internal External Switchover mode enabled 0 = Internal External Switchover mode disabled FSCM CONFIG1H Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled FOSC3:FOSC0 CONFIG1H Oscillator Selection bits 11xx = External RC oscillator, CLKO function on RA6 101x = External RC oscillator, CLKO function on RA6 1001 = Internal RC oscillator, CLKO function on RA6, port function on RA7 1000 = Internal RC oscillator, port function on RA6, port function on RA7 0111 = External RC oscillator, port function on RA6 0110 = HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) 0101 = EC oscillator, port function on RA6 0100 = EC oscillator, CLKO function on RA6 0011 = External RC oscillator, CLKO function on RA6 0010 = HS oscillator 0001 = XT oscillator 0000 = LP oscillator BORV1:BORV0 CONFIG2L Brown-out Reset Voltage bits 11 = Reserved 10 = VBOR set to 2.7V 01 = VBOR set to 4.2V 00 = VBOR set to 4.5V BOR CONFIG2L Brown-out Reset Enable bit 1 = Brown-out Reset enabled 0 = Brown-out Reset disabled PWRT CONFIG2L Power-up Timer Enable bit for PIC18F2X20/4X20 1 = PWRT disabled 0 = PWRT enabled PWRTEN CONFIG2L Power-up Timer Enable bit for PIC18F1X20 1 = PWRT disabled 0 = PWRT enabled WDTPS3:WDTP S0 CONFIG2H Watchdog Timer Postscaler Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 WDT CONFIG2H Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on SWDTEN bit) 2010 Microchip Technology Inc. DS39592F-page 25 PIC18FX220/X320 TABLE 5-4: Bit Name PIC18FX220/X320 BIT DESCRIPTIONS (CONTINUED) Configuration Words Description MCLRE CONFIG3H MCLR Pin Enable bit for PIC18F2X20/4X20 1 = MCLR pin enabled, RE3 input pin disabled 0 = RE3 input pin enabled, MCLR pin disabled MCLRE CONFIG3H MCLR Pin Enable bit for PIC18F1X20 1 = MCLR pin enabled, RA5 input pin disabled 0 = RA5 input pin enabled, MCLR pin disabled PBAD CONFIG3H PORTB A/D Enable bit for PIC18F2X20/4X20 1 = PORTB A/D<4:0> pins are configured as analog input channels on Reset 0 = PORTB A/D<4:0> pins are configured as digital I/O on Reset CCP2MX CONFIG3H CCP2 MUX bit for PIC18F2X20/4X20 1 = CCP2 input/output is multiplexed with RC1 0 = CCP2 input/output is multiplexed with RB3 DEBUG CONFIG4L In-Circuit Debugger Enable bit 1 = In-Circuit Debugger disabled (RB6, RB7 have I/O port function) 0 = In-Circuit Debugger enabled (RB6, RB7 have ICSPTM serial communication function) LVP CONFIG4L Low-Voltage Programming Enable bit 1 = Low-Voltage Programming enabled, RB5 is the PGM pin 0 = Low-Voltage Programming disabled, RB5 is an I/O pin STVR CONFIG4L Stack Overflow/Underflow Reset Enable bit 1 = Reset on stack overflow/underflow enabled 0 = Reset on stack overflow/underflow disabled CP3 CONFIG5L Code Protection bit for PIC18F2320/4320 (Block 3 code memory area: 001800h-001FFFh, unimplemented in PIC18F2220/4220) 1 = Block 3 is not code-protected 0 = Block 3 is code-protected CP2 CONFIG5L Code Protection bit for PIC18F2320/4320 (Block 2 code memory area: 001000h-0017FFh, unimplemented in PIC18F2220/4220) 1 = Block 2 is not code-protected 0 = Block 2 is code-protected CP1 CONFIG5L Code Protection bit for PIC18F1220 (Block 1 code memory area: 000800h-000FFFh) 1 = Block 1 is not code-protected 0 = Block 1 is code-protected CP1 CONFIG5L Code Protection bit for PIC18F1320 (Block 1 code memory area: 001000h-001FFFh) 1 = Block 1 is not code-protected 0 = Block 1 is code-protected CP1 CONFIG5L Code Protection bit for PIC18F2X20/4X20 (Block 1 code memory area: 000800h-000FFFh) 1 = Block 1 is not code-protected 0 = Block 1 is code-protected CP0 CONFIG5L Code Protection bit for PIC18F1220 (Block 0 code memory area: 000200h-0007FFh) 1 = Block 0 is not code-protected 0 = Block 0 is code-protected CP0 CONFIG5L Code Protection bit for PIC18F1320 (Block 0 code memory area: 000200h-000FFFh) 1 = Block 0 is not code-protected 0 = Block 0 is code-protected CP0 CONFIG5L Code Protection bit for PIC18F2X20/4X20 (Block 0 code memory area: 000200h-0007FFh) 1 = Block 0 is not code-protected 0 = Block 0 is code-protected DS39592F-page 26 2010 Microchip Technology Inc. PIC18FX220/X320 TABLE 5-4: Bit Name PIC18FX220/X320 BIT DESCRIPTIONS (CONTINUED) Configuration Words Description CPD CONFIG5H Code Protection bit (Data EEPROM) 1 = Data EEPROM is not code-protected 0 = Data EEPROM is code-protected CPB CONFIG5H Code Protection bit (Boot Block memory area: 000000h-0001FFh) 1 = Boot Block is not code-protected 0 = Boot Block is code-protected WRT3 CONFIG6L Write Protection bit for PIC18F2320/4320 (Block 3 code memory area: 001800h-001FFFh, unimplemented in PIC18F2220/4220) 1 = Block 3 is not write-protected 0 = Block 3 is write-protected WRT2 CONFIG6L Write Protection bit for PIC18F2320/4320 (Block 2 code memory area: 001000h-0017FFh, unimplemented in PIC18F2220/4220) 1 = Block 2 is not write-protected 0 = Block 2 is write-protected WRT1 CONFIG6L Write Protection bit for PIC18F1220 (Block 1 code memory area: 000800h-000FFFh) 1 = Block 1 is not write-protected WRT1 CONFIG6L Write Protection bit for PIC18F1320 (Block 1 code memory area: 001000h-001FFFh) 1 = Block 1 is not write-protected 0 = Block 1 is write-protected WRT1 CONFIG6L Write Protection bit for PIC18F2X20/4X20 (Block 1 code memory area: 000800h-000FFFh) 1 = Block 1 is not write-protected 0 = Block 1 is write-protected WRT0 CONFIG6L Write Protection bit for PIC18F1220 (Block 0 code memory area: 000200h-0007FFh) 0 = Block 1 is write-protected 1 = Block 0 is not write-protected 0 = Block 0 is write-protected WRT0 CONFIG6L Write Protection bit for PIC18F1320 (Block 0 code memory area: 000200h-000FFFh) 1 = Block 0 is not write-protected 0 = Block 0 is write-protected WRT0 CONFIG6L Write Protection bit for PIC18F2X20/4X20 (Block 0 code memory area: 000200h-0007FFh) 1 = Block 0 is not write-protected 0 = Block 0 is write-protected WRTD CONFIG6H Write Protection bit (Data EEPROM) 1 = Data EEPROM is not write-protected 0 = Data EEPROM is write-protected WRTB CONFIG6H Write Protection bit (Boot Block memory area: 000000h-0001FFh) 1 = Boot Block is not write-protected 0 = Boot Block is write-protected WRTC CONFIG6H Write Protection bit (Configuration registers: 300000h-3000FFh) 1 = Configuration registers are not write-protected 0 = Configuration registers are write-protected EBTR3 CONFIG7L Table Read Protection bit for PIC18F2320/4320 (Block 3 code memory area: 001800h-001FFFh, unimplemented in PIC18F2220/4220) 1 = Block 3 is not protected from table reads executed in other blocks 0 = Block 3 is protected from table reads executed in other blocks EBTR2 CONFIG7L Table Read Protection bit for PIC18F2320/4320 (Block 2 code memory area: 001000h-0017FFh, unimplemented in PIC18F2220/4220) 1 = Block 2 is not protected from table reads executed in other blocks 0 = Block 2 is protected from table reads executed in other blocks 2010 Microchip Technology Inc. DS39592F-page 27 PIC18FX220/X320 TABLE 5-4: Bit Name PIC18FX220/X320 BIT DESCRIPTIONS (CONTINUED) Configuration Words Description EBTR1 CONFIG7L Table Read Protection bit for PIC18F1220 (Block 1 code memory area: 000800h-000FFFh) 1 = Block 1 is not protected from table reads executed in other blocks 0 = Block 1 is protected from table reads executed in other blocks EBTR1 CONFIG7L Table Read Protection bit for PIC18F1320 (Block 1 code memory area: 001000h-001FFFh) 1 = Block 1 is not protected from table reads executed in other blocks 0 = Block 1 is protected from table reads executed in other blocks EBTR1 CONFIG7L Table Read Protection bit for PIC18F2X20/4X20 (Block 1 code memory area: 000800h-000FFFh) 1 = Block 1 is not protected from table reads executed in other blocks 0 = Block 1 is protected from table reads executed in other blocks EBTR0 CONFIG7L Table Read Protection bit for PIC18F1220 (Block 0 code memory area: 000200h-0007FFh) 1 = Block 0 is not protected from table reads executed in other blocks 0 = Block 0 is protected from table reads executed in other blocks EBTR0 CONFIG7L Table Read Protection bit for PIC18F1320 (Block 0 code memory area: 000200h-000FFFh) 1 = Block 0 is not protected from table reads executed in other blocks 0 = Block 0 is protected from table reads executed in other blocks EBTR0 CONFIG7L Table Read Protection bit for PIC18F2X20/4X20 (Block 0 code memory area: 000200h-0007FFh) 1 = Block 0 is not protected from table reads executed in other blocks 0 = Block 0 is protected from table reads executed in other blocks EBTRB CONFIG7H Table Read Protection bit (Boot Block memory area: 000000h-0001FFh) 1 = Boot Block is not protected from table reads executed in other blocks 0 = Boot Block is protected from table reads executed in other blocks DEV10:DEV3 DEVID2 Device ID bits These bits are used with the DEV2:DEV0 bits in the DEVID1 register to identify the part number. DEV2:DEV0 DEVID1 Device ID bits These bits are used with the DEV10:DEV3 bits in the DEVID2 register to identify the part number. REV4:REV0 DEVID1 Revision ID bits These bits are used to indicate the revision of the device. DS39592F-page 28 2010 Microchip Technology Inc. PIC18FX220/X320 5.4 Embedding Configuration Word Information in the HEX File To allow portability of code, a device programmer is required to read the Configuration Word locations from the hex file. If Configuration Word information is not present in the hex file, then a simple warning message should be issued. Similarly, while saving a hex file, all Configuration Word information must be included. An option to not include the Configuration Word information may be provided. When embedding Configuration Word information in the hex file, it should start at address 300000h. Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer. 5.5 Embedding Data EEPROM Information in the HEX File To allow portability of code, a device programmer is required to read the data EEPROM information from the hex file. If data EEPROM information is not present, a simple warning message should be issued. Similarly, when saving a hex file, all data EEPROM information must be included. An option to not include the data EEPROM information may be provided. When embedding data EEPROM information in the hex file, it should start at address F00000h. 5.6 Checksum Computation The checksum is calculated by summing the following: * The contents of all code memory locations * The Configuration Word, appropriately masked * ID locations The Least Significant 16 bits of this sum are the checksum. Table 5-5 describes how to calculate the checksum for each device. Note: The checksum calculation differs depending on the code-protect setting. Since the code memory locations read out differently depending on the code-protect setting, the table describes how to manipulate the actual code memory values to simulate the values that would be read from a protected device. When calculating a checksum by reading a device, the entire code memory can simply be read and summed. The Configuration Word and ID locations can always be read. Microchip Technology Inc. believes that this feature is important for the benefit of the end customer. 2010 Microchip Technology Inc. DS39592F-page 29 PIC18FX220/X320 TABLE 5-5: Device CHECKSUM COMPUTATION - PIC18FX220/X320 Code-Protect Blank Value 0xAA at 0 and Max Address None SUM (0000:01FFh) + SUM (0200:0FFFh) + SUM (1000:1FFFh) + (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 080h) + (CONFIG4L & 085h) + (CONFIG5L & 03h) + (CONFIG5H & 0C0h) + (CONFIG6L & 03h) + (CONFIG6H & 0E0h) + (CONFIG7L & 03h) + (CONFIG7H & 040h) F3EB F341 Boot Block SUM (0200:0FFFh) + SUM (1000:1FFFh) + (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 080h) + (CONFIG4L & 085h) + (CONFIG5L & 03h) + (CONFIG5H & 0C0h) + (CONFIG6L & 03h) + (CONFIG6H & 0E0h) + (CONFIG7L & 03h) + (CONFIG7H & 040h) + SUM (IDs) F5D6 F56D Boot/ Panel 1/ Panel 2 (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 080h) + (CONFIG4L & 085h) + (CONFIG5L & 03h) + (CONFIG5H & 0C0h) + (CONFIG6L & 03h) + (CONFIG6H & 0E0h) + (CONFIG7L & 03h) + (CONFIG7H & 040h) + SUM (IDs) 03D3 03BF All (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 080h) + (CONFIG4L & 085h) + (CONFIG5L & 03h) + (CONFIG5H & 0C0h) + (CONFIG6L & 03h) + (CONFIG6H & 0E0h) + (CONFIG7L & 03h) + (CONFIG7H & 040h) + SUM (IDs) 03D3 03BF None SUM (0000:01FFh) + SUM (0200:07FFh) + SUM (0800:0FFFh) + (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 080h) + (CONFIG4L & 085h) + (CONFIG5L & 03h) + (CONFIG5H & 0C0h) + (CONFIG6L & 03h) + (CONFIG6H & 0E0h) + (CONFIG7L & 03h) + (CONFIG7H & 040h) E3EB E341 Boot Block SUM (0200:07FFh) + SUM (0800:0FFFh) + (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 080h) + (CONFIG4L & 085h) + (CONFIG5L & 03h) + (CONFIG5H & 0C0h) + (CONFIG6L & 03h) + (CONFIG6H & 0E0h) + (CONFIG7L & 03h) + (CONFIG7H & 040h) + SUM (IDs) E5D5 E56C Boot/ Panel 1/ Panel 2 (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 080h) + (CONFIG4L & 085h) + (CONFIG5L & 03h) + (CONFIG5H & 0C0h) + (CONFIG6L & 03h) + (CONFIG6H & 0E0h) + (CONFIG7L & 03h) + (CONFIG7H & 040h) + SUM (IDs) 03D2 03BE All (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 083h) + (CONFIG4L & 085h) + (CONFIG5L & 0Fh) + (CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) + (CONFIG7L & 0Fh) + (CONFIG7H & 040h) + SUM (IDs) 03D2 03BE PIC18F1220 PIC18F1320 Legend: Checksum Item CONFIG SUM[a:b] SUM (IDs) + & DS39592F-page 30 = = = = = Description Configuration Word Sum of locations, a to b inclusive Byte-wise sum of lower four bits of all ID locations Addition Bit-wise AND 2010 Microchip Technology Inc. PIC18FX220/X320 TABLE 5-5: Device CHECKSUM COMPUTATION - PIC18FX220/X320 (CONTINUED) Code-Protect Blank Value 0xAA at 0 and Max Address None SUM (0000:01FFh) + SUM (0200:07FFh) + SUM (0800:0FFFh) + (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 083h) + (CONFIG4L & 085h) + (CONFIG5L & 0Fh) + (CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) + (CONFIG7L & 0Fh) + (CONFIG7H & 040h) 0F412h 0F368h Boot Block SUM (0200:07FFh) + SUM (0800:0FFFh) + (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 083h) + (CONFIG4L & 085h) + (CONFIG5L & 0Fh) + (CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) + (CONFIG7L & 0Fh) + (CONFIG7H & 040h) + SUM (IDs) 0F5E8h 0F59Dh SUM (0800:0FFFh) + (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 083h) + (CONFIG4L & 085h) + (CONFIG5L & 0Fh) + (CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) + (CONFIG7L & 0Fh) + (CONFIG7H & 040h) + SUM (IDs) 0FBE7h 0FB9Ch Boot Block/ Block 0/ Block 1 (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 083h) + (CONFIG4L & 085h) + (CONFIG5L & 0Fh) + (CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) + (CONFIG7L & 0Fh) + (CONFIG7H & 040h) + SUM (IDs) 03E5h 03EFh All (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 083h) + (CONFIG4L & 085h) + (CONFIG5L & 0Fh) + (CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) + (CONFIG7L & 0Fh) + (CONFIG7H & 040h) + SUM (IDs) 03E5h 03EFh Boot Block/ PIC18F2220/ Block 0 PIC18F4220 Legend: Checksum Item CONFIG SUM[a:b] SUM (IDs) + & = = = = = Description Configuration Word Sum of locations, a to b inclusive Byte-wise sum of lower four bits of all ID locations Addition Bit-wise AND 2010 Microchip Technology Inc. DS39592F-page 31 PIC18FX220/X320 TABLE 5-5: Device CHECKSUM COMPUTATION - PIC18FX220/X320 (CONTINUED) Code-Protect Checksum Blank Value 0xAA at 0 and Max Address None SUM (0000:01FFh) + SUM (0200:07FFh) + SUM (0800:0FFFh) + SUM (1000:17FFh) + SUM (1800:1FFFh) + (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 083h) + (CONFIG4L & 085h) + (CONFIG5L & 0Fh) + (CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) + (CONFIG7L & 0Fh) + (CONFIG7H & 040h) 0E412h 0E368h Boot Block SUM (0200:07FFh) + SUM (0800:0FFFh) + SUM (1000:17FFh) + SUM (1800:1FFFh) + (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 083h) + (CONFIG4L & 085h) + (CONFIG5L & 0Fh) + (CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) + (CONFIG7L & 0Fh) + (CONFIG7H & 040h) + SUM (IDs) 0E5E7h 0E59Ch Boot Block/ Block 0 SUM (0800:0FFFh) + SUM (1000:17FFh) + SUM (1800:1FFFh) + (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 083h) + (CONFIG4L & 085h) + (CONFIG5L & 0Fh) + (CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) + (CONFIG7L & 0Fh) + (CONFIG7H & 040h) + SUM (IDs) 0EBE6h 0EB9Bh PIC18F2320/ Boot Block/ PIC18F4320 Block 0/ Block 1 SUM (1000:17FFh) + SUM (1800:1FFFh) + (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 083h) + (CONFIG4L & 085h) + (CONFIG5L & 0Fh) + (CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) + (CONFIG7L & 0Fh) + (CONFIG7H & 040h) + SUM (IDs) 0F3E4h 0F399h Boot Block/ Block 0/ Block 1/ Block 2 SUM (1800:1FFFh) + (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 083h) + (CONFIG4L & 085h) + (CONFIG5L & 0Fh) + (CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) + (CONFIG7L & 0Fh) + (CONFIG7H & 040h) + SUM (IDs) 0FBE0h 0FB95h Boot Block/ Block 0/ Block 1/ Block 2/ Block 3 (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 083h) + (CONFIG4L & 085h) + (CONFIG5L & 0Fh) + (CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) + (CONFIG7L & 0Fh) + (CONFIG7H & 040h) + SUM (IDs) 03D8h 03E2h All (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 083h) + (CONFIG4L & 085h) + (CONFIG5L & 0Fh) + (CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) + (CONFIG7L & 0Fh) + (CONFIG7H & 040h) + SUM (IDs) 03D8h 03E2h Legend: Item CONFIG SUM[a:b] SUM (IDs) + & DS39592F-page 32 = = = = = Description Configuration Word Sum of locations, a to b inclusive Byte-wise sum of lower four bits of all ID locations Addition Bit-wise AND 2010 Microchip Technology Inc. PIC18FX220/X320 6.0 AC/DC CHARACTERISTICS TABLE 6-1: TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE Standard Operating Conditions Operating Temperature: 25C is recommended Param No. Sym Characteristic Min Max Units Conditions D110 VIHH High-Voltage Programming Voltage on MCLR/VPP 9.00 13.25 V D110A VIHL Low-Voltage Programming Voltage on MCLR/VPP 2.00 5.50 V D111 VDD Supply Voltage during Programming 2.00 5.50 V Externally timed; row erase and all writes 4.50 5.50 V Self-timed; all bulk erases -- 300 A D112 IPP Programming Current on MCLR/VPP D113 IDDP Supply Current during Programming -- 1 mA D031 VIL Input Low Voltage VSS 0.2 VSS V D041 VIH Input High Voltage 0.8 VDD VDD V D080 VOL Output Low Voltage -- 0.6 V IOL = 8.5 mA D090 VOH Output High Voltage VDD - 0.7 -- V IOH = -3.0 mA D012 CIO Capacitive Loading on I/O pin (PGD) -- 50 pF To meet AC specifications P2 Tsclk Serial Clock (Program Clock, PGC) Period 100 -- ns VDD = 5.0V 1 -- s VDD = 2.0V P2A TsclkL Serial Clock (Program Clock, PGC) Low Time 40 -- ns VDD = 5.0V 400 -- ns VDD = 2.0V P2B TsclkH Serial Clock (Program Clock, PGC) High Time 40 -- ns VDD = 5.0V 400 -- ns VDD = 2.0V P3 Tset1 Input Data Setup Time to Serial Clock 15 -- ns P4 Thld1 Input Data Hold Time from SCK 15 -- ns P5 Tdly1 Delay between 4-bit Command and Command Operand 20 -- ns P5A Tdly1a Delay between 4-bit Command Operand and Next 4-bit Command 20 -- ns P6 Tdly2 Delay between Last SCK of Command Byte to First SCK of Read of Data Word 20 -- ns P9 Tdly5 SCK High Time (minimum programming time) 1 -- ms P10 Tdly6 SCK Low Time after Programming (high-voltage discharge time) 5 -- s P11 Tdly7 Delay to allow Self-Timed Data Write or Bulk Erase to Occur 10 -- ms P12 Thld2 Input Data Hold Time from MCLR/VPP 2 -- s P13 Tset2 VDD Setup Time to MCLR/VPP 100 -- ns P14 Tvalid Data Out Valid from SCK 10 -- ns P15 Tset3 PGM Setup Time to MCLR/VPP 2 -- s 2010 Microchip Technology Inc. DS39592F-page 33 PIC18FX220/X320 NOTES: DS39592F-page 34 2010 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2010 Microchip Technology Inc. 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