1. General description
The 74HC257; 74HCT 257 are hig h- speed Si-g ate CMOS d evices and ar e pin co mpatible
with Low-power Schottky TTL (LSTTL).
The 74HC257 and 74 HCT257 have four identical 2-input multiplexers with 3-state outputs,
which select 4 bits of data from two sources and are controlled by a common data select
input (S).
The data input s from source 0 (1 I0 to 4I0) are selected when input S is LOW an d the dat a
inputs fr om source 1 (1I1 to 4I1) are selected when S is HIGH. Data appears at the
outputs (1Y to 4Y) in tr ue (non-inverting) form from the selected inputs.
The 74HC257 and 7 4HCT257 are the logic implemen tation of a 4-pole, 2-position switch,
where the position of the switch is determined by the logic levels applied to S. The output s
are forced to a high-impedance OFF-stat e when OE is HIGH.
The logic equations for the outputs are:
Except for their non-inverting (true) outputs the 74HC257; 74HCT257 are identical to the
74HC258.
2. Features
Non-inverting data path
3-state outp uts interface directly with system bus
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114E exceeds 2 000 V
MM JESD22-A115-A exceeds 20 0 V
Multiple package options
Specified from −40 °C to +85 °C and from −40 °C to +125 °C
74HC257; 74HCT257
Quad 2-input multiplexer; 3-state
Rev. 05 — 13 January 2010 Product data sheet
1Y OE 1I1 S•1I0•S•()•=
2Y OE 2I1 S•2I0•S•()•=
3Y OE 3I1 S•3I0•S•()•=
4Y OE 4I1 S•4I0•S•()•=
74HC_HCT257_5 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 05 — 13 January 2010 2 of 17
NXP Semiconductors 74HC257; 74HCT257
Quad 2-input multiplexer; 3-state
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC257N −40 °C to +125 °CDIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HCT257N
74HC257D −40 °C to +125 °CSO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74HCT257D
74HC257DB −40 °C to +125 °CSSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm SOT338-1
74HCT257DB
74HC257PW −40 °C to +125 °CTSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm SOT403-1
74HCT257PW
Fig 1. Logic symbol Fig 2. IEC logic symbol
mga835
S
OE
1Y
2Y
3Y
4Y
2
3
5
6
11
10
14
13
15
1
4
7
9
12
1I0
1I1
2I0
2I1
3I0
3I1
4I0
4I1
001aad467
15
1G1
1MUX
1
4
2
3
7
5
6
9
11
10
12
14
13
EN
74HC_HCT257_5 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 05 — 13 January 2010 3 of 17
NXP Semiconductors 74HC257; 74HCT257
Quad 2-input multiplexer; 3-state
Fig 3. Functional di ag ram
mgr28
0
S1
1I0
2
1Y
4
1I1
3
SELECTOR
3-STATE MULTIPLEXER OUTPUTS
2I0
5
2Y
7
2I1
6
3I0
11
3Y
9
3I1
10
4I0
14
4Y
12
4I1
13
OE
15
Fig 4. Logic diag ra m
001aad468
1Y
S
OE
1I0
1I1
2I0
2I1
3I0
3I1
4I0
4I1
2Y
3Y
4Y
74HC_HCT257_5 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 05 — 13 January 2010 4 of 17
NXP Semiconductors 74HC257; 74HCT257
Quad 2-input multiplexer; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
6. Functional description
6.1 Function t able
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
Fig 5. Pin configuration DIP16, SO16, SSOP16 and TSSOP16
74HC257
74HCT257
SVCC
1I0 OE
1I1 4I0
1Y 4I1
2I0 4Y
2I1 3I0
2Y 3I1
GND 3Y
001aad499
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
Table 2. Pin description
Symbol Pin Description
S 1 common data select input
1I0 to 4I0 2, 5, 11, 14 data input from source 0
1I1 to 4I1 3, 6, 10, 13 data input from source 1
1Y to 4Y 4, 7, 9, 12 3-state multiplexer output
GND 8 ground (0 V)
OE 15 3-state output enable input (active LOW)
VCC 16 supply voltage
Table 3. Function table[1]
Control Input Output
OE Snl0 nl1 nY
HXXXZ
L H X L L
L H X H H
LLLXL
L L H X H
74HC_HCT257_5 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 05 — 13 January 2010 5 of 17
NXP Semiconductors 74HC257; 74HCT257
Quad 2-input multiplexer; 3-state
7. Limiting values
[1] For DIP16 packages: above 70 °C, Ptot derates linearly with 12 mW/K.
[2] For SO16 packages: above 70 °C, Ptot derates linearly with 8 mW/K.
[3] For SSOP16 and TSSOP16 packages: above 60 °C, Ptot derates linearly with 5.5 mW/K.
8. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0.5 +7 V
IIK input clamping current VI < −0.5 V or
VI > VCC + 0.5 V -±20 mA
IOK output clamping current VO < −0.5 V or
VO > VCC + 0.5 V -±20 mA
IOoutput current VO = −0.5 V to VCC + 0.5 V - ±35 mA
ICC supply current -+70 mA
IGND ground current -−70 mA
Tstg storage temp erature −65 +150 °C
Ptot total power dissipation
DIP16 package [1] -750 mW
SO16 package [2] -500 mW
SSOP16 package [3] -500 mW
TSSOP16 package [3] -500 mW
Table 5. Recommended operating con ditions
Symbol Parameter Conditions Min Typ Max Unit
Type 74HC257
VCC supply voltage 2.0 5.0 6.0 V
VIinput voltage 0 - VCC V
VOoutput voltage 0 - VCC V
Δt/ΔVinput transition rise and
fall rates VCC = 2.0 V --625 ns
VCC = 4.5 V -1.67 139 ns
VCC = 6.0 V --83 ns
Tamb ambient temp erature −40 -+125 °C
Type 74HCT257
VCC supply voltage 4.5 5.0 5.5 V
VIinput voltage 0 - VCC V
VOoutput voltage 0 - VCC V
Δt/ΔVinput transition rise and
fall rates VCC = 4.5 V -1.67 139 ns
Tamb ambient temp erature −40 -+125 °C
74HC_HCT257_5 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 05 — 13 January 2010 6 of 17
NXP Semiconductors 74HC257; 74HCT257
Quad 2-input multiplexer; 3-state
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 °C−40 °C to
+85 °C−40 °C to
+125 °CUnit
Min Typ Max Min Max Min Max
74HC257
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 1.2 -1.5 -1.5 - V
VCC = 4.5 V 3.15 2.4 -3.15 -3.15 - V
VCC = 6.0 V 4.2 3.2 -4.2 -4.2 - V
VIL LOW-level
input voltage VCC = 2.0 V - 0.8 0.5 -0.5 -0.5 V
VCC = 4.5 V - 2.1 1.35 -1.35 -1.35 V
VCC = 6.0 V - 2.8 1.8 -1.8 -1.8 V
VOH HIGH-level
output voltage VI = VIH or VIL
IO = −20 μA; VCC = 2.0 V 1.9 2.0 -1.9 -1.9 - V
IO = −20 μA; VCC = 4.5 V 4.4 4.5 -4.4 -4.4 - V
IO = −20 μA; VCC = 6.0 V 5.9 6.0 -5.9 -5.9 - V
IO = −6.0 mA; VCC = 4.5 V 3.98 4.32 -3.84 -3.7 - V
IO = −7.8 mA; VCC = 6.0 V 5.48 5.81 -5.34 -5.2 - V
VOL LOW-level
output voltage VI = VIH or VIL
IO = 20 μA; VCC = 2.0 V - 0 0.1 -0.1 -0.1 V
IO = 20 μA; VCC = 4.5 V - 0 0.1 -0.1 -0.1 V
IO = 20 μA; VCC = 6.0 V - 0 0.1 -0.1 -0.1 V
IO = 6.0 mA; VCC = 4.5 V - 0.15 0.26 -0.33 -0.4 V
IO = 7.8 mA; VCC = 6.0 V - 0.16 0.26 -0.33 -0.4 V
IIinput leakage current VI = VCC or GND; VCC = 6.0 V - - ±0.1 -±1.0 ±1.0 ±1.0 μA
IOZ OFF-state
output current VI = VIH or VIL;
VO = VCC or GND;
VCC = 6.0 V
- - ±0.5 -±5.0 ±10.0 ±10.0 μA
ICC supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V - - 8.0 -80 160 160 μA
Ciinput capacitance -3.5 -pF
74HCT257
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 -2.0 -2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 -0.8 -0.8 V
VOH HIGH-level
output voltage VI = VIH or VIL; VCC = 4.5 V
IO = −20 μA4.4 4.5 -4.4 -4.4 - V
IO = −6 mA 3.98 4.32 -3.84 -3.7 - V
VOL LOW-level
output voltage VI = VIH or VIL; VCC = 4.5 V - 0.1 -0.1
IO = 20 μA - 0 0.1 -0.33 -0.4 V
IO = 6.0 mA -0.15 0.26 -±1.0 -±1.0 V
IIinput leakage current VI = VCC or GND; VCC = 5.5 V - - ±0.1 -±5.0 -±10 μA
74HC_HCT257_5 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 05 — 13 January 2010 7 of 17
NXP Semiconductors 74HC257; 74HCT257
Quad 2-input multiplexer; 3-state
10. Dynamic characteristics
IOZ OFF-state
output current VI = VIH or VIL; VCC = 5.5 V;
VO = VCC or GND per input
pin; other inputs at VCC or
GND; IO = 0 A
- - ±0.5 -80 -160 μA
ICC supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V - - 8.0 μA
ΔICC additional supply
current VI = VCC − 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V; IO = 0 A
per input pin; nI0, nI1 inputs -40 144 -180 -196 μA
per input pin; OE input -135 486 -608 -662 μA
per input pin; S input -70 252 -315 -343 μA
CIinput capacitance -3.5 -pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 °C−40 °C to
+85 °C−40 °C to
+125 °CUnit
Min Typ Max Min Max Min Max
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); For test circuit see Figure 8.
Symbol Parameter Conditions 25 °C −40 °C to
+85 °C−40 °C to
+125 °CUnit
Typ Max Max Max
74HC257
tpd propagation delay nl0 to nY or nl1 to nY;
see Figure 6 [1]
VCC = 2.0 V 36 110 140 165 ns
VCC = 4.5 V 13 22 28 33 ns
VCC = 5.0 V; CL = 15 pF 11 - - - ns
VCC = 6.0 V 10 19 24 28 ns
S to nY; see Figure 6
VCC = 2.0 V 47 150 190 225 ns
VCC = 4.5 V 17 30 38 45 ns
VCC = 5.0 V; CL = 15 pF 14 - - - ns
VCC = 6.0 V 14 26 33 38 ns
ten enable time OE to nY; see Figure 7 [2]
VCC = 2.0 V 33 150 190 225 ns
VCC = 4.5 V 12 30 38 45 ns
VCC = 6.0 V 10 26 33 38 ns
tdis disable time OE to nY; see Figure 7 [3]
VCC = 2.0 V 41 150 190 225 ns
VCC = 4.5 V 15 30 38 45 ns
VCC = 6.0 V 12 26 33 38 ns
74HC_HCT257_5 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 05 — 13 January 2010 8 of 17
NXP Semiconductors 74HC257; 74HCT257
Quad 2-input multiplexer; 3-state
[1] tpd is the same as tPHL, tPLH.
[2] ten is the same as tPZH, tPZL.
[3] tdis is the same as tPHZ, tPLZ.
[4] tt is the same as tTHL, tTLH.
[5] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
tttransition time see Figure 6 [4]
VCC = 2.0 V 14 60 75 90 ns
VCC = 4.5 V 512 15 18 ns
VCC = 6.0 V 410 13 15 ns
CPD power dissipation
capacitance per multiplexer;
VI = GND to VCC
[5] 45 -pF
74HCT257
tpd propagation delay nl0 to nY or nl1 to nY;
see Figure 6 [1]
VCC = 4.5 V 16 30 38 45 ns
VCC = 5.0 V; CL = 15 pF 13 - - ns
S to nY; see Figure 6
VCC = 4.5 V 20 35 44 53 ns
VCC = 5.0 V; CL = 15 pF 17 -ns
ten enable time OE to nY; V CC = 4.5 V;
see Figure 7 [2] 15 30 38 45 ns
tdis disable time OE to nY; V CC = 4.5 V;
see Figure 7 [3] 16 30 38 45 ns
tttransition time VCC = 4.5 V; see Figure 6 [4] 512 15 18 ns
CPD power dissipation
capacitance per multiplexer;
VI = GND to VCC
[5] 45 -pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); For test circuit see Figure 8.
Symbol Parameter Conditions 25 °C −40 °C to
+85 °C−40 °C to
+125 °CUnit
Typ Max Max Max
74HC_HCT257_5 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 05 — 13 January 2010 9 of 17
NXP Semiconductors 74HC257; 74HCT257
Quad 2-input multiplexer; 3-state
11. Waveforms
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Propagation delays input (S, nI0, nI1) to output (nY) and output (nY) transition times
001aad47
7
tPLH
tPHL
VM
VM
90 %
10 %
VMVM
output
nY
input
S, nI0, nI1
VI
GND
VOH
VOL
tTLH
tTHL
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. 3-state output enable and disable times
001aac47
9
tPLZ
tPHZ
outputs
disabled
outputs
enabled
90 %
10 %
outputs
enabled
OE input
VI
VCC
VOL
VOH
GND
GND
VM
tPZL
tPZH
VM
VM
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
trtf
90 %
10 %
Table 8. Measurement points
Type Input Output
VMVM
74HC257 0.5VCC 0.5VCC
74HCT257 1.3 V 1.3 V
74HC_HCT257_5 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 05 — 13 January 2010 10 of 17
NXP Semiconductors 74HC257; 74HCT257
Quad 2-input multiplexer; 3-state
Measurement points are given in Table 8 and test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistor.
Fig 8. Test circuit for switching times
VMVM
tW
tW
10 %
90 %
0 V
VI
VI
negative
pulse
positive
pulse
0 V
VMVM
90 %
10 %
tf
tr
tr
tf
001aad98
3
DUT
VCC VCC
VIVO
RT
RLS1
CL
open
G
Table 9. Test data
Type Input Load Switch position
VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ
74HC257 VCC 6 ns 50 pF 1 kΩopen GND VCC
74HCT257 3 V 6 ns 50 pF 1 kΩopen GND VCC
74HC_HCT257_5 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 05 — 13 January 2010 11 of 17
NXP Semiconductors 74HC257; 74HCT257
Quad 2-input multiplexer; 3-state
12. Package outline
Fig 9. Package outline SOT38-4 (DIP16)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT38-4 95-01-14
03-02-13
MH
c
(e )
1
ME
A
L
seating plane
A1
wM
b1
b2
e
D
A2
Z
16
1
9
8
E
pin 1 index
b
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
UNIT A
max. 12 b1(1) (1) (1)
b2cD E e M Z
H
L
mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
min. A
max. bmax.
w
ME
e1
1.73
1.30
0.53
0.38
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05 0.2542.54 7.62 8.25
7.80
10.0
8.3 0.764.2 0.51 3.2
inches 0.068
0.051
0.021
0.015
0.014
0.009
1.25
0.85
0.049
0.033
0.77
0.73
0.26
0.24
0.14
0.12 0.010.1 0.3 0.32
0.31
0.39
0.33 0.030.17 0.02 0.13
D
IP16: plastic dual in-line package; 16 leads (300 mil) SOT38
-4
74HC_HCT257_5 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 05 — 13 January 2010 12 of 17
NXP Semiconductors 74HC257; 74HCT257
Quad 2-input multiplexer; 3-state
Fig 10. Package outline SOT109-1 (SO16)
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
8
9
1
16
y
pin 1 index
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10
1.45
1.25 0.25 0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8 1.27 6.2
5.8
0.7
0.6
0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT109-1 99-12-27
03-02-19
076E07 MS-012
0.069 0.010
0.004
0.057
0.049 0.01 0.019
0.014
0.0100
0.0075
0.39
0.38
0.16
0.15 0.05
1.05
0.041
0.244
0.228
0.028
0.020
0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
0 2.5 5 mm
scale
S
O16: plastic small outline package; 16 leads; body width 3.9 mm SOT109
-1
74HC_HCT257_5 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 05 — 13 January 2010 13 of 17
NXP Semiconductors 74HC257; 74HCT257
Quad 2-input multiplexer; 3-state
Fig 11. Package outline SOT338-1 (SSOP16)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05
1.80
1.65 0.25 0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2 0.65 1.25
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
8
0
o
o
0.130.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT338-1 99-12-27
03-02-19
(1)
wM
bp
D
HE
E
Z
e
c
vMA
X
A
y
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
MO-150
pin 1 index
0 2.5 5 mm
scale
S
SOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338
-1
A
max.
2
74HC_HCT257_5 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 05 — 13 January 2010 14 of 17
NXP Semiconductors 74HC257; 74HCT257
Quad 2-input multiplexer; 3-state
Fig 12. Package outline SOT403-1 (TSSOP16)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3 0.65 6.6
6.2
0.4
0.3
0.40
0.06
8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403
-1
A
max.
1.1
pin 1 index
74HC_HCT257_5 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 05 — 13 January 2010 15 of 17
NXP Semiconductors 74HC257; 74HCT257
Quad 2-input multiplexer; 3-state
13. Revision history
Table 10. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT257_5 20100113 Product data sheet -74HC_HCT257_4
Modifications: •Table 7 “Dynamic characteristics”: ch anged 3OE to OE
74HC_HCT257_4 20090608 Product data sheet -74HC_HCT257_3
74HC_HCT257_3 20050920 Product data sheet -74HC_HCT257_CNV_2
74HC_HCT257_CNV_2 19980930 Product specification - -
74HC_HCT257_5 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 05 — 13 January 2010 16 of 17
NXP Semiconductors 74HC257; 74HCT257
Quad 2-input multiplexer; 3-state
14. Legal information
14.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warrant ies as to t he accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short dat a sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre va il.
14.3 Disclaimers
General — In formation in this document is believed to be accura te and
reliable. However, NXP Semiconductors d oes not give an y represent ations or
warranties, expressed or impli ed, as to the accuracy or completeness of such
information and shall have no liability for th e co nsequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for il lustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause pe rmanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other co nditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may af fect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to war ranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between inf ormation in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulatio ns. Export might require a prior
authorization from national authorities.
14.4 Trademarks
Notice: All refe renced brands, produc t names, service names and trademarks
are the property of their respective ow ners.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document cont ains the product specification.
NXP Semiconductors 74HC257; 74HCT257
Quad 2-input multiplexer; 3-state
© NXP B.V. 2010. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 13 January 2010
Document identifier: 74HC_HCT257_5
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
16. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 4
6.1 Function table. . . . . . . . . . . . . . . . . . . . . . . . . . 4
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Recommended operating conditions. . . . . . . . 5
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
13 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
14.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
14.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
14.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
14.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
15 Contact information. . . . . . . . . . . . . . . . . . . . . 16
16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
