HARRIS SEMICOND SECTOR Gl HARRIS CMOS Synchronous Programmable 4-Bit Counters High-Voltage Types (20-Volt Rating) CD40160B Decade with Asynchronous Clear CD40161B Binary with Asynchronous Clear CD40162B Decade with Synchronous Clear CD401638 Binary with Synchronous Clear @ COD40160B, C0401618, CD40162B, and CO40163B are 4-bit synchronous pro- grammable counters. The CLEAR function of the CD401628 and CD401638 is synchro- nous and a low level at the CLEAR input sets all four outputs low on the next positive CLOCK edge. The CLEAR function of the CD401608 and CD401618 is asynchronous and a low level at the CLEAR input sets all four outputs low regardless of the state of the CLOCK, LOAD, or ENABLE inputs. A low level at the LOAD input disables the counter and causes the output to agree with the setup data after the next CLOCK pulse regardless of the conditions of the ENABLE inputs. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. !nstru- mantal in accomplishing this function are two count-enable inputs and a carry output {Court}. Counting is enabled when both PE and TE inputs are high. The TE input is fed forward to enable Court. This enabled out- Put produces a positive output pulse with a MAXIMUM RATINGS, Absolute-Maximum Values: DC SUPPLY-VOLTAGE RANGE, pp) Voltages referenced to Vgg Terminal) ..........ec0ccee fede eee eaeeeneceneees -0.5V to +20V INPUT VOLTAGE RANGE, ALL INPUTS -0.5V to Vpp +0.5V OC INPUT CURRENT, ANY ONE INPUT ..............0.. Onde eee eneesene seeesenae TOMA POWER DISSIPATION PER PACKAGE (Pp): For Ta = ~559C to +1009C 00. eee ecseecenneeeeue ender emer eer eens cenanes s SOOMW For Ta = +100C to +1259C . Derate Linearity at 12mW/G to 200mW DEVICE DISSIPATION PER OUTPUT TRANSISTOR FOR Ta = FULL PACKAGE-TEMPERATURE RANGE {All Package Types)........ aeees T0OMW OPERATING-TEMPERATURE RANGE (TA) -eeeceee Se seeeeee te eeeweuee o0e-7850G to +12509C STORAGE TEMPERATURE RANGE (Tgtg) sos cecseccccseeeneenees veeee 65C to $1509 LEAD TEMPERATURE (DURING SOLDERING): . Atdistance 1/16 + 1/32 inch (1.59 + 0.79mm) from case for 108 max ......-... seeees #26506 TO*SOURGE VOLTAGE {YnsV YUE D MM 4302271 0037734 4 MBHAS 145-2 3-05 CD40160B, CD40161B, CD40162B, CD40163B Types Features: Internal look-ahead for fast counting Carry output for cascading Pe 4 Ht. oi Synchronously programmable Te 3 is Clear asynchronous input CLEAR 7 p42 (CD40160B, CD401618) toxs 2 2 3 Clear synchronous input shack as (CD401628, CD401638) 7 8 Synchronous load control input ee ~~; as Low-power TTL compatibility 6! IS caRRY Standardized, symmetrical output ~ [~~ our characteristics Van tie = 100% tested for quiescent current at 20 V Veet Maximum input current of 1 2A at 18 V over full package-temperature range; 100 nA at 18 V and 25C Noise margin (over full package-tempera- ature range): = 1 Vat Vpp =5 V 2V at Vop = 10 V 2.5 Vat Vop =15V a5&-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 13B, Standard Specitications for Description of B' Series CMOS Devices duration approximately equal to the positive Portion of the Q1 output. This positive overflow carry pulse can be used to enable Successive cascaded stages. Logic transitions at the PE or TE inputs may occur when the clock is either high or low, The C0401608, CD401618, CD401 62B, and CD40163B8 types are supplied in 16-lead hermetic dual-in-line ceramic packages (D and F suffixes), 16-lead dual-in-line plastic Packages (E suffix), and in chip form (H suffix). s2cS-2a6zant Functional Diagram Applications: " Programmable binary and decade counting = Counter contro!/timers Frequency dividing The CD40160B8 through CD401638 types are functionally equivalent to and pin-com- patible with the TTL counter series 74LS160 through 74LS163 respectively. DRAIN=TO: SOURCE VOLTAGE (Yo3)V atch-24s:a03 Fig. 1 Typical output low (sink) current characteristics, a2$-2esrsar Fig. 2 Minimum output low (sink) current characteristics. 3-415 COMMERCIAL CMOS HIGH VOLTAGE ICs,44E > Ml 4302271 0037735 & MMHAS - HARRIS SEMICOND SECTOR VS" 3-05 CD40160B, CD40161B, CD40162B, CD40163B Types ~~ coaciezs SYNCHRONOUS CLEAR e INPUTS PROTECTED BY COS/MOS PROTECTION NETWORK 92CL-29226R) Fig, 3~ Logic diagrams for CD40160B and CD40162B BCD decade counters. co4oi6IB ASYNCHRONOUS CLEAR Load * ciock* CLEAR * CO40I6368 SYNCHRONOUS CLEAR OD crocx CLEAR | | * INPUTS PROTECTED i BY COS/MOS PROTECTION NETWORK a at a2 92CL-2922S8At Yss Fig, 4 Logic diagrams for CD401618 and CD40163B binary counters. 3-416HARRIS SEMICOND SECTOR WHE D MM 43902271 00377356 & MRHAS T-YS-Q3 05: CD40160B, CD40161B, CD40162B, CD40163B Types RECOMMENDED OPERATING CONDITIONS at Ty = 25C, Except as Noted ORAIK=T0-SOURCE VOLTAGE {Vpg]V For maximum reliability, nominal operating conditions shauld be selected so that operation is always within the following ranges: CHARACTERISTIC Vpp LIMITS UNITS (v) MIN. MAX. Supply Voltage Range (Full Ta = Full Package- Temperature Range) -_ 3 18 Vv Setup Time: tsy 5 240 - Data to Clock 10 so - ns 15 60 - 5 240 - Load to Clock 10 90 - ns Nason 15 60 Fig. 5 Typical output high (source) 5 340 _ current characteristics, . PE or TE to Clock 10 140 - ns DRAIN-TO-SOURCE VOLTAGE (Vos)-V 15 100 - a Clear to Clock aa ~ ns i (C0401628, CD401638) 15 100 2 wee 5 0 - z E a All Hold Times, ty 10 0 - ns 3 mer 15 0 - gg Clear Removal Time, trem 1 on 7 3] 1S (CD401608, CD40161B) - ns . aa 15 70 - 2 ak = . 5 170 - 3} |G Clear Pulse Width, tw 10 70 _ ns . . w2G8-203202 =x (CD401608, CD401618) Fig. G~ Minimum output high (source) S g 15 50 = current characteristics, ot 5 - 2 Clock Input Frequency, fet 10 - 5.5 MHz AMBIENT TEMPERATURE (Ty }0 25C 15 - 8 5 170 - Clock Pulse Width, tw 10 70 - ns 15 50 - 5 - 200 Clock Rise or Fal! Time, teCL or teCL 10 - 70 us 16 - 18 toao capacitance sits-20571 Fig. 7 Typicat Propagation delay time as 4 TRUTH TABLE TOL Ce on oad capacitance CLOCK CLR LOAD PE TE OPERATION S/S 1 0 x xX | PRESET : 3 SJ 1 1 0 x NC JS 1 1 x | o | Ne 3 = JS, 1 1 1 1 COUNT g x 0 Xx X x RESET (CD401608, CD401618) 3 JS, 0 Xx xX X RESET (CD40162B, CD40163B) N 1 x x x NC (CD401628, CD40163B) LOAD CAPROITANCE TOI oe easenit Fig. 8 Typical transition time as a function 1 = HIGH LEVEL 0= LOW LEVEL X = DON'T CARE NC = NO CHANGE of load capacitance. ' 3-417HARRIS SEMICOND SECTOR WUE D MM 4302271 0037737 T MMHAS T-YS"Q3-0S5 CD401608B, CD40161B, CD40162B, CD40163B Types STATIC ELECTRICAL CHARACTERISTICS CHARAC CONDITIONS LIMITS AT INDICATED N . 6 TERISTIC TEMPERATURES (C) {t z Yo | Yin |Yoo +28 ST eet (v) (v) | (v)] -55 | -40 +85 {+125 | Min. | Typ. |Max. 2 . - 05| 5 5 5| 150] 1s0/ 004] 5 & a eat Or it 20% m= CLES EF Device - 0,10| 10 10} 10] 300) 300] 0.04] 10} 4a) |* Current, - 0,15} 15 | 201 20] 600) soo] 0.04] 20 lop Max. ~ 0,20] 20 | 100] 100] 3000] 3000] 0.08 | 100 * = 6 Output L 0.4 05| 5] 064] 061] 042] o36| 051 1| - MeO ANe ea-zaeer lutput Low Fig. 9- Typical aissipatic (Sink) Current] 0.5 | 0,10| 10| 16] 15{ 11) o9f +a! 26] FT funetion of CLOCK fugu, for Min. 15 fois] is! 42] 4] 2ef 24! gal eal ; Vpo Output Hign 48 0,5| 5 |-0.64|-0.61 | -0.42}-0.36 |-o51} -1| - Ima (Source) 2.5 o5{ S| -2] -1.8] -1.3)-1.15] -16f -3.27 parent, 9.5 | 0,10] 10 | -1.6/ -15] -1.1! -o9] -13l -26] on 35 [o18] 15 | -42| -4 | 28) c2a] caal coal c 2 (Output Voltage:| 05] 5 0.05 - 0 | 0.05 2 Low-Level, - 0,10} 10 0.05 - 0} 0.05 t Vor Max. ~ fo6 15 0.05 - 0] 0.08] y 8 Output = 05] 5 4.95 4.95 54] - - Voltage: _ - High-Level, 0.10} 10 9.95) 10 _ 9208-28972 Vou Min. ~ 0.18 | 18 14.95 14.95 i Fig. 10 Dynamic power dissipation test 054.5) | 5 1.5 | 15 circuit. Input Low - Voltage 1,9 -_ | 10 3 - - 3 vo Vir Max. fsias] | 15 4 - -| 4ty 4 ~ Yoo INPUTS Input High 0.54.5] 5 3.5 35, -|] - s Voltage, 1,9 ~ 410 7 7 -|[- . ss : VinMin. fea38] | 15 11 mn; -|- a Input Current 5 ly Max. - 0,18] 18 120.4 | +04 ] +t | 21 |+1075} 40.1] pA o $ ae S ees-27401Mt Fig. t1~ Quiescent-device-current test circuit. Yoo os : : Vy . ~ - meus | t , TERMINAL ASSIGNMENT & = weasure IMPUTS a perrers - pan fe) _ Yn CLEAR vss _ To eat Yoo 20 Soe = @ cee CONMECT ALL UNUSED ve - Le = INPUTS TO EITHER re } po OF Ysg- am = 8 Vg - q : . ~ an pe. , saca-enea . ss Wrure arin vss Fig. 12 Input-current tese circuit. WeCS-2 744i Fig. 13 Input-voltage test circuit. 3-418HARRIS SEMICOND SECTOR 4W4E D MM 4302271 0037738 1 EMHAS 7 95-23-08 CD40160B, CD40161B, CD40162B, CD40163B Types DYNAMIC ELECTRICAL CHARACTERISTICS at Ta=25C; - wo Input t,, ty = 20 ns, Cy = 50 pF, Ry = 200 kQ TEST LIMITS CHARACTERISTIC CONDITIONS | ALL TYPES* UNITS Vop (Vv) Min. ] Typ. | Max. CLOCK OPERATION Propagation Delay Time, tpHitpLH 5 7 200 400 . Clock to Q - 10 - 80 160 ns 18 - 60 120 5 - 225 450 Clock to Coyt 10 - 95 190 ns 15 ~ 70 140 5 _ -125 250 TE to Coury 10 - 55 110 ns 15 - 40 80 Minimum Setup Time, toy 5 ~ 120 240 Data to Clock 10 ~" | 45 90 ns 15 - 30 | 60 5 - 120 240 Load to Clock 10 - 45 90 ns 15 ~ | 30 | 60 5 - 170 340 PE to TE to Clock 10 - 70 | 140 ns 88 15 - 60 | 100 Su 5 [ =] 3 ae Minimum Hold Time, ty 10 - - 0 ns La 15 - ~ 0 y = 5 ~-] 100 | 200 se Transition Time, tTHLTLH 10 - 50 100 as oF 15 - 40 | 80 5 - 85 170 Minimum Clock Pulse Width, tw 10 - 35 70 ns 15 - 25 50 5 2 3 = Maximum Clock Frequency, fot 10 5.5 8.6 - MHz 15 _8 12 - 5 200 ~ - Maximum Clock Rise or Fall Time,t 10 70 ~ - Hs tCL, trot, 15 15 ~ - CLEAR OPERATION Propagation Delay Time, tpHL 5 - 250 500 (CD40160B, CD401618) 10 - 110 | 220 ns Clear to Q 15 - 80 160 Minimum Setup Time, ts; Bo - 170 340 (CD401628, CD401638) 10 -. 70 140 ns Clear to Clock ; 16 - 50 100 Minimum Hold Time, ty 5 _ - 0 (CD40162B, CD40163B) 10 - - 0 ns Clear to Clock 15 - - 0 : Minimum Clear Removal Time, trem 1. a m 700 ns (CO401608, CD40161B) 16 - _ 35 |. 70 Minimum Clear Pulse Width, ty, 1 : - a 0 (CD401608, CD40161B) 16 _ 25 | 50 ns * Except as noted. : t If more than one unit is cascaded in the Parallel clocked application, t,CL should be made tess than or equal to the sum of the fixed propagation delay at 50 pF and the transition time of the carry output driving stage for the estimated capacitive load. 3-419HARRIS SEMNICOND SECTOR QUE D MM 4302271 0037739 3 MBHAS sly ~ . ~ e CD40160B, CD40161B, CD40162B, CD40163B Types 3-23-08 CLERIC! l j ASYNCHRONOUS ZCEaR I CLEARICO405628} Ly feesenrances Load 1 I t DATA INPUTS e2 I P3 a j L L \ Pa 4 stperssoe 7 LLL PLL LPL omens" LULL Lar [oa 1 I B | i | i! __ a4 + + Pott | GARRY OUT Fol ls s o a 2 si I! bk ue | cOUNT 1aHigiT CLEAR PRESET 92CL-29228R1 Fig. 14 Timing diagram for CD401608, CD401628, CCEAR (c0401616}-]_ ASYNCHRONOUS l CLEAR (C0401639 } | [evacHAoNous Load l T 1 i Pr + t DATA P2 T INPUTS a 1 L pal I l i sseexieos08@) LLL 1 ! rot crocetcosor3a) _ 7] PLLA LP LPS LY LPL ry TL 1 CARRY OUT 9 te ts it3s 9 oT i ak CLEAR PRESET count mesrr e2cL-292258t Fig. 1 Timing diagram for CD401618, CO401638B. 3-420HARRIS SEMICOND SECTOR CD40160B, CD40161B, CD40162B, CD40163B Types - Q 2 a TH LE > 1 > GL- ch cu YUE D MM 4302271 0037740 T MAAS T4S-QX3OS a : E - 8a 2.235) on 92cu-29226 Fig. 16 Detail of flip-flops of CD40160B and CD40161B fasynchronaus clear}. o 4-10 | (0.102-0.254} 108-114 - 12.693-2.895) > ow e2ch~29968 Dimensions and pad layout for CD40160BH. Dimensions and pad layout ce for CD40161BH,CD401628H, and CD40163BH are identical. Do a Dimensions in parentheses are in millimeters and 2 Ss a are derived from the basic inch dimensions as in- oO wl dicated. Grid graduations are in mils (10-3 inch), - g . R 35 cL ch a , aS 2x a =o fn 8 = rae ce cf o on . , A a ce uw >On 92M-29227 Fig. 17 Oetail of flip-flops for CD401628 and CD40163B {synchronous clear}. Toso Yoo PL P2 P3 PS PL P2 3 Pe PL P2 P3 P4 Pe 10 Fe TO ee tb TE co t] Te e TE co} cLx CLR CLK CLR CuK TLR Qt 02 a3 a4 OF 02.03 a4 4 bh a4 cLock pe ctEaR a2cw-29989 Fig. 18 ~ C ges in the parallel-clocked made. LOAD Yoo Yan Yoo Titi itt? Ltt re TO re TD PE TO Te co Te co Te coh [cLK CUR CLK CLA eux COR clock @1 a2 03 a4 a a2 93 a4 Qt 02 3 04 cCEAR 92M-29970 : Fig, 19 Cascaded counter packages in the ripple-clocked made. 3-421