MC13109A
UNIVERSAL CT–0
SUBSYSTEM
INTEGRATED CIRCUIT
FB SUFFIX
PLASTIC PACKAGE
CASE 848B
(QFP–52)
52 1
Device Tested Operating
Temperature Range Package
ORDERING INFORMATION
MC13109AFB TA = –20 to 85°CQFP–52
MC13109AFTA LQFP–48
FTA SUFFIX
PLASTIC PACKAGE
CASE 932
(LQFP–48)
48 1
Order this document by MC13109A/D
1
MOTOROLA RF/IF DEVICE DATA
Universal Cordless Telephone
Subsystem IC
The MC13109A integrates several of the functions required for a cordless
telephone into a single integrated circuit. This significantly reduces
component count, board space requirements, and external adjustments. It is
designed for use in both the handset and the base.
•Dual Conversion FM Receiver
– Complete Dual Conversion Receiver – Antenna Input to Audio Output
80 MHz Maximum Carrier Frequency
– RSSI Output
– Carrier Detect Output with Programmable Threshold
– Comparator for Data Recovery
– Operates with Either a Quad Coil or Ceramic Discriminator
•Compander
– Expandor Includes Mute, Digital Volume Control and Speaker Driver
– Compressor Includes Mute, ALC and Limiter
•Dual Universal Programmable PLL
– Supports New 25 Channel U.S. Standard with No External Switches
– Universal Design for Domestic and Foreign CT–0 Standards
– Digitally Controlled Via a Serial Interface Port
– Receive Side Includes 1st LO VCO, Phase Detector, and 14–Bit
Programmable Counter and 2nd LO with 12–Bit Counter
– Transmit Section Contains Phase Detector and 14–Bit Counter
– MPU Clock Output Eliminates Need for MPU Crystal
•Supply Voltage Monitor
– Externally Adjustable Trip Point
•2.0 to 5.5 V Operation with One–Third the Power Consumption of
Competing Devices
Mute
Expander
Simplified Block Diagram
1st
Mixer
Data
Out
Rx In 2nd
Mixer
Carrier
Detect
Tx Out
Tx In
Tx VCO
Limiting IF
Amplifier Detector
2nd LO
PLL
1st LO
PLL RSSI
Mute
Compressor
Tx Phase
Detector
µP Serial
Interface
Low Battery
Detect
Rx
Out
SPI
Low
Battery
Indicator
This device contains 6,609 active transistors.
Motorola, Inc. 1999 Rev 1
MC13109A
2MOTOROLA RF/IF DEVICE DATA
Figure 1. MC13109AFB Test Circuit
C1
9–35pF
C2
4.3pF
XL1
10.24
MHz
C44 10µF
C4
0.01µF
C3 0.047µF
R33
3.0k
R34
1.5k C45
0.1µF
R35
32.4k
C46
0.0047
µF
R36
22.1k
C43 0.1µF
R31
100k
R32
100k
VCC/2
Ext_Ref
VCCE
Rx_Audio
Open
C42
5.0nF
R29
49.9k R30
49.9k
C40
1.0µF
VCCA
C30
1.0µF
Ext_C_In
R27
49.9k
C38
5.0nF
R28
49.9k
C47
1.0µF
Tx_In
L1
Mix1_In
C36
0.01µF
C35 0.01µF
Open
In
Out
1
2
3
C34
1.0µF
In
Out
1
2
3
Gnd
CF2
Ext_IF
455k
In
R23
10.2
R24
10 R23
1.5k
C33 0.1µF
C32 0.1µF
C31 0.1µF
C30
0.1µFC29
10µF
VCC
L2
R22
12k
C28
0.1µF
C27 0.1µF
R21 8.2k
C26
0.01µF
Det_Out
Audio_In_In
R20
49.9k
C25
1.0µF
C24
510pF R19
49.9k
Pre_Amp
R18
20k
R17
5.62k
C22
0.1µF
C21
0.033µF
C23
0.001µF
DA_Fil
DA_In
VCCA
C19
10µFC20
0.1µF
E_Out
Exp_IF Ext_SA_In
C18
1.0µF
R16
49.9k
C16
510
pF
R14
130
SA_Out
R13
3.9k
VCCD
VCC R12
100k
C15
10pF
U1
DA
DB
VCC LS09
Out
Gnd
U1
DA
DB
VCC
LS09
Out
Gnd
U1
DA
DB
VCC
LS09
Out
Gnd
U1
DA
DB
VCC LS09
Out
Gnd
Clk_5.0V
Open
VCCE
R11 1.0k
Clk_5.0V
EN_5.0V
R10 1.0k
R9
1.0k
EN_5.0V
Open
Open
Data_5.0V
5.0V
1
2
14
3
7
6
7
4
5
14
8
7
10
9
14
13
12
14
11
7
MPS5179
Q1
R6
1.0k C12 33pF
C11 47pF
C10
68pF R7
22.1k
R5 22.1k
C9
33pF
L3 0.22µH
C8 18pF
C7
15pF
1N5140
C6 0.022µFR4
100k
R2
32.4k
C5
0.1µF
R3
32.4k
R1
1.5k
C48
1.0µF
VCCA
C14
1.0µF
R8
100k
Tx_VCO
Ext
50
C17
47µF
LO2
In
LO2
Out
PLL
Vref
Rx
PD
Gnd
PLL
Tx
PD
Ecap
Tx
VCO
Data
EN
Clk
Clk
Out
CD
Out/
Hardware
Interrupt
BD
Out DA
Out SA
Out SA
In E
Out VCC
Audio DA
In Pre–
Amp
Out
Rx
Audio
In
Det
Out RSSI
Q Coil
VCC RF
Lim C2
Lim C1
Lim In
Gnd RF
Mix2 Out
Mix2 In
VB
Mix1 Out
Mix1 In2
Mix1
In1
LO1
In
LO1
Out
Vcap
Ctrl
Gnd
Audio
Tx
In
Amp
Out
C In
C
Cap
Lim
Out
Spl
Amp
In
Tx
Out
Ref
N/A
N/A
Status
Out
N/A
52 51 50 49 48 47 46 45 44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
28
27
14 15 16 17 18 19 20 21 22 23 24 25 26
VB
PLL Vref
Low
Battery
Detect
VBSpkr
Mute
Carrier
Detect RSSI
1st LO
2nd Mix
ALC
13
12
11
10
9
8
7
6
5
4
3
2
1
TOKO
A7MES–12597Z
VCC
330
VB
Ref
Spkr
Amp Vol
Ctrl
Expander
E
Cap Data
Amp
VB
Pre–
Amp
2nd LO
1st
Mix
Compressor
Limiter
2nd
LO Spl
Amp
Tx
Mute
Half Supply
Reference
2nd LO
10.240
R Phase
Detect
x
T Phase
Detect
x
14b Prog
R Ctr
x
1st LO
14b Prog
T Ctr
x
P Serial
Interface
µ
Prog
Clk Ctr
2.2V
Voltage
Regulator
Bandgap
Reference
Detector IF Amp/
Limiter
1st LO
VCO
+–
+–
+–+–
R15
49.9k
C13
0.01
µF
Rx
Mute
C41
0.47
µF
MIC_
Amp
Out
Open LO1
12b Prog
Ref Ctr
÷1÷4÷25
CF1 10.7 MHz
CF2 455 MHz
Data_5.0 V
MC13109A
3
MOTOROLA RF/IF DEVICE DATA
Figure 2. MC13109AFTA Test Circuit
C9
33pF
C1
9–35pF
C2
4.3pF
XL1
10.24
MHz
C44 10µF
C4 0.01µF
C3 0.047µF
R33
3.0k
R34
1.5k
C45
0.1µF
R35
32.4k
C46
0.0047
µF
R36
22.1k
C43
0.1µF
R31
100k
R32
100k VCC/2 Ext_Ref
VCCE
Rx_Audio
Open
C42
5.0nF
R29
49.9k
R30
49.9k C40
1.0µF
VCCA
C30
1.0µF
MIC_
Amp
Out
R27
49.9k
C38
5.0nF
R28
49.9k
C47
1.0µF
Tx_In
Open LO1
L1
Mix1_In
C35 0.01µF
Open
In
Out
1
2
3
C34
1.0µF
In
Out
1
2
3
Gnd
CF2
Ext_IF 455k
In
R23
10.2
R24
10
R23
1.5k
C33
0.1µF
C32 0.1µF
C31 0.1µF
C30
0.1µFC29
10µFVCC
L2
R22
12k
C28
0.1µF
C27
0.1µF
R21
8.2k
Det_Out
Audio_In_In
R20
49.9k
C25
1.0µF
C24
510pF
R19
49.9k
Pre_Amp
R18
20k
R17
5.62k
C22
0.1µF
C21
0.033µFC23
0.001µF
DA_Fil
DA_In
VCCA
E_Out
Exp_IF Ext_SA_In
C18
1.0µF
R16
49.9k
C16
510pF
R14
130
SA_Out
R13
3.9k
VCCD
VCC
R12
100k
C15
10pF
U1
DA
DB
VCC
LS09
Out
Gnd
U1
DA
DB
VCC
LS09
Out
Gnd
U1
DA
DB
VCC
LS09
Out
Gnd
U1
DA
DB
VCCLS09
Out
Gnd
Open
VCCE
R11
1.0k
Clk_5.0V
EN_5.0V
R9
1.0k
EN_5.0V
Open
Data_5.0V
5.0V
1
2
14
3
7
6
7
4
5
14
8
7
10
9
14
13
12
14
11
7
MPS5179
Q1
R6
1.0k
C12
33pF
C11 47pF C10
68pF
R7
22.1k
R5
22.1k
L3 0.22µH
C8 18pF
C7
15pF
1N5140
C6 0.022µFR4
100k
R2
32.4k
C5
0.1µF
R3
32.4k
R1
1.5k
C48
1.0µF
VCCA
Tx_VCO
Ext
50
C17
47µF
LO2
In
LO2
Out
PLL
Vref
Rx
PD
Gnd
PLL
Tx
PD
E Cap
Tx
VCO
Data
EN
Clk
Clk
Out
CD Out/
Hardware
Interrupt
BD
Out DA
Out SA
Out SA In E
Out VCC
Audio DA
In Pre–
Amp
Out
Rx
Audio
In
Det
Out RSSI
Q Coil
VCC RF
Lim C2
Lim C1
Lim In
Gnd RF
Mix2 Out
Mix2 In
VB
Mix1 Out
Mix1 In2
Mix1 In1
LO1
In
LO1
Out
Vcap
Ctrl
Gnd
Audio
Tx
In
Amp
Out
C In
C
Cap
Lim
Out
Spl
Amp
In
Tx
Out
Ref
12b Prog
Ref Ctr
VB
PLL Vref
Low
Battery
Detect
VBSpkr
Mute
Carrier
Detect RSSI
1st LO
2nd Mix
VB
ALC
48 47 46 45 44 43 42 41 40 38 37
34
33
32
31
30
29
28
27
26
25
242322212019181716151413
12
11
10
9
8
7
6
5
4
3
2
1
VCC
TOKO
A7MES–12597Z
VCC
330
39
35
36
C13
0.01
µF
C14
1.0
µF
R8
100k
R10
1.0k
R15
49.9k
C19
10µFC20
0.1µF
C26
0.01µF
C36 0.01µF
C41
0.47
µF
Spl
Amp
Tx
Mute
Limiter
Compressor
Half
Supply
Reference2nd LO
1st
Mix
Pre–
Amp
Rx
Mute
Data
Amp
VB
Vol
Ctrl
Spkr
Amp
Ref
2nd
LO
1st LO
Expander
E
Cap
Detector
Bandgap
2.2V
14b Prog
P Serial
Prog T Phase 2nd LO
+–
1st LO
IF Amp/
+–
+–
+–
Clk Ctr
Interface T Ctr
µ
x
Voltage
Regulator
Reference
14b Prog
R Ctr
x
Detect
xR Phase
Detect
x10.240
Limiter
VCO
÷1÷4÷25
Open
Data_
5.0 V
Clk_5.0 V
Ext_C_In
CF1 10.7 MHzCF2 455 MHz
MC13109A
4MOTOROLA RF/IF DEVICE DATA
MAXIMUM RATINGS
Rating Symbol Value Unit
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Power Supply Voltage
ÁÁÁÁ
ÁÁÁÁ
VCC
ÁÁÁÁÁ
ÁÁÁÁÁ
–0.5 to +5.5
ÁÁÁ
ÁÁÁ
Vdc
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Junction Temperature
ÁÁÁÁ
ÁÁÁÁ
TJ
ÁÁÁÁÁ
ÁÁÁÁÁ
–65 to +150
ÁÁÁ
ÁÁÁ
°C
NOTES: 1.Devices should not be operated at or outside these limits. The “Recommended Operating
Conditions” table provides for actual device operation.
2.ESD data available upon request.
3.Meets Human Body Model (HBM) ≤2000V and Machine Model (MM) ≤200V.
RECOMMENDED OPERATING CONDITIONS
Characteristic Min Typ Max Unit
VCC 2.0 – 5.5 Vdc
Operating Ambient Temperature –20 – 85 °C
NOTE: All limits are not necessarily functional concurrently.
ELECTRICAL CHARACTERISTICS (VCC = 2.6 V, TA = 25°C, RF In = 46.61 MHz,
fDEV = ±3.0 kHz, fmod = 1.0 kHz; Test Circuit Figure 1.)
Characteristic Min Typ Max Unit
POWER SUPPLY
Static Current
Active Mode (VCC = 2.6 V) – 6.1 12 mA
Active Mode (VCC = 3.6 V) – 6.5 – mA
Receive Mode (VCC = 2.6 V) – 3.9 7.0 mA
Receive Mode (VCC = 3.6 V) – 4.3 – mA
Standby Mode (VCC = 2.6 V) – 320 600 µA
Standby Mode (VCC = 3.6 V) – 550 – µA
Inactive Mode (VCC = 2.6 V) – 40 80 µA
Inactive Mode (VCC = 3.6 V) – 54 – µA
MC13109A
5
MOTOROLA RF/IF DEVICE DATA
ELECTRICAL CHARACTERISTICS (continued)
FM Receiver
The FM receivers can be used with either a quad coil or a
ceramic resonator. The FM receiver and 1st LO have been
designed to work for all country channels, including 25
channel U.S., without the need for any external switching
circuitry (see Figure 25.)
(Test Conditions: VCC = 2.6 V, TA = 25°C, fO = 46.61 MHz, fDEV = ±3.0 kHz, fmod = 1.0 kHz.)
Characteristic Condition Input
Pin Measure
Pin Symbol Min Typ Max Unit
Sensitivity (Input for
12 dB SINAD) Matched Impedance
Differential Input Mix1
In1/2 Det Out VSIN – 0.7 – µVrms
1st Mixer Voltage
Conversion Gain Vin = 1.0 mVrms, with
CF1 as Load Mix1
In1/2 Mix1 Out MXgain1 – 10 – dB
2nd Mixer Voltage
Conversion Gain Vin = 3.0 mVrms, with
CF2 as Load Mix2 In Mix2 Out MXgain2 – 20 – dB
1st Mixer Input
Impedance – – Mix1 In1
Mix1 In2RP1
CP1 – 0.88
2.5 – kΩ
pF
2nd Mixer Input
Impedance – – Mix2 In RP2
CP2 – 3.0
2.7 – kΩ
pF
1st Mixer Output
Impedance – – Mix1 Out RP1 Out
CP1 Out – 390
1.8 –Ω
pF
2nd Mixer Output
Impedance – – Mix2 Out RP2 Out
CP2 Out – 1.5
12 – kΩ
pF
1st and 2nd Mixer
Voltage Gain Total Vin = 1.0 mVrms, with
CF1 and CF2 as Load Mix1
In1/2 Mix2 Out MXgainT 24 27 – dB
IF –3.0 dB Limiting
Sensitivity fin = 455 kHz Lim In Det Out IF Sens – 55 100 µVrms
Total Harmonic Distortion
(CCITT Filter) With RC = 8.2 kΩ/
0.01 µF Filter at Det
Out
Mix1
In1/2 Det Out THD – 1.0 3.0 %
Recovered Audio With RC = 8.2 kΩ/
0.01 µF Filter at Det
Out
Mix1
In1/2 Det Out AFO 80 100 154 mV rms
Demodulator Bandwidth –Lim In Det Out BW – 20 – kHz
Signal to Noise Ratio Vin = 10 mV rms,
RC = 8.2 kΩ/0.01 µFMix1
In1/2 Det Out SN – 50 – dB
AM Rejection Ratio 30% AM, Vin =
10 mV rms,
RC = 8.2 kΩ/0.001 µF
Mix1
In1/2 Det Out AMR 30 40 – dB
First Mixer 3rd Order
Intercept (Input
Referred)
Matched Impedance
Input Mix1
In1/2 Mix1 Out TOImix1 – –10 – dBm
Second Mixer 3rd Order
Intercept (Input
Referred)
Matched Impedance
Input Mix2 In Mix2 Out TOImix2 ––27 – dBm
Detector Output
Impedance – – Det Out ZO– 870 – Ω
MC13109A
6MOTOROLA RF/IF DEVICE DATA
ELECTRICAL CHARACTERISTICS (continued)
RSSI/Carrier Detect
Connect 0.01 µF to Gnd from “RSSI” output pin to form the
carrier detect filter. “CD Out” is an open collector output
which requires an external 100 kΩ pull–up resistor to VCC.
The carrier detect threshold is programmable through the
MPU interface.
(RL = 100 kΩ, VCC = 2.6 V, TA = 25°C.)
Characteristic Condition Input
Pin Measure
Pin Symbol Min Typ Max Unit
RSSI Output Current
Dynamic Range – Mix1 In RSSI RSSI – 65 – dB
Carrier Sense Threshold CD Threshold Adjust =
(10100) Mix1 In CD Out VT–11 – mVrms
Hysteresis – Mix1 In CD Out Hys – 1.5 – dB
Output High Voltage Vin = 0 µV rms, RL = 100
kΩ, CD = (10100) Mix1 In CD Out VOH – 2.6 – V
Output Low Voltage Vin = 100 µVrms, RL =
100 kΩ, CD = (10100) Mix1 In CD Out VOL – 0.01 0.4 V
Carrier Sense Threshold
Adjustment Range Programmable through
MPU Interface – – VTrange –20 –11 dB
Carrier Sense Threshold
– Number of Steps Programmable through
MPU Interface – – VTn – 32 – –
Data Amp Comparator
Inverting hysteresis comparator. Open collector output
with internal 100 kΩ pull–up resistor. A band pass filter is
connected between the “Det Out” pin and the “DA In” pin with
component values as shown in the attached block diagram.
The “DA In” input signal is ac coupled.
(VCC = 2.6 V, TA = 25°C)
Characteristic Condition Input
Pin Measure
Pin Symbol Min Typ Max Unit
Hysteresis – DA In DA Out Hys 30 40 50 mV
Threshold Voltage –DA In DA Out VTVCC – 0.9 VCC – 0.7 VCC – 0.5 V
Input Impedance – – DA In ZI– 12 – kΩ
Output Impedance – – DA Out ZO– 104 – kΩ
Output High Voltage Vin = VCC – 1.0 V,
IOH = 0 mA DA In DA Out VOH VCC – 0.1 2.6 – V
Output Low Voltage Vin = VCC – 0.4 V,
IOL = 0 mA DA In DA Out VOL – 0.04 0.4 V
MC13109A
7
MOTOROLA RF/IF DEVICE DATA
ELECTRICAL CHARACTERISTICS (continued)
Pre–Amplifier/Expander/Rx Mute/Volume Control
The Pre–Amplifier is an inverting rail–to–rail output swing
operational amplifier with the non–inverting input terminal
connected to the internal VB half supply reference. External
resistors and capacitors can be connected to set the gain and
frequency response. The expander analog ground is set to
the half supply reference so the input and output swing
capability will increase as the supply voltage increases. The
volume control can be adjusted through the MPU interface.
The “Rx Audio In” input signal is ac coupled.
(Test Conditions: VCC = 2.6 V, TA = 25°C, fin = 1.0 kHz, Set External Pre–Amplifier R’s for Gain of 1, Volume Control = (0111).)
Characteristic Condition Input
Pin Measure
Pin Symbol Min Typ Max Unit
Pre–Amp Open Loop
Gain – Rx
Audio In Pre–Amp AVOL – 60 – dB
Pre–Amp Gain
Bandwidth – Rx
Audio In Pre–Amp GBW – 100 – kHz
Pre–Amp Maximum
Output Swing RL = 10 kΩRx
Audio In Pre–Amp VOmax – VCC – 0.3 – Vpp
Expander 0 dB Gain
Level Vin = –10 dBV Rx
Audio In E Out G –3.0 –0.3 3.0 dB
Expander Gain
Tracking Vin = –20 dBV, Output
Relative to G Rx
Audio In E Out Gt–21 –19.84 –19 dB
Vin = –30 dBV, Output
Relative to G –42 –40.12 –37
Total Harmonic
Distortion Vin = –10 dBV Rx
Audio In E Out THD – 0.2 – %
Maximum Output
Voltage Increase input voltage
until output voltage
THD = 5%, then
measure output
voltage. RL = 10 kΩ
Rx
Audio In E Out VOmax – –5.0 – dBV
Attack T ime Ecap = 1.0 µF,
Rfilt = 20 kΩ
(See Appendix B)
Rx
Audio In E Out ta– 3.0 – ms
Release T ime Ecap = 1.0 µF,
Rfilt = 20 kΩ
(See Appendix B)
Rx
Audio In E Out tr– 13.5 – ms
Compressor to
Expander Crosstalk V (Rx Audio In)
= 0 V rms,
Vin = –10 dBV
C In E Out CT– –76 – dB
Rx Mute Vin = –10 dBV
No popping detectable
during Rx Mute
transitions
Rx
Audio In E Out Me– –65 – dB
Volume Control Range Programmable through
MPU Interface – – VCrange –14 – 16 dB
Volume Control Steps Programmable through
MPU Interface – – VCn – 16 – –
MC13109A
8MOTOROLA RF/IF DEVICE DATA
ELECTRICAL CHARACTERISTICS (continued)
Speaker Amplifier/SP Mute
The Speaker Amplifier is an inverting rail–to–rail
operational amplifier. The non–inverting input terminal is
connected to the internal VB half supply reference. External
resistors and capacitors are used to set the gain and
frequency response. The “SA In” input is ac coupled.
(Test Conditions: VCC = 2.6 V, TA = 25°C, fin = 1.0 kHz, External Resistors Set for Gain of 1.)
Characteristic Condition Input
Pin Measure
Pin Symbol Min Typ Max Unit
Maximum Output Swing VCC = 2.3 V,
RL = 1 30 ΩSA In SA Out VOmax – 0.8 – Vpp
L
VCC = 2.3 V,
RL = 6 00 Ω
V34V
– 2.0
30
–
VCC = 3.4 V,
RL = 6 00 Ω– 3.0 –
SP Mute Vin = –20 dBV
RL = 130 Ω
No popping detectable
during SP Mute
transitions
SA In SA Out Msp – –67 – dB
Mic Amplifier
The Mic Amplifier is an inverting rail–to–rail output
operational amplifier with the non–inverting input terminal
connected to the internal VB half supply reference. External
resistors and capacitors are connected to set the gain and
frequency response. The “Tx In” input is ac coupled.
(Test Conditions: VCC = 2.6 V, TA = 25°C, fin = 1.0 kHz, External Resistors Set for Gain of 1.)
Characteristic Condition Input
Pin Measure
Pin Symbol Min Typ Max Unit
Open Loop Gain –Tx In Amp Out AVOL – 60 – dB
Gain Bandwidth –Tx In Amp Out GBW – 100 – kHz
Maximum Output Swing RL = 10 kΩTx In Amp Out VOmax – VCC – 0.3 – Vpp
MC13109A
9
MOTOROLA RF/IF DEVICE DATA
ELECTRICAL CHARACTERISTICS (continued)
Compressor/ALC/Tx Mute/Limiter
The compressor analog gound is set to the half supply
reference so the input and output swing capability will
increase as the supply voltage increases. The “C In” input is
ac coupled. The ALC (Automatic Level Control) provides a
soft limit to the output signal swing as the input voltage
increases slowly (i.e., a sine wave is maintained). The Limiter
circuit limits rapidly changing signal levels by clipping the
signal peaks. The ALC and/or Limiter can be disabled
through the MPU serial interface.
(Test Conditions: VCC = 2.6 V, fin = 1.0 kHz, TA = 25°C.)
Characteristic Condition Input
Pin Measure
Pin Symbol Min Typ Max Unit
Compressor 0 dB Gain
Level Vin = –10 dBV, ALC
disabled, Limiter
disabled
C In Lim Out G –3.0 –0.06 3.0 dB
Compressor Gain
Tracking Vin = –30 dBV, Output
Relative to G C In Lim Out Gt–11 –10.12 –9.0 dB
Vin = –50 dBV, Output
Relative to G –23 –20.16 –17
Maximum Compressor
Gain Vin –70 dBV C In Lim Out AVmax – 29 – dB
Total Harmonic
Distortion Vin –10 dBV, ALC
disabled, Limiter
disabled
C In Lim Out THD – 0.5 – %
Input Impedance –C In Lim Out Zin – 16 – kΩ
Attack T ime Ccap = 1.0 µF,
Rfilt = 20 kΩ
(see Appendix B)
C In Lim Out ta– 3.0 – ms
Release T ime Ccap = 1.0 µF,
Rfilt = 20 kΩ
(see Appendix B)
C In Lim Out tr– 13.5 – ms
Expander to
Compressor Crosstalk V (C In) = 0 V rms,
Vin = –10 dBV Rx
Audio In Lim Out CT– –43.6 – dB
Tx Data Mute Vin = –10 dBV, ALC
disabled
No popping detectable
during Rx Mute
transitions
C In Lim Out Me– –76 – dB
ALC Dynamic Range –C In Lim Out DR ––18 to 2.5 – dBV
ALC Output Level Vin = –18 dBV C In Lim Out ALCout – –16 – dBV
Vin = –2.5 dBV – –11.4 –
Limiter Output Level ALC disabled C In Tx Out Vlim – 0.8 – Vpp
MC13109A
10 MOTOROLA RF/IF DEVICE DATA
ELECTRICAL CHARACTERISTICS (continued)
Splatter Amplifier
The Splatter Amplifier is an inverting rail–to–rail output
operational amplifier with the non–inverting input terminal
connected to the internal VB half supply reference. External
resistors and capacitors can be connected to set the gain and
frequency response. The “Spl Amp In” input is ac coupled.
(Test Conditions: VCC = 2.6 V, TA = 25°C, fin = 1.0 kHz, External resistors Set for Gain of 1.)
Characteristic Condition Input
Pin Measure
Pin Symbol Min Typ Max Unit
Open Loop Gain –Spl Amp
In Tx Out AVOL – 60 – dB
Gain Bandwidth –Spl Amp
In Tx Out GBW – 100 – kHz
Maximum Output Swing RL = 10 kΩSpl Amp
In Tx Out VOmax – VCC – 0.3 – Vpp
Tx Audio Path Recommendation
The recommended configuration for the Tx Audio path
includes setting the Microphone Amplifier gain to 16 dB using
the external gain setting resistors and setting the Splatter
Amplifier gain to 9.0 dB using the external gain setting
resistors.
PLL Voltage Regulator
The PLL supply voltage is regulated to a nominal of 2.2 V.
The “VCC Audio” pin is the supply voltage for the internal
voltage regulator. The “PLL Vref ” pin is the 2.2 V regulated
output voltage. T wo capacitors with 10 µF and 0.01 µF values
must be connected to the “PLL V ref ” pin to filter and stabilize
this regulated voltage. The voltage regulator provides power
for the 2nd LO, Rx and Tx PLL’s, and MPU Interface. The
voltage regulator can also be used to provide a regulated
supply voltage for external IC’s. Rx and Tx PLL loop
performance are independent of the power supply voltage
when the voltage regulator is used. The voltage regulator
requires about 200 mV of “headroom”. When the power
supply decreases to within about 200 mV of the output
voltage, the regulator will go out of regulation but the output
voltage will not turn off. Instead, the output voltage will
maintain about a 200 mV delta to the power supply voltage as
the power supply voltage continues to decrease. The “PLL
Vref” pin can be connected to “VCC Audio” by the external
wiring if voltage higher than 2.2 V is required. But it should
not be connected to other supply except “VCC Audio”. The
voltage regulator is “on” in the Active and Rx modes. In the
Standby and Inactive modes, the voltage regulator is turned
off to reduce current drain and the “PLL Vref” pin is internally
connected to “VCC Audio” (i.e., the supply voltage is
maintained but is now unregulated).
(Test Conditions: VCC = 2.6 V, TA = 25°C.)
Characteristic Condition Input
Pin Measure
Pin Symbol Min Typ Max Unit
Output Voltge Level VCC = 2.6 V,
OL= 0 mA – VCC PLL Vout – 2.2 – V
Line Regulation IL = 0 mA, VCC = 2.6 to
5.5 V VCC VCC PLL Reg line – 3.66 40 mV
Load Regulation VCC = 2.6 V, IL = 0 to
1.0 mA VCC VCC PLL Regload –40 –2.28 – mV
MC13109A
11
MOTOROLA RF/IF DEVICE DATA
ELECTRICAL CHARACTERISTICS (continued)
Low Battery Detect
An external resistor divider is connected to the “Ref” input
pin to set the threshold for the low battery detect. The voltage
at the “Ref” input pin is compared to an internal 1.23 V
Bandgap reference voltage. The “BD Out” pin is open
collector and requires and external pull–up resistor to VCC.
(Test Conditions: VCC = 2.6 V, TA = 25°C.)
Characteristic Condition Input
Pin Measure
Pin Symbol Min Typ Max Unit
Average Threshold
Voltage Take average of rising
and falling threshold Ref Ref/
BD Out Threshold – 1.23 – V
Hysteresis – Ref Ref/
BD Out Hys – 2.0 – mV
Input Current Vin = 1.6 V – Ref Iin – 12.33 50 nA
Output High Voltage Vref = 1.6, RL = 3.9 kΩRef BD Out VOH VCC – 0.1 2.59 – V
Output Low Voltage Vref = 0.9, RL = 3.9 kΩRef BD Out VOL – 0.6 0.4 V
Figure 3. Data Amp Operation
Data
Signal
Data Amp
Data Amp
Output
Hysteresis
MC13109A
12 MOTOROLA RF/IF DEVICE DATA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PIN FUNCTION DESCRIPTION
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
48–TQFP
Pin
ÁÁ
52–QFP
Pin
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Symbol
ÁÁ
Type
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Description
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
1
2
ÁÁ
1
2
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
LO2 In
LO2 Out
ÁÁ
–
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
These pins form the PLL reference oscillator when connected to an external
parallel–resonant crystal (10.24 MHz typical). The reference oscillator is also the
second Local Oscillator (LO2) for the RF receiver.
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
3
ÁÁ
3
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
PLL V ref
ÁÁ
Supply
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Voltage Regulator output pin. The internal voltage regulator provides a stable
power supply voltage for the Rx and Tx PLL’s and can also be used as a
regulated supply voltage for the other IC’s.
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
4
ÁÁ
ÁÁ
ÁÁ
4
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Rx PD
ÁÁ
ÁÁ
ÁÁ
Output
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Three state voltage output of the Rx Phase Detector. This pin is either “high”,
“low”, or “high impedance” depending on the phase difference of the phase
detector input signals. During lock, very narrow pulses with a frequency equal to
the reference frequency are present. This pin drives the external Rx PLL loop
filter. It is important to minimize the line length and capacitance of this pin.
ÁÁÁÁ
ÁÁÁÁ
5
5
ÁÁÁÁÁ
ÁÁÁÁÁ
Gnd PLL
Gnd
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Ground pin for PLL section of IC.
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
6
ÁÁ
ÁÁ
6
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Tx PD
ÁÁ
ÁÁ
Output
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Three state voltage output of the Tx Phase Detector. This pin is either “high”,
“low”, or “high impedance” depending on the phase difference of the phase
detector input signals. During lock, very narrow pulses with a frequency equal to
the reference frequency are present. This pin drives the external Tx PLL loop
filter. It is important to minimize the line length and capacitance on this pin.
ÁÁÁÁ
ÁÁÁÁ
7
7
ÁÁÁÁÁ
ÁÁÁÁÁ
E Cap
–
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Expander rectifier filter capacitor pin. Connect capacitor to VCC.
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
8
ÁÁ
ÁÁ
8
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Tx VCO
ÁÁ
ÁÁ
Input
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
T ransmit divide counter input which is driven by an ac coupled external transmit
loop VCO. The minimum signal level is 200 mVpp @ 80.0 MHz. This pin also
functions as the test mode input for the counter tests.
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
9
10
11
ÁÁ
9
10
11
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Data
EN
Clk
ÁÁ
Input
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Microprocessor serial interface input pins for programming various counters and
control functions.
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
12
ÁÁ
ÁÁ
ÁÁ
12
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Clk Out
ÁÁ
ÁÁ
ÁÁ
Output
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Microprocessor Clock Output which is derived from the 2nd LO crystal oscillator
and a programmable divider. It can be used to drive a microprocessor and
thereby reduce the number of crystals required in the system design. The driver
has an internal resistor in series with the output which can be combined with an
external capacitor to form a low pass filter to reduce radiated noise on the PCB.
This output also functions as the output for the counter test modes.
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
N/A
ÁÁ
14
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Status Out
ÁÁ
Output
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
This pin indicates when the internal latches may have lost memory due to a
power glitch.
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
13
ÁÁ
15
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
CD Out/
Hardware
Interrupt
ÁÁ
Output/
Input
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Dual function pin; 1) Carrier detect output (open collector with external 100 kΩ
pull–up resistor. 2) Hardware interrupt input which can be used to “wake–up”
from Inactive Mode.
ÁÁÁÁ
ÁÁÁÁ
14
16
ÁÁÁÁÁ
ÁÁÁÁÁ
BD Out
Output
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Low battery detect output (open collector with external pull–up resistor).
ÁÁÁÁ
ÁÁÁÁ
15
17
ÁÁÁÁÁ
ÁÁÁÁÁ
DA Out
Output
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Data amplifier output (open collector with internal 100 kΩ pull–up resistor).
ÁÁÁÁ
ÁÁÁÁ
16
18
ÁÁÁÁÁ
ÁÁÁÁÁ
SA Out
Output
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Speaker amplifier output.
ÁÁÁÁ
ÁÁÁÁ
17
19
ÁÁÁÁÁ
ÁÁÁÁÁ
SA In
Input
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Speaker amplifier input (ac coupled).
ÁÁÁÁ
ÁÁÁÁ
18
20
ÁÁÁÁÁ
ÁÁÁÁÁ
E Out
Output
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Expander output.
ÁÁÁÁ
ÁÁÁÁ
19
21
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC Audio
Supply
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
VCC supply for audio section.
ÁÁÁÁ
ÁÁÁÁ
20
22
ÁÁÁÁÁ
ÁÁÁÁÁ
DA In
Input
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Data amplifier input (ac coupled).
ÁÁÁÁ
ÁÁÁÁ
21
23
ÁÁÁÁÁ
ÁÁÁÁÁ
Pre–Amp Out
Output
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Pre–amplifier output for connection of pre–amplifier feedback resistor.
ÁÁÁÁ
ÁÁÁÁ
22
24
ÁÁÁÁÁ
ÁÁÁÁÁ
Rx Audio In
Input
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Rx audio input to pre–amplifier (ac coupled).
ÁÁÁÁ
ÁÁÁÁ
23
25
ÁÁÁÁÁ
ÁÁÁÁÁ
Det Out
Output
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Audio output from FM detector.
ÁÁÁÁ
ÁÁÁÁ
24
26
ÁÁÁÁÁ
ÁÁÁÁÁ
RSSI
–
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Receive signal strength indicator filter capacitor.
ÁÁÁÁ
ÁÁÁÁ
N/A
27
ÁÁÁÁÁ
ÁÁÁÁÁ
N/A
–
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Not used.
ÁÁÁÁ
ÁÁÁÁ
25
28
ÁÁÁÁÁ
ÁÁÁÁÁ
Q Coil
–
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
A quad coil or ceramic discriminator are connected to this pin.
ÁÁÁÁ
ÁÁÁÁ
26
29
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC RF
Supply
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
VCC supply for RF receiver section.
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
27
28
ÁÁ
30
31
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Lim C2
Lim C1
ÁÁ
–
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
IF amplifier/limiter capacitor pins.
MC13109A
13
MOTOROLA RF/IF DEVICE DATA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PIN FUNCTION DESCRIPTION (continued)
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
48–TQFP
Pin
ÁÁ
52–QFP
Pin
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Symbol
ÁÁ
Type
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Description
ÁÁÁÁ
ÁÁÁÁ
29
32
ÁÁÁÁÁ
ÁÁÁÁÁ
Lim In
Input
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Signal input for IF amplifier/limiter.
ÁÁÁÁ
ÁÁÁÁ
30
33
ÁÁÁÁÁ
ÁÁÁÁÁ
Gnd RF
Gnd
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Ground pin for RF section of the IC.
ÁÁÁÁ
ÁÁÁÁ
31
34
ÁÁÁÁÁ
ÁÁÁÁÁ
Mix2 Out
Output
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Second mixer output.
ÁÁÁÁ
ÁÁÁÁ
32
35
ÁÁÁÁÁ
ÁÁÁÁÁ
Mix2 In
Input
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Second mixer input.
ÁÁÁÁ
ÁÁÁÁ
33
36
ÁÁÁÁÁ
ÁÁÁÁÁ
VB
–
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Internal half supply analog ground reference.
ÁÁÁÁ
ÁÁÁÁ
34
37
ÁÁÁÁÁ
ÁÁÁÁÁ
Mix1 Out
Output
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
First mixer output.
ÁÁÁÁ
ÁÁÁÁ
35
38
ÁÁÁÁÁ
ÁÁÁÁÁ
Mix1 In2
Input
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Negative polarity first mixer input.
ÁÁÁÁ
ÁÁÁÁ
36
39
ÁÁÁÁÁ
ÁÁÁÁÁ
Mix1 In1
Input
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Positive polarity first mixer input.
ÁÁÁÁ
ÁÁÁÁ
37
38
40
41
ÁÁÁÁÁ
ÁÁÁÁÁ
LO1 In
LO1 Out
–
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Tank elements for 1st LO multivibrator oscillator are connected to these pins.
ÁÁÁÁ
ÁÁÁÁ
39
42
ÁÁÁÁÁ
ÁÁÁÁÁ
Vcap Ctrl
–
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
1st LO varactor control pin.
ÁÁÁÁ
ÁÁÁÁ
40
43
ÁÁÁÁÁ
ÁÁÁÁÁ
Gnd Audio
Gnd
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Ground for audio section of the IC.
ÁÁÁÁ
ÁÁÁÁ
41
44
ÁÁÁÁÁ
ÁÁÁÁÁ
Tx In
Input
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Tx path input to Microphone Amplifier (ac coupled).
ÁÁÁÁ
ÁÁÁÁ
42
45
ÁÁÁÁÁ
ÁÁÁÁÁ
Amp Out
Output
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Microphone amplifier output.
ÁÁÁÁ
ÁÁÁÁ
43
46
ÁÁÁÁÁ
ÁÁÁÁÁ
C In
Input
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Compressor input (ac coupled).
ÁÁÁÁ
ÁÁÁÁ
44
47
ÁÁÁÁÁ
ÁÁÁÁÁ
C Cap
–
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Compressor rectifier filter capacitor pin. Connect capacitor to VCC.
ÁÁÁÁ
ÁÁÁÁ
45
48
ÁÁÁÁÁ
ÁÁÁÁÁ
Lim Out
Output
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Tx path limiter output.
ÁÁÁÁ
ÁÁÁÁ
46
49
ÁÁÁÁÁ
ÁÁÁÁÁ
Spl Amp In
Input
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Splatter amplifier input (ac coupled).
ÁÁÁÁ
ÁÁÁÁ
47
50
ÁÁÁÁÁ
ÁÁÁÁÁ
Tx Out
Output
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Tx path audio output.
ÁÁÁÁ
ÁÁÁÁ
48
51
ÁÁÁÁÁ
ÁÁÁÁÁ
Ref
Input
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Reference voltage input for low battery detect.
ÁÁÁÁ
ÁÁÁÁ
N/A
52
ÁÁÁÁÁ
ÁÁÁÁÁ
N/A
–
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Not used.
Power Supply Voltage
This circuit is used in a cordless telephone handset and
base unit. The handset is battery powered and can operate
on two or three NiCad cells or on 5.0 V power.
PLL Frequency Synthesizer General Description
Figure 4 shows a simplified block diagram of the
programmable universal dual phase locked loop (PLL). This
dual PLL is fully programmable through the MCU serial
interface and supports most country channel frequencies
including USA (25 ch), France, Spain, Australia, Korea, New
Zealand, U.K., Netherlands and China (see channel
frequency tables in Appendix A).
The 2nd local oscillator and reference divider provide the
reference frequency for the Rx and Tx PLL loops. The
programmed divider value for the reference divider is
selected based on the crystal frequency and the desired Rx
and Tx reference frequency values. Additional divide by 25
and divide by 4 blocks are provided to allow for generation of
the 1.0 kHz and 6.25 kHz reference frequencies required for
the U.K. The 14–Bit Tx counter is programmed for the
desired transmit channel frequency . The 14–Bit Rx counter is
programmed for the desired first local oscillator frequency. All
counters power up in the proper default state for USA
channel #6 and for a 10.24 MHz reference frequency crystal.
Internal fixed capacitors can be connected to the tank circuit
of the 1st LO through microprocessor control to extend the
sensitivity of the 1st LO for U.S. 25 channel operation.
MC13109A
14 MOTOROLA RF/IF DEVICE DATA
14–b Programmable
Rx Counter
Figure 4. Dual PLL Simplified Block Diagram
14–b Programmable
Tx Counter
12–b
Programmable
Reference
Counter
÷25
÷1
÷4
LO2 In
LO2 Out
1, 1
2, 2
Tx PD
8, 8
6, 6
Tx VCO
Rx PD
4, 4
LO1 In
37, 40
LO1 Out
38, 41
Tx Phase
Detector
Rx Phase
Detector
Tx
VCO
LPF
Tx Ref
Rx Ref
U.K. Base
U.K. Handset
U.K. Handset
U.K. Base
LPF
Vcap Ctrl
39, 42
1st LO
LO2
ELECTRICAL CHARACTERISTICS (VCC = 2.6 V, TA = 25°C)
Characteristic Condition Measure
Pin Symbol Min Typ Max Unit
PLL PIN DC
Input Voltage Low – Data
Clk
EN
Hardware Int.
VIL – – 0.3 V
Input Voltage High – Data
Clk
EN
VIH “PLL V ref” –
0.3 – “VCC Audio” V
Input Current Low Vin = 0.3 V Data
Clk
EN
IIL –5.0 –3.0 – µA
Input Current High Vin = (VCC Audio) –
0.3 Data
Clk
EN
IIH – 0.6 5.0 µA
Hysteresis Voltage – Data
Clk
EN
Vhys – 1.0 – V
Output Current High –Rx PD
Tx PD IOH – – –0.7 mA
Output Current Low –Rx PD
Tx PD IOL 0.7 – – mA
Output Voltage Low IIL = 0.7 mA Rx PD
Tx PD VOL – – (PLL Vref)*
0.2 V
Output Voltage High IIH = –0. 7mA Rx PD
Tx PD VOH (PLL Vref)*
0.8 – – V
T ri–State Leakage
Current V = 1.2 V Rx PD
Tx PD IOZ –50 – 50 nA
Input Capacitance – Data
Clk
EN
Cin – – 8.0 pF
Output Capacitance –Rx PD
Tx PD Cout – – 8.0 pF
MC13109A
15
MOTOROLA RF/IF DEVICE DATA
ELECTRICAL CHARACTERISTICS (continued) (VCC = 2.6 V, TA = 25°C)
Characteristic UnitMaxTypMinSymbol
Measure
PinCondition
PLL PIN INTERFACE
EN to Clk Setup T ime –EN, Clk tsuEC 200 – – ns
Data to Clk Setup T ime –Data, Clk tsuDC 100 – – ns
Hold T ime –Data, Clk th90 – – ns
Recovery Time –EN, Clk trec 90 – – ns
Input Pulse Width –EN, Clk tw100 – – ns
Input Rise and Fall T ime – Data
Clk
EN
tr, tf– – 9.0 µs
MPU Interface
Power–Up Delay 90% of PLL Vref to
Data, Clk, EN – tpuMPU – 100 – µs
PLL LOOP
2nd LO Frequency – LO2 In
LO2 Out fLO – – 12 MHz
“Tx VCO” Input Frequency Vin = 200 mVpp Tx VCO ftxmax – – 80 MHz
PLL I/O Pin Specifications
The 2nd LO, Rx and Tx PLL’s and MPU serial interface are
normally powered by the internal voltage regulator at the “PLL
Vref” pin. The “PLL Vref” pin is the output of a voltage regulator
which is powered from the “VCC Audio” power supply pin.
Therefore, the maximum input and output levels for most PLL
I/O pins (LO2 In, LO2 Out, Rx PD, Tx PD, Tx VCO) is the
regulated voltage at the “PLL Vref” pin. The ESD protection
diodes on these pins are also connected to “PLL Vref”.
Internal level shift buffers are provided for the pins (Data, Clk,
EN, Clk Out) which connect directly to the microprocessor.
The maximum input and output levels for these pins is VCC.
Figure 5 shows a simplified schematic of the PLL I/O pins.
Figure 5. PLL I/O Pin Simplified Schematics
PLL Vref
(2.2 V)
InI/O
VCC Audio
(2.0 to 5.5 V) PLL Vref
(2.2 V) VCC Audio
(2.0 to 5.5 V)
Clk Out PinData, Clk, and EN PinsLO2 In, LO2 Out,
Rx PD, Tx PD and
Tx VCO Pins
Out
2.0 µA
1.0 kΩ
Microprocessor Serial Interface
The “Data”, “Clk”, and “EN” pins provide an MPU serial
interface for programming the reference counters, the
transmit and receive channel divider counter and various
control functions. The “Data” and “Clk” pins are used to load
data into the shift register. Figure 6 shows “Data” and “Clk”
pin timing. Data is clocked on positive clock transitions.
Figure 6. Data and Clock Timing Requirement
Data,
Clk, EN
Data
Clk
tsuDC
trtf
50%
50%
th
10%
90%
After data is loaded into the shift register, the data is
latched into the appropriate latch register using the “EN” pin.
This is done in two steps. First, an 8–Bit address is loaded
into the shift register and latched into the 8–Bit address latch
register. Then, up to 16–Bits of data is loaded into the shift
register and latched into the data latch register specified by
the address that was previously loaded. Figure 7 shows the
timing required on the EN pin. Latching occurs on the
negative EN transition.
MC13109A
16 MOTOROLA RF/IF DEVICE DATA
Figure 7. Enable Timing Requirement
Clk
EN
tsuEC
50%
50% 50%
trec
Previous Data Latch
Last
Clock First
Clock
50%
The state of the EN pin when clocking data into the shift
register determines whether the data is latched into the
address register or a data register. Figure 8 shows the
address and data programming diagrams. In the data
programming mode, there must not be any clock transitions
when “EN” is high. The clock can be in a high state (default
high) or a low state (default low) but must not have any
transitions during the “EN” high state. The convention in
these figures is that latch bits to the left are loaded into the
shift register first.
Figure 8. Microprocessor Interface Programming
Mode Diagrams
Data 8–Bit Address
EN
Data
EN
Address Register Programming Mode
16–Bit Data
Data Register Programming Mode
Latch
Latch
MSB
MSB LSB
LSB
The MPU serial interface is fully operational within 100 µs
after the power supply has reached its minimum level during
power–up (See Figure 9). The MPU Interface shift registers
and data latches are operational in all four power saving
modes; Inactive, Standby, Rx, and Active Modes. Data can
be loaded into the shift registers and latched into the latch
registers in any of the operating modes.
Figure 9. Microprocessor Serial Interface
Power–Up Delay
VCC tpuMPU
2.0 V
Data,
Clk, EN
Status Out
This is a digital output which indicates whether the latch
registers have been reset to their power–up default values.
Latch power–up default values are given in Figure 28. If there
is a power glitch or ESD event which causes the latch
registers to be reset to their default values, the “Status Out”
pin will indicate this to the MPU so it can reload the correct
information into the latch registers.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 10. Status Out Operation
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Status Latch Register Bits
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Status Out
Logic Level
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
Latch bits not at power–up default value
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
Latch bits at power–up default value
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
Data Registers
Figure 11 shows the data latch registers and addresses
which are used to select each of these registers. Latch bits to
the left (MSB) are loaded into the shift register first. The LSB
bit must always be the last bit loaded into the shift register.
“Don’t Care” bits can be loaded into the shift register first if
8–Bit bytes of data are loaded.
MC13109A
17
MOTOROLA RF/IF DEVICE DATA
1. (00000001)
Latch Address
U.K. Handset
Select
2. (00000010)
3. (00000011)
4. (00000100)
5. (00000101)
7. (0000011 1)
14–Bit Tx CounterMSB LSB
MSB LSB
MSB LSB
MSB LSB
MSB LSB
14–Bit Rx Counter
12–Bit Reference Counter
5–Bit CD Threshold Control
4–Bit Test Mode 3–Bit 1st LO
Capacitor Selection
14–Bit
Volume
Control
U.K. Base
Select
ALC
Disable Not
Used Limiter
Disable Clk
Disable MPU
Clk1 MPU
Clk0 Stdby
Mode Rx
Mode Tx
Mute Rx
Mute SP
Mute
Tx Counter Latch
Rx Counter Latch
Reference Counter Latch
Mode Control Latch
Threshold Control Latch
7–Bit Auxillary Latch
6. (00000110)
Figure 11. Microprocessor Interface Data Latch Registers
Reference Frequency Selection
The “LO2 In” and “LO2 Out” pins form a reference oscillator
when connected to an external parallel–resonant crystal. The
reference oscillator is also the second local oscillator for the
RF Receiver. Figure 12 shows the relationship between
different crystal frequencies and reference frequencies for
cordless phone applications in various countries.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 12. Reference Frequency and
Reference Divider Values
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
Reference
ÁÁÁÁÁ
ÁÁÁÁÁ
U.K. Base/
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Crystal
ÁÁÁÁ
ÁÁÁÁ
Divider
ÁÁÁÁÁ
ÁÁÁÁÁ
Handset
ÁÁÁÁÁ
ÁÁÁÁÁ
Reference
ÁÁÁÁÁÁ
Frequency
ÁÁÁÁ
Value
ÁÁÁÁÁ
Divider
ÁÁÁÁÁ
Frequency
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
10.24 MHz
ÁÁÁÁ
ÁÁÁÁ
2048
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
5.0 kHz
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
10.24 MHz
ÁÁÁÁ
ÁÁÁÁ
1024
ÁÁÁÁÁ
ÁÁÁÁÁ
4
ÁÁÁÁÁ
ÁÁÁÁÁ
2.5 kHz
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
11.15 MHz
ÁÁÁÁ
ÁÁÁÁ
2230
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
5.0 kHz
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
12.00 MHz
ÁÁÁÁ
ÁÁÁÁ
2400
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
5.0 kHz
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
11.15 MHz
ÁÁÁÁ
ÁÁÁÁ
1784
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
6.25 kHz
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
11.15 MHz
ÁÁÁÁ
ÁÁÁÁ
446
ÁÁÁÁÁ
ÁÁÁÁÁ
4
ÁÁÁÁÁ
ÁÁÁÁÁ
6.25 kHz
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
11.15 MHz
ÁÁÁÁ
ÁÁÁÁ
446
ÁÁÁÁÁ
ÁÁÁÁÁ
25
ÁÁÁÁÁ
ÁÁÁÁÁ
1.0 kHz
Reference Counter
Figure 13 shows how the reference frequencies for the Rx
and Tx loops are generated. All countries except U.K. require
that the Tx and Rx reference frequencies be identical. In this
case, set “U.K. Base Select” and “U.K. Handset Select” bits
to “0”. Then the fixed divider is set to “1” and the Tx and Rx
reference frequencies will be equal to the crystal oscillator
frequency divided by the programmable reference counter
value. The U.K. is a special case which requires a different
reference frequency value of Tx and Rx.
For U.K. base operation, set “U.K. Base Select” to “1”. For
U.K. handset operation, set “U.K. Handset Select” to “1”. The
Netherlands is also a special case since a 2.5 kHz reference
frequency is used for both the Tx and Rx reference and the
total divider value required is 4096 which is larger than the
maximum divide value available from the 12–Bit reference
divider (4095). In this case, set “U.K. Base Select” to “1” and
set “U.K. Handset Select” to “1”. This will give a fixed divide
by 4 for both the Tx and Rx reference. Then set the reference
divider to 1024 to get a total divider of 4096.
Mode Control Register
Power saving modes, mutes, disables, volume control,
and microprocessor clock output frequency are all set by the
Control Register. Operation of the Control Register is
explained in Figures 14 through 21.
MC13109A
18 MOTOROLA RF/IF DEVICE DATA
0
0
1
1
0
1
0
1
1
25
4
4
1
4
25
4
LO2 Out
Tx Reference Frequency
Figure 13. Reference Register Programming Mode
12–b
Programmable
Reference
Counter
÷25
÷1
÷4
LO2 In
Rx Reference Frequency
U.K. Base
U.K. Handset
U.K. Handset
U.K. Base
U.K. Handset
Select U.K. Base
Select
LO2
Tx Divider
Value Rx Divider
Value Application
All but U.K. and Netherlands
U.K. Baseset
U.K. Handset
Netherlands Base and Handset
U.K. Handset
Select MSB LSB12–Bit Reference Counter
U.K. Base
Select
14–Bit Reference Counter Latch
Figure 14. Control Register Bits
MSB LSB
4–Bit Volume
Control
ALC
Disable Not
Used Limiter
Disable Clk
Disable MPU
Clk1 MPU
Clk0 Stdby
Mode Rx
Mode Tx
Mute Rx
Mute SP
Mute
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 15. Mute and Disable Control Bit Descriptions
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
ALC Disable
ÁÁÁ
Á
Á
Á
ÁÁÁ
1
0
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Automatic Level Control Disabled
Normal Operation
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Limiter Disable
ÁÁÁ
Á
Á
Á
ÁÁÁ
1
0
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Limiter Disabled
Normal Operation
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Clock Disable
ÁÁÁ
ÁÁÁ
1
0
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
MPU Clock Output Disabled
Normal Operation
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Tx Mute
ÁÁÁ
Á
Á
Á
ÁÁÁ
1
0
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
T ransmit Channel Muted
Normal Operation
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Rx Mute
ÁÁÁ
Á
Á
Á
ÁÁÁ
1
0
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Receive Channel Muted
Normal Operation
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
SP Mute
ÁÁÁ
ÁÁÁ
1
0
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
Speaker Amp Muted
Normal Operation
Power Saving Operating Modes
When the MC13109A is used in a handset, it is important
to conserve power in order to prolong battery life. There are
five modes of operation; Active, Rx, Standby, Interrupt and
Inactive. In Active Mode, all circuit blocks are powered. In Rx
mode, all circuitry is powered down except for those circuit
sections needed to receive a transmission from the base. In
the Standby and Interrupt Modes, all circuitry is powered
down except for the circuitry needed to provide the clock
output for the microprocessor . In Inactive Mode, all circuitry is
powered down except the MPU interface. Latch memory is
maintained in all modes. Figure 16 shows the control register
bit values for selection of each power saving mode and
Figure 17 show the circuit blocks which are powered in each
of these operating mode.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 16. Power Saving Mode Selection
ÁÁÁ
Á
Á
Á
ÁÁÁ
Stdby
Mode
Bit
ÁÁÁ
Á
Á
Á
ÁÁÁ
Rx
Mode
Bit
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
“CD Out/Hardware
Interrupt” Pin
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Power Saving
Mode
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
X
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Active
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
X
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Rx
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
X
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Standby
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1 or High Impedance
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Inactive
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Inactive
MC13109A
19
MOTOROLA RF/IF DEVICE DATA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 17. Circuit Blocks Powered During Power Saving Modes
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Circuit Blocks
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Active
ÁÁÁÁ
ÁÁÁÁ
Rx
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Standby
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Inactive
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
“PLL V ref” Regulated Voltage
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
X
ÁÁÁÁ
ÁÁÁÁ
X
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
X1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
X1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
MPU Interface
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
X
ÁÁÁÁ
ÁÁÁÁ
X
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
X
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
X
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
2nd LO Oscillator
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
X
ÁÁÁÁ
ÁÁÁÁ
X
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
X
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
MPU Clock Output
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
X
ÁÁÁÁ
ÁÁÁÁ
X
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
X
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
RF Receiver
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
X
ÁÁÁÁ
ÁÁÁÁ
X
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
1st LO VCO
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
X
ÁÁÁÁ
ÁÁÁÁ
X
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Rx PLL
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
X
ÁÁÁÁ
ÁÁÁÁ
X
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Carrier Detect
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
X
ÁÁÁÁ
ÁÁÁÁ
X
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Data Amp
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
X
ÁÁÁÁ
ÁÁÁÁ
X
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Low Battery Detect
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
X
ÁÁÁÁ
ÁÁÁÁ
X
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Tx PLL
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
X
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Rx Audio Path
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
X
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Tx Audio Path
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
X
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
NOTE: 1.In Standby and Inactive Modes, “PLL V ref” remains powered but is not regulated. It will fluctuate with VCC.
Inactive Mode Operation and Hardware Interrupt
In some handset applications it may be desirable to power
down all circuitry including the microprocessor (MPU). First
put the MC13109A into the Inactive mode, which turns off the
MPU Clock Output (see Figure 18), and then disable the
microprocessor. In order to give the MPU adequate time to
power down, the MPU Clock output remains active for a
minimum of one reference counter cycle (about 200 µs) after
the command is given to switch into the “Inactive” mode. An
external timing circuit should be used to initiate the turn–on
sequence. The “CD Out” pin has a dual function. In the Active
and Rx modes it performs the carrier detect function. In the
Standby and Inactive modes the carrier detect circuit is
disabled and the “CD Out” pin is in a “High” state due to the
external pull–up resistor. In the Inactive mode the “CD Out”
pin is the input for the hardware interrupt function. When the
“CD Out” pin is pulled “low” by the external timing circuit, the
MC13109A switches from the Inactive to the Interrupt mode
thereby turning on the MPU Clock Output. The MPU can then
resume control of the combo IC. The “CD Out” pin must
remain low until the MPU changes the operating mode from
Interrupt to Standby, Active or Rx modes.
Figure 18. Hardware Interrupt Operation
Mode
EN
CD Out/Hardware Interrupt
MPU Clock Out
CD Out Low
Delay after MPU selects Inactive Mode to when CD turns off
CD Turns Off
External Timer
Pulls Pin Low
MPU Initiates
Mode Change
Timer Output
Disabled
MPU Initiates
Inactive Mode
“MPU Clock Out” remains active for a minimum of one count of reference
counter after “CD Out/Hardware Interrupt” pin goes high
Active/Rx Inactive Interrupt Standby/Rx/Active
MC13109A
20 MOTOROLA RF/IF DEVICE DATA
“Clk Out” Divider Programming
The “Clk Out” pin is derived from the 2nd local oscillator and
can be used to drive a microprocessor, thereby reducing the
number of crystals required. Figure 19 shows the relationship
between the crystal frequency and the clock output for
different divider values. Figure 20 shows the “Clk Out” register
bit values.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 19. Clock Output Values
ÁÁÁÁÁ
ÁÁÁÁÁ
Crystal
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Clock Output Divider
ÁÁÁÁÁ
ÁÁÁÁÁ
Crystal
Frequency
ÁÁÁÁ
ÁÁÁÁ
2
ÁÁÁÁ
ÁÁÁÁ
3
ÁÁÁÁ
ÁÁÁÁ
5
ÁÁÁÁ
ÁÁÁÁ
10
ÁÁÁÁÁ
ÁÁÁÁÁ
10.24 MHz
ÁÁÁÁ
ÁÁÁÁ
5.120 MHz
ÁÁÁÁ
ÁÁÁÁ
3.413 MHz
ÁÁÁÁ
ÁÁÁÁ
2.048 MHz
ÁÁÁÁ
ÁÁÁÁ
1.024 MHz
ÁÁÁÁÁ
ÁÁÁÁÁ
11.15 MHz
ÁÁÁÁ
ÁÁÁÁ
5.575 MHz
ÁÁÁÁ
ÁÁÁÁ
3.717 MHz
ÁÁÁÁ
ÁÁÁÁ
2.230 MHz
ÁÁÁÁ
ÁÁÁÁ
1.115 MHz
ÁÁÁÁÁ
ÁÁÁÁÁ
12.00 MHz
ÁÁÁÁ
ÁÁÁÁ
6.000 MHz
ÁÁÁÁ
ÁÁÁÁ
4.000 MHz
ÁÁÁÁ
ÁÁÁÁ
2.400 MHz
ÁÁÁÁ
ÁÁÁÁ
1.200 MHz
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 20. Clock Output Divider
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Clk Out
Bit #1
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Clk Out
Bit #2
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Clk Out
Divider Value
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
2
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
3
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
5
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
10
MPU “Clk Out” Power–Up Default Divider Value
The power–up default divider value is “divide by 10”. This
provides an MPU clock of about 1.0 MHz after initial
power–up. The reason for choosing this relatively low clock
frequency after intial power–up is that some microprocessors
that operate down to a 2.0 V power supply have a maximum
clock frequency of 1.0 MHz. After initial power–up, the MPU
can change the clock divider value to set the clock to the
desired operating frequency. Special care has been taken in
the design of the clock divider to ensure that the transition
between one clock divider value and another is “smooth”
(i.e., there will be no narrow clock pulses to disturb the MPU).
MPU “Clk Out” Radiated Noise on Circuit Board
The clock line running between the MC13109A and the
microprocessor has the potential to radiate noise which can
cause problems in the system especially if the clock is a
square wave digital signal with large high frequency
harmonics. In order to minimize radiated noise, a 1.0 kΩ
resistor is included on–chip in–series with the “Clk Out” output
driver . A small capacitor can be connected to the “Clk Out” line
on the PCB to form a single pole low pass filter. This filter will
significantly reduce noise radiated from the “Clk Out” line.
Volume Control
The volume control can be programmed in 2.0 dB gain steps
from –14 dB to 16 dB. The power–up default value is 0 dB.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 21. Volume Control
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Volume Control
Bit #3
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Volume Control
Bit #2
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Volume Control
Bit #1
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Volume Control
Bit #0
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
Volume
Control #
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Gain/Attenuation
Amount
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
–14 dB
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
–12 dB
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
2
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
–10 dB
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
3
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
–8.0 dB
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
4
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
–6.0 dB
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
5
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
–4.0 dB
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
6
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
–2.0 dB
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
7
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0 dB
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
8
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
2.0 dB
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
9
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
4.0 dB
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
10
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
6.0 dB
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
11
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
8.0 dB
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
12
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
10 dB
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
13
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
12 dB
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
14
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
14 dB
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
15
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
16 dB
Gain Control Register
The gain control register contains bits which control the
Carrier Detect threshold. Operation of these latch bits are
explained in Figures 22 and 23. MSB LSB5–Bit CD Threshold Control
Figure 22. Gain Control Latch Bits
MC13109A
21
MOTOROLA RF/IF DEVICE DATA
Carrier Detect Threshold Programming
The “CD Out” pin will give an indication to the
microprocessor if a carrier signal is present on the selected
channel. The nominal value and tolerance of the carrier
detect threshold is given in the carrier detect specification
section of this document. If a different carrier detect threshold
value is desired, it can be set through the MPU interface as
shown in Figure 23 below.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 23. Carrier Detect Threshold Control
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
CD
Bit #4
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
CD
Bit #3
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
CD
Bit #2
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
CD
Bit #1
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
CD
Bit #0
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
CD
Control #
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
Carrier Detect
Threshold
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–20 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–19 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
2
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–18 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
3
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–17 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
4
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–16 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
5
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–15 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
6
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–14 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
7
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–13 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
8
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–12 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
9
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–11 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
10
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–10 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
11
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–9.0 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
12
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–8.0 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
13
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–7.0 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
14
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–6.0 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
15
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–5.0 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
16
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–4.0 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
17
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–3.0 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
18
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–2.0 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
19
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–1.0 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
20
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
0 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
21
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
1.0 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
22
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
2.0 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
23
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
3.0 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
24
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
4.0 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
25
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
5.0 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
26
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
6.0 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
27
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
7.0 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
28
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
8.0 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
29
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
9.0 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
30
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
10 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
31
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
11 dB
MC13109A
22 MOTOROLA RF/IF DEVICE DATA
Auxiliary Register
The auxiliary register contains a 3–Bit 1st LO Capacitor
Selection latch and a 4–Bit Test Mode latch. Operation of
these latch bits are explained in Figures 24, 25 and 26.
Figure 24. Auxiliary Register Latch Bits
4–Bit Test Mode 3–Bit 1st LO
Capacitor Selection
MSB LSB MSB LSB
First Local Oscillator Capacitor Selection for 25
Channel U.S. Operation
There is a very large frequency difference between the
minimum and maximum channel frequencies in the proposed
25 Channel U.S. standard. The sensitivity of the 1st LO is not
large enough to accommodate this large frequency variation.
Fixed capacitors can be connected across the 1st LO tank
circuit to change the 1st LO sensitivity. Internal switches and
capacitors are provided to enable microprocessor control
over internal fixed capacitor values. Figure 25 shows the
schematic of the 1st LO tank circuit. Figure 26 shows the
latch control bit values.
Figure 25. First LO Schematic
LO1 In
40
LO1 Out
41
Vcap Ctrl
42
Internal Capacitor
1st LO
Varactor
Varactor
Cext Lext
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 26. 1st LO Capacitor Select for U.S. 25 Channels
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
1st LO
Cap.
Bit 2
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
1st LO
Cap.
Bit 1
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
1st LO
Cap.
Bit 0
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
1st LO
Cap.
Select
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
U.S.
Base
Channels
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
U.S.
Handset
Channels
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Varactor Value
over 0.5 to 2.2
V Range
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
External
Capacitor
Value
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
External
Inductor
Value
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
16 – 25
ÁÁÁÁÁ
ÁÁÁÁÁ
–
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
10 – 6.4 pF
ÁÁÁÁÁ
ÁÁÁÁÁ
27 pF
ÁÁÁÁÁ
ÁÁÁÁÁ
0.47 µH
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
–
ÁÁÁÁÁ
ÁÁÁÁÁ
16 – 25
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
10 – 6.4 pF
ÁÁÁÁÁ
ÁÁÁÁÁ
33 pF
ÁÁÁÁÁ
ÁÁÁÁÁ
0.47 µH
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1 – 6
ÁÁÁÁÁ
ÁÁÁÁÁ
–
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
10 – 6.4 pF
ÁÁÁÁÁ
ÁÁÁÁÁ
27 pF
ÁÁÁÁÁ
ÁÁÁÁÁ
0.47 µH
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
2
ÁÁÁÁÁ
ÁÁÁÁÁ
7 – 15
ÁÁÁÁÁ
ÁÁÁÁÁ
–
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
10 – 6.4 pF
ÁÁÁÁÁ
ÁÁÁÁÁ
27 pF
ÁÁÁÁÁ
ÁÁÁÁÁ
0.47 µH
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
3
ÁÁÁÁÁ
ÁÁÁÁÁ
–
ÁÁÁÁÁ
ÁÁÁÁÁ
1 – 6
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
10 – 6.4 pF
ÁÁÁÁÁ
ÁÁÁÁÁ
33 pF
ÁÁÁÁÁ
ÁÁÁÁÁ
0.47 µH
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
4
ÁÁÁÁÁ
ÁÁÁÁÁ
–
ÁÁÁÁÁ
ÁÁÁÁÁ
7 – 15
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
10 – 6.4 pF
ÁÁÁÁÁ
ÁÁÁÁÁ
33 pF
ÁÁÁÁÁ
ÁÁÁÁÁ
0.47 µH
MC13109A
23
MOTOROLA RF/IF DEVICE DATA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 27. Test Mode Description
ÁÁÁ
Á
Á
Á
ÁÁÁ
TM #
ÁÁÁ
Á
Á
Á
ÁÁÁ
TM 3
ÁÁÁ
Á
Á
Á
ÁÁÁ
TM 2
ÁÁÁ
Á
Á
Á
ÁÁÁ
TM 1
ÁÁÁ
Á
Á
Á
ÁÁÁ
TM 0
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
Counter Under Test or
Test Mode Option
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
“Tx VCO”
Input Signal
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
“Clk Out” Output Expected
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
Normal Operation
ÁÁÁÁÁ
ÁÁÁÁÁ
>200 mVpp
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
–
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
Rx Counter, upper 6
ÁÁÁÁÁ
ÁÁÁÁÁ
0 to 2.2 V
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Input Frequency/64
ÁÁÁ
ÁÁÁ
2
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
Rx Counter, lower 8
ÁÁÁÁÁ
ÁÁÁÁÁ
0 to 2.2 V
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
See Note Below
ÁÁÁ
ÁÁÁ
3
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
Rx Prescaler
ÁÁÁÁÁ
ÁÁÁÁÁ
0 to 2.2 V
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Input Frequency/4
ÁÁÁ
ÁÁÁ
4
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
Tx Counter, upper 6
ÁÁÁÁÁ
ÁÁÁÁÁ
0 to 2.2 V
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Input Frequency/64
ÁÁÁ
ÁÁÁ
5
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
Tx Counter, lower 8
ÁÁÁÁÁ
ÁÁÁÁÁ
0 to 2.2 V
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
See Note Below
ÁÁÁ
ÁÁÁ
6
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
Tx Prescaler
ÁÁÁÁÁ
ÁÁÁÁÁ
>200 mVpp
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Input Frequency/4
ÁÁÁ
ÁÁÁ
7
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
Reference Counter
ÁÁÁÁÁ
ÁÁÁÁÁ
0 to 2.2 V
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Input Frequency/Reference Counter Value
ÁÁÁ
ÁÁÁ
8
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
Divide by 4, 25
ÁÁÁÁÁ
ÁÁÁÁÁ
0 to 2.2 V
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Input Frequency/100
ÁÁÁ
ÁÁÁ
9
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
AGC Gain = 10 Option
ÁÁÁÁÁ
ÁÁÁÁÁ
N/A
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
–
ÁÁÁ
ÁÁÁ
10
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
AGC Gain = 25 Option
ÁÁÁÁÁ
ÁÁÁÁÁ
N/A
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
–
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
NOTE: To determine the correct output, look at the lower 8 bits in the Rx or Tx register (Divisor (7;0). If the value of the divisor is > 16, then the output divisor
value is Divisor (7;2) (the upper 6 bits of the divisor). If Divisor (7;0) < 16 and Divisor (3;2) > = 2, then output divisor value is Divisor (3;2) (bits 2 and 3
of the divisor). If Divisor (7;0) < 16 and Divisor (3;2) < 2, then output divisor value is (Divisor (3;2) + 60).
Test Modes
Test Mode Control latch bits enable independent testing of
internal counters and set AGC Gain Options. In test mode,
the “Tx VCO” input pin is multiplexed to the input of the
counter under test and the output of the counter under test is
multiplexed to the “Clk Out” output pin so that each counter
can be individually tested. Make sure test mode bits are set to
“0” for normal operation. Test mode operation is described in
Figure 27. During normal operation and when testing the Tx
Prescaler , the “Tx VCO” input can be a minimum of 200 mVpp
at 80 MHz and should be ac coupled. For other test modes,
input signals should be standard logic levels of 0 to 2.2 V and
a maximum frequency of 16 MHz.
Power–Up Defaults for Control and Counter Registers
When the IC is first powered up, all latch registers are
initialized to a defined state. The MC13109A is initially placed
in the Rx mode with all mutes active and nothing disabled.
The reference counter is set to generate a 5.0 kHz reference
frequency from a 10.24 MHz crystal. The MPU clock output
divider is set to 10 to give the minimum clock output
frequency. The Tx and Rx latch registers are set for USA
Channel Frequency #21. Figure 28 shows the initial
power–up states for all latch registers.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 28. Latch Register Power–Up Defaults
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
MSB
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
LSB
ÁÁÁÁÁ
ÁÁÁÁÁ
Register
ÁÁÁÁ
ÁÁÁÁ
Count
ÁÁÁ
ÁÁÁ
15
ÁÁ
ÁÁ
14
ÁÁÁ
ÁÁÁ
13
ÁÁÁ
ÁÁÁ
12
ÁÁ
ÁÁ
11
ÁÁÁ
ÁÁÁ
10
ÁÁ
ÁÁ
9
ÁÁÁ
ÁÁÁ
8
ÁÁÁ
ÁÁÁ
7
ÁÁ
ÁÁ
6
ÁÁÁ
ÁÁÁ
5
ÁÁÁ
ÁÁÁ
4
ÁÁ
ÁÁ
3
ÁÁÁ
ÁÁÁ
2
ÁÁ
ÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
Tx
ÁÁÁÁ
ÁÁÁÁ
9965
ÁÁÁ
ÁÁÁ
–
ÁÁ
ÁÁ
–
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁ
ÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁ
ÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁ
ÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
Rx
ÁÁÁÁ
ÁÁÁÁ
7215
ÁÁÁ
ÁÁÁ
–
ÁÁ
ÁÁ
–
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁ
ÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁ
ÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁ
ÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
Ref
ÁÁÁÁ
ÁÁÁÁ
2048
ÁÁÁ
ÁÁÁ
–
ÁÁ
ÁÁ
–
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
Mode
ÁÁÁÁ
ÁÁÁÁ
N/A
ÁÁÁ
ÁÁÁ
–
ÁÁ
ÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁ
ÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁ
ÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁ
ÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
Gain
ÁÁÁÁ
ÁÁÁÁ
N/A
ÁÁÁ
ÁÁÁ
–
ÁÁ
ÁÁ
–
ÁÁÁ
ÁÁÁ
–
ÁÁÁ
ÁÁÁ
–
ÁÁ
ÁÁ
–
ÁÁÁ
ÁÁÁ
–
ÁÁ
ÁÁ
–
ÁÁÁ
ÁÁÁ
–
ÁÁÁ
ÁÁÁ
–
ÁÁ
ÁÁ
–
ÁÁÁ
ÁÁÁ
–
ÁÁÁ
ÁÁÁ
1
ÁÁ
ÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁ
ÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
TM
ÁÁÁÁ
ÁÁÁÁ
N/A
ÁÁÁ
ÁÁÁ
–
ÁÁ
ÁÁ
–
ÁÁÁ
ÁÁÁ
–
ÁÁÁ
ÁÁÁ
–
ÁÁ
ÁÁ
–
ÁÁÁ
ÁÁÁ
–
ÁÁ
ÁÁ
–
ÁÁÁ
ÁÁÁ
–
ÁÁÁ
ÁÁÁ
–
ÁÁ
ÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
0
ÁÁÁ
ÁÁÁ
0
MC13109A
24 MOTOROLA RF/IF DEVICE DATA
Figure 29. ICC versus VCC at Active Mode Figure 30. ICC versus VCC at Receive Mode
Figure 31. ICC versus VCC at Standby Mode Figure 32. ICC versus VCC at Inactive Mode
Figure 33. RSSI Output versus RFin Figure 34. Recovered Audio/THD versus fDEV
fDEV, DEVIATION, (kHz)RFin, RF INPUT (dBm)
VCC, SUPPLY VOL TAGE (V)
THD
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
02.5 3.0 3.5 4.0 4.5 5.0 VCC, SUPPLY VOL TAGE (V)
5.0
4.5
4.0
3.5
3.0
2.52.5 3.0 3.5 4.0 4.5 5.0
VCC, SUPPLY VOL TAGE (V)
1.2
1.0
0.8
0.6
0.4
0.2
02.5 3.0 3.5 4.0 4.5 5.0 VCC, SUPPLY VOL TAGE (V)
80
70
60
50
40
30
20
10
02.5 3.0 3.5 4.0 4.5 5.0
1.6
1.0
0.8
0.6
0.4
0.2
0
–120 –100 –80 –60 –40 0
300
250
200
150
100
50
01.0 3.0 5.0 7.0 9.0
1.2
1.4
–20 2.0 4.0 6.0 8.0
Recovered Audio
R22 = 12 kΩ
6.0
5.0
4.0
3.0
2.0
1.0
0
, SUPPLY CURRENT ( A)µRECOVERED AUDIO (V) ICC
RSSI OUTPUT (dB) , SUPPLY CURRENT (mA)ICC
, SUPPLY CURRENT (mA)ICC
, SUPPLY CURRENT (mA)ICC
THD (%)
MC13109A
25
MOTOROLA RF/IF DEVICE DATA
Figure 35. Typical Expander Response Figure 36. Typical Compressor Response
Rx AUDIO IN (dBV)
10
0
–10
–20
–30
–40
–50
–60
–70
–35 –30 –25 –20 –15 0 COMPRESSOR, Cin LEVEL INPUT (dBV)
0
–10
–20
–30
–40
–60
–80 –70 –60 –50 –40 –30
0
–20
–40
–60
–80
–10 –5.0
–50
–20 –10 0
MIXER
1
IN (dBm)
–80 –70 –60 –50 –40 –30 –20 –10 0
0
–20
–40
–60
–80
MIXER
2
IN (dBm)
–80 –70 –60 –50 –40 –30 –20 –10 0–90
ACL “On”
ACL “Off”
Figure 37. First Mixer Third Order
Intercept Performance Figure 38. Second Mixer Third Order
Intercept Performance
MIXER OUTPUT (dBm)
MIXER OUTPUT (dBm)
EXPANDER, E OUT (dBV)
COMPRESSOR LEVEL OUTPUT, LIM OUT (dBV)
MC13109A
26 MOTOROLA RF/IF DEVICE DATA
APPENDIX A – MEASUREMENT OF COMPANDOR ATTACK/DECAY TIME
This measurement definition is based on EIA/CCITT
recommendations.
Compressor Attack Time
For a 12 dB step up at the input, attack time is defined as
the time for the output to settle to 1.5X of the final steady state
value.
Compressor Decay Time
For a 12 dB step down at the input, decay time is defined
as the time for the input to settle to 0.75X of the final steady
state value.
Decay Time
0.75X Final Value
1.5X Final Value
Attack Time
0 mV
0 mV
Input
Output
12 dB
Expander Attack
For a 6.0 dB step up at the input, attack time is defined as
the time for the output to settle to 0.57X of the final steady
state value.
Expander Decay
For a 6.0 dB step down at the input, decay time is defined
as the time for the output to settle to 1.5X of the final steady
state value.
Decay Time
1.5X Final Value
0.57X Final Value
Attack Time
0 mV
Input
Output
6.0 dB
0 mV
MC13109A
27
MOTOROLA RF/IF DEVICE DATA
FB SUFFIX
PLASTIC PACKAGE
CASE 848B–04
(QFP–52)
ISSUE C
OUTLINE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND IS
COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE
PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE.
4. DATUMS –A–, –B– AND –D– TO BE DETERMINED AT DATUM
PLANE –H–.
5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING
PLANE –C–.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER
SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH
AND ARE DETERMINED AT DATUM PLANE –H–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON
THE LOWER RADIUS OR THE FOOT.
DETAIL A
L
39
40 26
27
1
52 14
13
L
–A–
B
V
S
A–B
M
0.20 (0.008) D S
H
A–B0.05 (0.002)
S
A–B
M
0.20 (0.008) D S
C
–D–
B
V
–B–
S
A–B
M
0.20 (0.008) D S
H
A–B0.05 (0.002)
S
A–B
M
0.20 (0.008) D S
C
–H–
0.10 (0.004)
–C– SEATING
PLANE
DATUM
PLANE
M
G
H
E
CM
_
_
DETAIL C
U
_
Q
_
X
WK
T
R
DETAIL C
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.90 10.10 0.390 0.398
B9.90 10.10 0.390 0.398
C2.10 2.45 0.083 0.096
D0.22 0.38 0.009 0.015
E2.00 2.10 0.079 0.083
F0.22 0.33 0.009 0.013
G0.65 BSC 0.026 BSC
H––– 0.25 ––– 0.010
J0.13 0.23 0.005 0.009
K0.65 0.95 0.026 0.037
L7.80 REF 0.307 REF
M5 10 5 10
N0.13 0.17 0.005 0.007
Q0 7 0 7
R0.13 0.30 0.005 0.012
S12.95 13.45 0.510 0.530
T0.13 ––– 0.005 –––
U0 ––– 0 –––
V12.95 13.45 0.510 0.530
W0.35 0.45 0.014 0.018
X1.6 REF 0.063 REF
____
____
__
B
B
DETAIL A –A–, –B–, –D–
JN
D
F
BASE METAL
SECTION B–B
S
A–B
M
0.02 (0.008) D S
C
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Af firmative Action Employer .
MC13109A
28 MOTOROLA RF/IF DEVICE DATA
FTA SUFFIX
PLASTIC PACKAGE
CASE 932–02
(Thin QFP)
ISSUE D
OUTLINE DIMENSIONS
DIM
AMIN MAX MIN MAX
INCHES
7.000 BSC 0.276 BSC
MILLIMETERS
A1 3.500 BSC 0.138 BSC
B7.000 BSC 0.276 BSC
B1 3.500 BSC 0.138 BSC
C1.400 1.600 0.055 0.063
D0.170 0.270 0.007 0.011
E1.350 1.450 0.053 0.057
F0.170 0.230 0.007 0.009
G0.500 BASIC 0.020 BASIC
H0.050 0.150 0.002 0.006
J0.090 0.200 0.004 0.008
K0.500 0.700 0.020 0.028
M12 REF 12 REF
N0.090 0.160 0.004 0.006
P0.250 BASIC 0.010 BASIC
Q1 5 1 5
R0.150 0.250 0.006 0.010
S9.000 BSC 0.354 BSC
S1 4.500 BSC 0.177 BSC
V9.000 BSC 0.354 BSC
V1 4.500 BSC 0.177 BSC
W0.200 REF 0.008 REF
X1.000 REF 0.039 REF
NOTES:
1 DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2 CONTROLLING DIMENSION: MILLIMETER.
3 DATUM PLANE –AB– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4 DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
AT DATUM PLANE –AB–.
5 DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
6 DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7 DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.350 (0.014).
8 MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9 EXACT SHAPE OF EACH CORNER IS OPTIONAL.
__
____
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÉÉÉÉ
ÉÉÉÉ
A
A1
–T–
Z0.200 (0.008) AB T–U
–U–
4X
Z0.200 (0.008) AC T–U
4X
B
B1
1
12
13 24
25
36
37
48
–Z–
S1
S
V
V1
P
AE AE
–T–, –U–, –Z–
DETAIL Y
DETAIL Y
BASE METAL
NJ
F
D
S
T–U
M
0.080 (0.003) Z S
AC
SECTION AE–AE
–AB–
–AC– AD
G0.080 (0.003) AC
M
_
TOP & BOTTOM
Q
_
W
K
X
E
C
H
0.250 (0.010)
GAUGE PLANE
R
9
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MC13109A/D
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