Dual, 10-Bit, 125MSPS
DIGITAL-TO-ANALOG CONVERTER
FEATURES
●125MSPS UPDATE RATE
●
SINGLE SUPPLY: +3.3V or +5V
●HIGH SFDR: 68dB at fOUT = 20MHz
●LOW GLITCH: 2pV-s
●LOW POWER: 310mW at +5V
●INTERNAL REFERENCE
●POWER-DOWN MODE: 23mW
APPLICATIONS
●COMMUNICATIONS:
Base Stations, WLL, WLAN
Baseband I/Q Modulation
●MEDICAL/TEST INSTRUMENTATION
●ARBITRARY WAVEFORM GENERATORS (ARB)
●DIRECT DIGITAL SYNTHESIS (DDS)
DESCRIPTION
The DAC2900 is a monolithic, 10-bit, dual-channel,
high-speed Digital-to-Analog Converter (DAC), and is
optimized to provide high dynamic performance while
dissipating only 310mW on a +5V single supply.
Operating with high update rates of up to 125MSPS, the
DAC2900 offers exceptional dynamic performance, and
enables the generation of very high output frequencies
suitable for
Direct IF
applications. The DAC2900 has
been optimized for communications applications in which
separate I and Q data are processed while maintaining
tight gain and offset matching.
Each DAC has a high-impedance differential-current
output, suitable for single-ended or differential analog
output configurations.
The DAC2900 combines high dynamic performance with
a high throughput rate to create a cost-effective solution
for a wide variety of waveform-synthesis applications:
• Pin compatibility between family members provides
10-bit (DAC2900), 12-bit (DAC2902), and 14-bit
(DAC2904) resolution.
• Pin compatible to the AD9763 dual DAC.
• Gain matching is typically 0.5% of full-scale, and offset
matching is specified at 0.02% max.
• The DAC2900 utilizes an advanced CMOS process; the
segmented architecture minimizes output glitch energy,
and maximizes dynamic performance.
• All digital inputs are +3.3V and +5V logic compatible.
The DAC2900 has an internal reference circuit, and
allows use of an external reference.
• The DAC2900 is available in a TQFP-48 package, and
is specified over the extended industrial temperature
range of –40°C to +85°C.
DAC2900
DAC2900
SBAS166C – JUNE 2001 – REVISED SEPTEMBER 2008
Copyright © 2001-2008, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
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All trademarks are the property of their respective owners.
DAC2900
2SBAS166C
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ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments
recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation pro-
cedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
+VA to AGND ........................................................................ –0.3V to +6V
+VD to DGND........................................................................–0.3V to +6V
AGND to DGND................................................................. –0.3V to +0.3V
+VA to +VD............................................................................... –6V to +6V
CLK, PD to DGND ..................................................... –0.3V to VD + 0.3V
D0-D9 to DGND ......................................................... –0.3V to VD + 0.3V
IOUT, IOUT to AGND ........................................................ –1V to VA + 0.3V
BW, BYP to AGND..................................................... –0.3V to VA + 0.3V
REFIN, FSA to AGND ................................................. –0.3V to VA + 0.3V
INT/EXT to AGND ...................................................... –0.3V to VA + 0.3V
Junction Temperature.................................................................... +150°C
Case Temperature......................................................................... +100°C
Storage Temperature .................................................................... +125°C
SPECIFIED
PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT PACKAGE DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY
DAC2900Y TQFP-48 PFB –40°C to +85°C DAC2900Y DAC2900Y/250 Tape and Reel, 250
""" " "DAC2900Y/1K Tape and Reel, 1000
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com.
PACKAGE/ORDERING INFORMATION(1)
ELECTRICAL CHARACTERISTICS
DAC2900Y
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RESOLUTION 10 Bits
Output Update Rate (fCLOCK)125 MSPS
STATIC ACCURACY(1)
Differential Nonlinearity (DNL) TA = +25°C±0.25 LSB
TMIN to TMAX –1.0 +1.0 LSB
Integral Nonlinearity (INL) TA = +25°C±0.25 LSB
TMIN to TMAX –1.0 +1.0 LSB
DYNAMIC PERFORMANCE
Spurious-Free Dynamic Range (SFDR) To Nyquist
fOUT = 1MHz, fCLOCK = 50MSPS 0dBFS Output 70 80 dBc
–6dBFS Output 75 dBc
–12dBFS Output 70 dBc
fOUT = 1MHz, fCLOCK = 26MSPS 80 dBc
fOUT = 2.18MHz, fCLOCK = 52MSPS 80 dBc
fOUT = 5.24MHz, fCLOCK = 52MSPS 80 dBc
fOUT = 10.4MHz, fCLOCK = 78MSPS 75 dBc
fOUT = 15.7MHz, fCLOCK = 78MSPS 71 dBc
fOUT = 5.04MHz, fCLOCK = 100MSPS 80 dBc
fOUT = 20.2MHz, fCLOCK = 100MSPS 68 dBc
fOUT = 20.1MHz, fCLOCK = 125MSPS 61 dBc
fOUT = 40.2MHz, fCLOCK = 125MSPS 56 dBc
Spurious-Free Dynamic Range within a Window
fOUT = 1.0MHz, fCLOCK = 50MSPS 2MHz Span 86 dBc
fOUT = 5.02MHz, fCLOCK = 50MSPS 10MHz Span 80 dBc
fOUT = 5.03MHz, fCLOCK = 78MSPS 10MHz Span 80 dBc
fOUT = 5.04MHz, fCLOCK = 125MSPS 10MHz Span 80 dBc
Total Harmonic Distortion (THD)
fOUT = 1MHz, fCLOCK = 50MSPS –77 –68 dBc
fOUT = 5.02MHz, fCLOCK = 50MSPS –74 dBc
fOUT = 5.03MHz, fCLOCK = 78MSPS –73 dBc
fOUT = 5.04MHz, fCLOCK = 125MSPS –70 dBc
Multitone Power Ratio 8 Tone with 110kHz Spacing
fOUT = 2.0MHz to 2.99MHz, fCLOCK = 65MSPS 0dBFS Output 80 dBc
At TMIN to TMAX, +VA = +5V, +VD = +3.3V, differential transformer coupled output, and 50Ω doubly-terminated, unless otherwise noted. Independent Gain mode.
PRODUCT EVM ORDERING NUMBER COMMENT
DAC2900 DAC2900-EVM Fully populated evaluation board. See user manual for details.
DAC2900 3
SBAS166C www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
At TMIN to TMAX, +VA = +5V, +VD = +3.3V, differential transformer coupled output, and 50Ω doubly-terminated, unless otherwise noted. Independent Gain mode.
DYNAMIC PERFORMANCE (Cont.)
Signal-to-Noise Ratio (SNR) 0dBFS Output 62 dBc
fOUT = 5.02MHz, fCLOCK = 50MHz
Signal-to-Noise and Distortion (SINAD) 0dBFS Output 61.5 dBc
fOUT = 5.02MHz, fCLOCK = 50MHz
Channel Isolation
fOUT = 1MHz, fCLOCK = 52MSPS 85 dBc
fOUT = 20MHz, fCLOCK = 125MSPS 77 dBc
Output Settling Time(2) to 0.1% 30 ns
Output Rise Time(2) 10% to 90% 2 ns
Output Fall Time(2) 10% to 90% 2 ns
Glitch Impulse 2pV-s
DC ACCURACY
Full-Scale Output Range(3)(FSR) All Bits HIGH, IOUT 220mA
Output Compliance Range –1.0 +1.25 V
Gain Error—Full-Scale With Internal Reference –5 ±1+5%FSR
Gain Error With External Reference –2.5 ±1 +2.5 %FSR
Gain Matching With Internal Reference –2.0 0.5 +2.0 %FSR
Gain Drift With Internal Reference ±50 ppmFSR/°C
Offset Error With Internal Reference –0.02 +0.02 %FSR
Offset Drift With Internal Reference ±0.2 ppmFSR/°C
Power-Supply Rejection, +VA+5V, ±10% –0.2 +0.2 %FSR/V
Power-Supply Rejection, +VD+3.3V, ±10% –0.025 +0.025 %FSR/V
Output Noise IOUT = 20mA, RLOAD = 50Ω50 pA/√Hz
IOUT = 2mA 30 pA/√Hz
Output Resistance 200 kΩ
Output Capacitance IOUT, IOUT to Ground 6 pF
REFERENCE/CONTROL AMP
Reference Voltage +1.18 +1.25 +1.31 V
Reference Voltage Drift ±50 ppmFSR/°C
Reference Output Current 100 nA
Reference Multiplying Bandwidth 0.3 MHz
Input Compliance Range +0.5 +1.25 V
DIGITAL INPUTS
Logic Coding Straight Binary
Logic High Voltage, VIH +VD = +5V 3.5 5 V
Logic Low Voltage, VIL +VD = +5V 0 1.2 V
Logic High Voltage, VIH +VD = 3.3V 2 3 V
Logic Low Voltage, VIL +VD = 3.3V 0 0.8 V
Logic High Current, IIH(4) +VD = 3.3V ±10 µA
Logic Low Current +VD = 3.3V ±10 µA
Input Capacitance 5pF
POWER SUPPLY
Supply Voltages
+VA+3.0 +5 +5.5 V
+VD+3.0 +3.3 +5.5 V
Supply Current
IVA(5) VA = +5V, lOUT = 20mA 58 65 mA
IVA(5) Power-Down Mode 1.7 3 mA
IVD(5) 4.2 7 mA
IVD(6) 17 19.5 mA
Power Dissipation(5) VA = +5V, VD = 3.3V, lOUT = 20mA 310 350 mW
Power Dissipation(6) VA = +5V, VD = 3.3V, lOUT = 20mA 348 390 mW
Power Dissipation(5) VA = +5V, VD = 3.3V, lOUT = 2mA 130 mW
Power Dissipation Power-Down Mode 23 38 mW
Thermal Resistance, TQFP-48
θ
JA 60 °C/W
θ
JC 13 °C/W
TEMPERATURE RANGE
Specified Ambient –40 +85 °C
Operating Ambient –40 +85 °C
NOTES: (1) At output lOUT, while driving a virtual ground. (2) Measured single-ended into 50Ω load. (3) Nominal full-scale output current is 32 x IREF; see Application
Information section for details. (4) Typically 45µA for the PD pin, which has an internal pull-down resistor. (5) Measured at fCLOCK = 25MSPS and fOUT = 1MHz.
(6) Measured at fCLOCK = 100MSPS and fOUT = 40MHz.
DAC2900Y
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DAC2900
4SBAS166C
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PIN DESIGNATOR DESCRIPTION
1-10 D[9:0]_1 Data Port DAC1, Data Bit 9 (MSB) to Bit 0 (LSB).
11-14 NC No Connection
15 DGND Digital Ground
16 +VDDigital Supply, +3.0V to +5.5V
17 WRT1 DAC1 Input Latches Write Signal
18 CLK1 Clock Input DAC1
19 CLK2 Clock Input DAC2
20 WRT2 DAC2 Input Latches Write Signal
21 DGND Digital Ground
22 +VDDigital Supply, +3.0V to +5.5V
23-32 D[9:0]_2 Data Port DAC2, Data Bit 9 (MSB) to Bit 0 (LSB).
33-36 NC No Connection
37 PD
Power-Down Function Control Input;
H
= DAC in power-down mode;
L
= DAC in normal operation (Internal pull-down for default
L
).
38 AGND Analog Ground
39 IOUT2 Current Output DAC2. Full-scale with all bits of data port 2 high.
40 IOUT2 Complementary Current Output DAC2. Full-scale with all bits of data port 2 low.
41 FSA2 Full-Scale Adjust, DAC2. Connect External RSET Resistor
42 GSET Gain-Setting Mode (H = 1 Resistor, L = 2 Resistor)
43 REFIN Internal Reference Voltage output; External Reference Voltage input. Bypass with 0.1µF to AGND for internal reference
operation.
44 FSA1 Full-Scale Adjust, DAC1. Connect External RSET Resistor
45 IOUT1 Complementary Current Output DAC1. Full-scale with all bits of data port 1 low.
46 IOUT1 Current Output DAC1. Full-scale with all bits of data port 1 high.
47 +VAAnalog Supply, +3.0V to +5.5V
48 NC No Connection
PIN DESCRIPTIONS
PIN CONFIGURATION
Top View TQFP-48
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 43 42 41 40 39 38
13 14 15 16 17 18 19 20 21 22 23
37
24
DAC2900
NC
NC
NC
NC
D0_2
D1_2
D2_2
D3_2
D4_2
D5_2
D6_2
D7_2
NC
+V
A
I
OUT
1
I
OUT
1
FSA1
REF
IN
GSET
FSA2
I
OUT
2
I
OUT
2
AGND
PD
NC
NC
DGND
+V
D
WRT1
CLK1
CLK2
WRT2
DGND
+V
D
D9_2 (MSB)
D8_2
D9_1 (MSB)
D8_1
D7_1
D6_1
D5_1
D4_1
D3_1
D2_1
D1_1
D0_1
NC
NC
DAC2900 5
SBAS166C www.ti.com
TIMING DIAGRAM
SYMBOL DESCRIPTION MIN TYP MAX UNITS
tSInput Setup Time 2 ns
tHInput Hold Time 1.5 ns
tLPW, tCPW Latch/Clock Pulsewidth 3.5 4 ns
tCW Delay Rising CLK Edge to 0 tPW – 2ns
Rising WRT Edge
tPD Propagation Delay 1 ns
tSET Settling Time (0.1%) 30 ns
DIGITAL INPUTS AND TIMING
The data input ports of the DAC2900 accept a standard
positive coding with data bit D9 being the most significant
bit (MSB). The converter outputs support a clock rate of up
to 125MSPS. The best performance will typically be achieved
with a symmetrical duty cycle for write and clock; however,
the duty cycle may vary as long as the timing specifications
are met. Also, the setup and hold times may be chosen
within their specified limits.
All digital inputs of the DAC2900 are CMOS-compatible.
The logic thresholds depend on the applied digital supply
voltages, such that they are set to approximately half the
supply voltage: Vth = +VD/2 (±20% tolerance). The DAC2900
is designed to operate with a digital supply (+VD) of +3.0V
to +5.5V.
The two converter channels within the DAC2900 consist of
two independent, 10-bit, parallel data ports. Each DAC
channel is controlled by its own set of write (WRT1, WRT2)
and clock (CLK1, CLK2) inputs. Here, the WRT lines
control the channel input latches and the CLK lines control
the DAC latches. The data is first loaded into the input latch
by a rising edge of the WRT line. This data is presented to
the DAC latch on the following falling edge of the WRT
signal. On the next rising edge of the CLK line, the DAC is
updated with the new data and the analog output signal will
change accordingly. The double latch architecture of the
DAC2900 results in a defined sequence for the WRT and
CLK signals, expressed by parameter tCW. A correct timing
is observed when the rising edge of CLK occurs at the same
time, or before, the rising edge of the WRT signal. This
condition can simply be met by connecting the WRT and
CLK lines together. Note that all specifications were mea-
sured with the WRT and CLK lines connected together.
tPD
tH
tLPW
tCPW
tCW tSET
D[9:0](n) D[9:0](n + 1)
tS
IOUT(n) IOUT(n + 1)
50%
DATA IN
WRT1
WRT2
CLK1
CLK2
IOUT1
IOUT2
DAC2900
6SBAS166C
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TYPICAL CHARACTERISTICS
At TA = +25°C, +VA = +5V, +VD = +3.3V, differential output IOUTFS = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise noted.
TYPICAL DNL
Code
DNL (LSBs)
0.50
0.40
0.30
0.20
0.10
0.00
–0.10
–0.20
–0.30
–0.40
–0.50 400200 600 800 1k0
TYPICAL INL
Code
INL (LSBs)
0.50
0.40
0.30
0.20
0.10
0.00
–0.10
–0.20
–0.30
–0.40
–0.50 400200 600 800 1k0
SFDR vs fOUT AT 26MSPS
fOUT (MHz)
SFDR (dBc)
85
80
75
70
65
60 426810120
–6dBFS
–12dBFS
0dBFS
SFDR vs fOUT AT 52MSPS
fOUT (MHz)
SFDR (dBc)
85
80
75
70
65
60 1051520250
0dBFS
–6dBFS
–12dBFS
SFDR vs fOUT AT 78MSPS
fOUT (MHz)
SFDR (dBc)
85
80
75
70
65
60
55 1051520 3525 300
0dBFS
–12dBFS
–6dBFS
SFDR vs fOUT AT 100MSPS
fOUT (MHz)
SFDR (dBc)
85
80
75
70
65
60
55
50 201510525304535 400
–6dBFS
0dBFS
–12dBFS
DAC2900 7
SBAS166C www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, +VA = +5V, +VD = +3.3V, differential output IOUTFS = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise noted.
SFDR vs TEMPERATURE AT 125MSPS, 0dBFS
Temperature (°C)
SFDR (dBc)
90
85
80
75
70
65
60
55
50 0–20 20 8540 60 80–40
10MHz
20MHz
2MHz
40MHz
SFDR vs fOUT AT 125MSPS
fOUT (MHz)
SFDR (dBc)
85
80
75
70
65
60
55
50 2010 30 6040 500
–12dBFS
0dBFS
–6dBFS
SFDR vs IOUT AND fOUT AT 78MSPS, 0dBFS
fOUT (MHz)
SFDR (dBc)
84
82
80
78
76
74
72
70
68
66
64
62
60 1051525200
20mA
10mA
2mA
5mA
GAIN AND OFFSET DRIFT
Temperature (°C)
Gain Error (% FS)
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
Offset Error (% FS)
0.004
0.003
0.002
0.001
0
–0.001
–0.002
–0.003
–0.004
0–20 20 40 60 80 85–40
Offset Error
Gain Error
IVD vs RATIO AT +VD = 3.3V
Ratio (fOUT/fCLK)
IVD (mA)
25
20
15
10
5
00.100.05 0.15 0.450.20 0.25 0.30 0.35 0.400.00
125MSPS
78MSPS
52MSPS
26MSPS
100MSPS
IVA vs IOUTFS
IOUTFS (mA)
IVA (mA)
60
55
50
45
40
35
30
25
20
15
10 1051520250
DAC2900
8SBAS166C
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, +VA = +5V, +VD = +3.3V, differential output IOUTFS = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise noted.
SINGLE-TONE SFDR
Frequency (MHz)
Magnitude (dBm)
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90 4 8 12 16 200
fCLOCK = 52MSPS
fOUT = 5.23MHz
Amplitude = 0dBFS
SINGLE-TONE SFDR
Frequency (MHz)
Magnitude (dBm)
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90 10 20 30 40 500
fCLOCK = 100MSPS
fOUT = 20.2MHz
Amplitude = 0dBFS
DUAL-TONE SFDR
Frequency (MHz)
Magnitude (dBm)
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90 7.8 15.6 23.4 31.2 39.00
f
CLOCK
= 78MSPS
f
OUT
1 = 9.44MHz
f
OUT
2 = 10.44MHz
Amplitude = 0dBFS
FOUR-TONE SFDR
Frequency (MHz)
Magnitude (dBm)
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90 510
15 20 250
f
CLOCK
= 50MSPS
f
OUT
1 = 6.25MHz
f
OUT
2 = 6.75MHz
f
OUT
3 = 7.25MHz
f
OUT
4 = 7.75MHz
Amplitude = 0dBFS
DAC2900 9
SBAS166C www.ti.com
FIGURE 1. Block Diagram of the DAC2900.
APPLICATION INFORMATION
THEORY OF OPERATION
The architecture of the DAC2900 uses the current steering
technique to enable fast switching and a high update rate.
The core element within the monolithic DAC is an array of
segmented current sources that are designed to deliver a full-
scale output current of up to 20mA, as shown in Figure 1. An
internal decoder addresses the differential current switches
each time the DAC is updated and a corresponding output
current is formed by steering all currents to either output
summing node, IOUT or IOUT. The complementary outputs
deliver a differential output signal, which improves the
dynamic performance through reduction of even-order har-
monics, common-mode signals (noise), and double the peak-
to-peak output signal swing by a factor of two, compared to
single-ended operation.
The segmented architecture results in a significant reduction
of the glitch energy, improves the dynamic performance
(SFDR), and DNL. The current outputs maintain a very high
output impedance of greater than 200kΩ.
The full-scale output current is determined by the ratio of the
internal reference voltage (1.24V) and an external resistor,
RSET. The resulting IREF is internally multiplied by a factor
of 32 to produce an effective DAC output current that can
range from 2mA to 20mA, depending on the value of RSET.
The DAC2900 is split into a digital and an analog portion,
each of which is powered through its own supply pin. The
digital section includes edge-triggered input latches and the
decoder logic, while the analog section consists of the
current source array with its associated switches, and the
reference circuitry.
DAC TRANSFER FUNCTION
The full-scale output current, IOUTFS, is the summation of the
two complementary output currents:
IOUTFS = IOUT + IOUT (1)
The individual output currents depend on the DAC code and
can be expressed as:
IOUT = IOUTFS × (Code/1024) (2)
IOUT = IOUTFS × (1023 – Code)/1024 (3)
where Code is the decimal representation of the DAC data
input word. Additionally, IOUTFS is a function of the refer-
ence current IREF, which is determined by the reference
voltage and the external setting resistor, RSET.
IOUTFS = 32 × IREF = 32 × VREF/RSET (4)
In most cases the complementary outputs will drive resistive
loads or a terminated transformer. A signal voltage will
develop at each output according to:
VOUT = IOUT × RLOAD (5)
VOUT = IOUT × RLOAD (6)
DAC
Latch 1
WRT1
CLK1
CLK2
WRT2
Data Input
Port 2
D[9:0]_2
Data Input
Port 1
D[9:0]_1
l
OUT
1
l
OUT
1
Input
Latch 1
Reference
Control Amplifier FSA2
REF
IN
FSA1
GSET
PD
DAC1
Segmented Switches
Current Sources
DAC2900
l
OUT
2
l
OUT
2
+V
A
+V
D
+V
D
DAC
Latch 2
Input
Latch 2 DAC2
Segmented Switches
Current Sources
AGNDDGNDDGND
DAC2900
10 SBAS166C
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The value of the load resistance is limited by the output
compliance specification of the DAC2900. To maintain
specified linearity performance, the voltage for IOUT and
IOUT should not exceed the maximum allowable compliance
range.
The two single-ended output voltages can be combined to
find the total differential output swing:
VVV Code IR
OUTDIFF OUT OUT OUTFS LOAD
==
×××–(–)2 1023
1024
(7)
ANALOG OUTPUTS
The DAC2900 provides two complementary current out-
puts, IOUT and IOUT. The simplified circuit of the analog
output stage representing the differential topology is shown
in Figure 2. The output impedance of IOUT and IOUT results
from the parallel combination of the differential switches,
along with the current sources and associated parasitic
capacitances.
be adapted to the output of the DAC2900 by selecting a
suitable transformer while maintaining optimum voltage
levels at IOUT and IOUT. Furthermore, using the differential
output configuration in combination with a transformer will
be instrumental for achieving excellent distortion perfor-
mance. Common-mode errors, such as even-order harmon-
ics or noise, can be substantially reduced. This is particularly
the case with high output frequencies.
For those applications requiring the optimum distortion and
noise performance, it is recommended to select a full-scale
output of 20mA. A lower full-scale range down to 2mA may
be considered for applications that require a low power
consumption, but can tolerate a slightly reduced perfor-
mance level.
OUTPUT CONFIGURATIONS
The current outputs of the DAC2900 allow for a variety of
configurations, some of which are illustrated in Table I. As
mentioned previously, utilizing the converter's differential
outputs will yield the best dynamic performance. Such a
differential output circuit may consist of an RF transformer
or a differential amplifier configuration. The transformer
configuration is ideal for most applications with ac coupling,
while op amps will be suitable for a DC-coupled configura-
tion.
The signal voltage swing that may develop at the two
outputs, IOUT and IOUT, is limited by a negative and positive
compliance. The negative limit of –1V is given by the
breakdown voltage of the CMOS process, and exceeding it
will compromise the reliability of the DAC2900, or even
cause permanent damage. With the full-scale output set to
20mA, the positive compliance equals 1.25V, operating with
an analog supply of +VA = 5V. Note that the compliance
range decreases to about 1V for a selected output current of
IOUTFS = 2mA. Care should be taken that the configuration
of the DAC2900 does not exceed the compliance range to
avoid degradation of the distortion performance and integral
linearity.
Best distortion performance is typically achieved with the
maximum full-scale output signal limited to approximately
0.5VPP. This is the case for a 50Ω doubly terminated load
and a 20mA full-scale output current. A variety of loads can
The single-ended configuration may be considered for appli-
cations requiring a unipolar output voltage. Connecting a
resistor from either one of the outputs to ground will convert
the output current into a ground-referenced voltage signal.
To improve on the DC linearity an I-to-V converter can be
used instead. This will result in a negative signal excursion
and, therefore, requires a dual supply amplifier.
DIFFERENTIAL WITH TRANSFORMER
Using an RF transformer provides a convenient way of convert-
ing the differential output signal into a single-ended signal
while achieving excellent dynamic performance (see Figure 3).
The appropriate transformer should be carefully selected based
on the output frequency spectrum and impedance requirements.
The differential transformer configuration has the benefit of
significantly reducing common-mode signals, thus improving
the dynamic performance over a wide range of frequencies.
Furthermore, by selecting a suitable impedance ratio (winding
ratio), the transformer can be used to provide optimum imped-
ance matching while controlling the compliance voltage for the
converter outputs. The model shown, ADTT1-1 (by Mini-
Circuits), has a 1:1 ratio and may be used to interface the
DAC2900 to a 50Ω load. This results in a 25Ω load for each of
the outputs, I
OUT
and I
OUT
. The output signals are AC coupled
and inherently isolated because of its magnetic coupling.
FIGURE 2. Equivalent Analog Output.
I
OUT
I
OUT
DAC2900
R
L
R
L
+V
A
INPUT CODE (D9 - D0) IOUT IOUT
11 1111 1111 20mA 0mA
00 0000 0000 10mA 10mA
00 0000 0000 0mA 20mA
TABLE I. Input Coding versus Analog Output Current.
DAC2900 11
SBAS166C www.ti.com
As shown in Figure 3, the transformer center tap is con-
nected to ground. This forces the voltage swing on IOUT and
IOUT to be centered at 0V. In this case the two resistors, RL,
may be replaced with one, RDIFF, or omitted altogether. This
approach should only be used if all components are close to
each other, and if the VSWR is not important. A complete
power transfer from the DAC output to the load can be
realized, but the output compliance range should be ob-
served. Alternatively, if the center tap is not connected, the
signal swing will be centered at RL × IOUTFS/2. However, in
this case, the two resistors, RL, must be used to enable the
necessary DC-current flow for both outputs.
The OPA680 is configured for a gain of two. Therefore,
operating the DAC2900 with a 20mA full-scale output will
produce a voltage output of ±1V. This requires the amplifier
to operate from a dual power supply ( 5V). The tolerance of
the resistors typically sets the limit for the achievable com-
mon-mode rejection. An improvement can be obtained by
fine tuning resistor R4.
This configuration typically delivers a lower level of AC
performance than the previously discussed transformer solu-
tion because the amplifier introduces another source of
distortion. Suitable amplifiers should be selected based on
their slew-rate, harmonic distortion, and output swing capa-
bilities. High-speed amplifiers like the OPA680 or OPA687
may be considered. The AC performance of this circuit may
be improved by adding a small capacitor, CDIFF, between the
outputs IOUT and IOUT (as shown in Figure 4). This will
introduce a real pole to create a low-pass filter in order to
slew-limit the DAC fast output signal steps, which otherwise
could drive the amplifier into slew-limitations or into an
overload condition; both would cause excessive distortion.
The difference amplifier can easily be modified to add a
level shift for applications requiring the single-ended output
voltage to be unipolar (that is, swing between 0V and +2V).
DUAL TRANSIMPEDANCE OUTPUT CONFIGURATION
The circuit example of Figure 5 shows the signal output
currents connected into the summing junctions of the dual
voltage-feedback op amp OPA2680 that is set up as a
transimpedance stage, or I-to-V converter. With this circuit,
the DAC output will be kept at a virtual ground, minimizing
the effects of output impedance variations, which results in
the best DC linearity (INL). As mentioned previously, care
should be taken not to drive the amplifier into slew-rate
limitations, and produce unwanted distortion.
DIFFERENTIAL CONFIGURATION USING AN OP AMP
If the application requires a DC-coupled output, a difference
amplifier may be considered, as shown in Figure 4. Four
external resistors are needed to configure the voltage-feed-
back op amp OPA680 as a difference amplifier performing
the differential to single-ended conversion. Under the shown
configuration, the DAC2900 generates a differential output
signal of 0.5VPP at the load resistors, RL. The resistor values
shown were selected to result in a symmetric 25Ω loading
for each of the current outputs since the input impedance of
the difference amplifier is in parallel to resistors RL, and
should be considered.
FIGURE 3. Differential Output Configuration Using an RF
Transformer.
FIGURE 5. Dual, Voltage-Feedback Amplifier OPA2680
Forms Differential Transimpedance Amplifier.
FIGURE 4. Difference Amplifier Provides Differential to
Single-Ended Conversion and DC-Coupling.
DAC2900
I
OUT
I
OUT
1:1
ADTT1-1
(Mini-Circuits)
R
L
50Ω
R
L
50Ω
R
S
Optional
R
DIFF
IOUT
IOUT
DAC2900
RL
26.1ΩRL
28.7ΩR4
402Ω
R3
200Ω
R2
402Ω
R1
200Ω
OPA680
COPT +5V
VOUT
–5V
1/2
OPA2680
1/2
OPA2680
DAC2900
–V
OUT
= I
OUT
• R
F
1
–V
OUT
= I
OUT
• R
F
2
R
F1
R
F2
C
F1
C
F2
C
D1
C
D2
I
OUT
I
OUT
50Ω
50Ω–5V
+5V
DAC2900
12 SBAS166C
www.ti.com
The DC gain for this circuit is equal to feedback resistor RF.
At high frequencies, the DAC output impedance (CD1, CD2)
will produce a zero in the noise gain for the OPA2680 that
may cause peaking in the closed-loop frequency response.
CF is added across RF to compensate for this noise gain
peaking. To achieve a flat transimpedance frequency re-
sponse, the pole in each feedback network should be set to:
1
24ππRC GBP
RC
FF FD
=
(8)
with GBP = Gain Bandwidth Product of OPA
which will give a corner frequency f-3dB of approximately:
fGBP
RC
dB FD
–3 2
=π
(9)
The full-scale output voltage is simply defined by the prod-
uct of IOUTFS × RF, and has a negative unipolar excursion. To
improve on the ac performance of this circuit, adjustment of
RF and/or IOUTFS should be considered. Further extensions of
this application example may include adding a differential
filter at the OPA2680 output followed by a transformer, in
order to convert to a single-ended signal.
SINGLE-ENDED CONFIGURATION
Using a single load resistor connected to the one of the DAC
outputs, a simple current-to-voltage conversion can be ac-
complished. The circuit in Figure 6 shows a 50Ω resistor
connected to IOUT, providing the termination of the further
connected 50Ω cable. Therefore, with a nominal output
current of 20mA, the DAC produces a total signal swing of
0V to 0.5V into the 25Ω load.
Different load resistor values may be selected as long as the
output compliance range is not exceeded. Additionally, the
output current, IOUTFS, and the load resistor, may be mutu-
ally adjusted to provide the desired output signal swing and
performance.
INTERNAL REFERENCE OPERATION
The DAC2900 has an on-chip reference circuit, which con-
sists of a 1.24V bandgap reference and two control amplifi-
ers, one for each DAC. The full-scale output current (IOUTFS)
of the DAC2900 is determined by the reference voltage,
VREF, and the value of resistor RSET. IOUTFS can be calcu-
lated by:
IOUTFS = 32 × IREF = 32 × VREF / RSET (10)
As shown in Figure 7, the external resistor RSET connects to
the FSA pin (Full-Scale Adjust). The reference control
amplifier operates as a V-to-I converter producing a refer-
ence current, IREF, which is determined by the ratio of VREF
and RSET (see Equation 10). The full-scale output current,
IOUTFS, results from multiplying IREF by a fixed factor of 32.
Using the internal reference, a 2kΩ resistor value results in
a full-scale output of approximately 20mA. Resistors with a
tolerance of 1% or better should be considered. Selecting
higher values, the output current can be adjusted from 20mA
down to 2mA. Operating the DAC2900 at lower than 20mA
output currents may be desirable for reasons of reducing the
total power consumption, improving the distortion perfor-
mance, or observing the output compliance voltage limita-
tions for a given load condition.
It is recommended to bypass the REFIN pin with a ceramic
chip capacitor of 0.1µF or more. The control amplifier is
internally compensated, and its small signal bandwidth is
approximately 0.3MHz.
FIGURE 6. Driving a Doubly Terminated 50Ω Cable Directly.
FIGURE 7. Internal Reference Configuration.
I
OUT
I
OUT
DAC2900
25Ω
50Ω50Ω
I
OUTFS
= 20mA V
OUT
= 0V to +0.5V
DAC2900
+1.24V Ref.
R
SET
2kΩ0.1µF
FSA
+5V
+V
A
REF
IN
Current
Sources
I
REF
= V
REF
R
SET
Ref
Control
Amp
DAC2900 13
SBAS166C www.ti.com
GAIN SETTING OPTIONS
The full-scale output current on the DAC2900 can be set two
ways: either for each of the two DAC channels independently
or for both channels simultaneously. For the independent gain
set mode, the GSET pin (pin 42) must be LOW (that is,
connected to AGND). In this mode, two external resistors are
required—one RSET connected to the FSA1 pin (pin 44) and
the other to the FSA2 pin (pin 41). In this configuration, the
user has the flexibility to set and adjust the full-scale output
current for each DAC independently, allowing for the com-
pensation of possible gain mismatches elsewhere within the
transmit signal path.
Alternatively, bringing the GSET pin HIGH (that is, con-
nected to +VA), the DAC2900 will switch into the simulta-
neous gain set mode. Now the full-scale output current of both
DAC channels is determined by only one external RSET
resistor connected to the FSA1 pin, while any present resistor
at the FSA2 pin must be removed. The formula for deriving
the correct RSET remains unchanged (for example, RSET = 2kΩ
will result in a 20mA output for both DACs).
EXTERNAL REFERENCE OPERATION
The internal reference can be disabled by simply applying an
external reference voltage into the REFIN pin, which in this
case functions as an input, as shown in Figure 8. The use of
an external reference may be considered for applications that
require higher accuracy and drift performance, or to add the
ability of dynamic gain control.
While a 0.1µF capacitor is recommended to be used with the
internal reference, it is optional for the external reference
operation. The reference input, REFIN, has a high input
impedance (1MΩ) and can easily be driven by various
sources. Note that the voltage range of the external reference
should stay within the compliance range of the reference
input (0.1V to 1.25V).
POWER-DOWN MODE
The DAC2900 features a power-down function which can
be used to reduce the total supply current to less than 6mA
over the specified supply range of 3.0V to 5.5V. Applying
a logic HIGH to the PD pin will initiate the power-down
mode, while a logic LOW enables normal operation. When
left unconnected, an internal active pull-down circuit will
enable the normal operation of the converter.
FIGURE 8. External Reference Configuration.
R
SET
External
Reference
I
REF
= V
REF
R
SET
DAC2900
+1.24V Ref.
FSA
+5V
+V
A
REF
IN
Current
Sources
Ref
Control
Amp
DAC2900
14 SBAS166C
www.ti.com
GROUNDING, DECOUPLING AND
LAYOUT INFORMATION
Proper grounding and bypassing, short lead length, and the use
of ground planes are particularly important for high-frequency
designs. Multilayer PCBs are recommended for best perfor-
mance since they offer distinct advantages such as minimiza-
tion of ground impedance, separation of signal layers by
ground layers, etc.
The DAC2900 uses separate pins for its analog and digital
supply and ground connections. The placement of the decou-
pling capacitor should be such that the analog supply (+VA)
is bypassed to the analog ground (AGND), and the digital
supply bypassed to the digital ground (DGND). In most
cases 0.1µF ceramic chip capacitors at each supply pin are
adequate to provide a low impedance decoupling path. Keep
in mind that their effectiveness largely depends on the
proximity to the individual supply and ground pins. There-
fore they should be located as close as physically possible to
those device leads. Whenever possible, the capacitors should
be located immediately under each pair of supply/ground
pins on the reverse side of the pc board. This layout ap-
proach will minimize the parasitic inductance of component
leads and PCB runs.
Further supply decoupling with surface-mount tantalum ca-
pacitors (1µF to 4.7µF) may be added as needed in proxim-
ity of the converter.
Low noise is required for all supply and ground connections
to the DAC2900. It is recommended to use a multilayer PCB
utilizing separate power and ground planes. Mixed signal
designs require particular attention to the routing of the
different supply currents and signal traces. Generally, analog
supply and ground planes should only extend into analog
signal areas, such as the DAC output signal and the refer-
ence signal. Digital supply and ground planes must be
confined to areas covering digital circuitry, including the
digital input lines connecting to the converter, as well as the
clock signal. The analog and digital ground planes should be
joined together at one point underneath the DAC. This can
be realized with a short track of approximately 1/8 inch
(3mm).
The power to the DAC2900 should be provided through the
use of wide pcb runs or planes. Wide runs will present a
lower trace impedance, further optimizing the supply decou-
pling. The analog and digital supplies for the converter
should only be connected together at the supply connector of
the pc board. In the case of only one supply voltage being
available to power the DAC, ferrite beads along with bypass
capacitors may be used to create an LC filter. This will
generate a low-noise analog supply voltage, which can then
be connected to the +VA supply pin of the DAC2900.
While designing the layout, it is important to keep the analog
signal traces separated from any digital line, in order to
prevent noise coupling onto the analog signal path.
DAC2900 15
SBAS166C www.ti.com
DATE REVISION PAGE SECTION DESCRIPTION
1–Updated front page to standard format.
2 Pkg/Ordering Info Table Updated Package/Ordering Information table.
3 Electrical Characteristics Changed values for Supply Current and Power Dissipation.
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
9/08 C
PACKAGE OPTION ADDENDUM
www.ti.com 21-May-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
DAC2900Y/1K ACTIVE TQFP PFB 48 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC2900Y/1KG4 ACTIVE TQFP PFB 48 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC2900Y/250 ACTIVE TQFP PFB 48 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC2900Y/250G4 ACTIVE TQFP PFB 48 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DAC2900Y/1K TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
DAC2900Y/250 TQFP PFB 48 250 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DAC2900Y/1K TQFP PFB 48 1000 367.0 367.0 38.0
DAC2900Y/250 TQFP PFB 48 250 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK
4073176/B 10/96
Gage Plane
0,13 NOM
0,25
0,45
0,75
Seating Plane
0,05 MIN
0,17
0,27
24
25
13
12
SQ
36
37
7,20
6,80
48
1
5,50 TYP
SQ
8,80
9,20
1,05
0,95
1,20 MAX 0,08
0,50 M
0,08
0°–7°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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