Rev. 1.1 6/18 Copyright © 2018 by Silicon Laborato ries Si598/Si599
Si598/Si599
10–810 MHZ I2C PROGRAMMABLE XO/VCXO
Features
Applications
Description
The Si598 XO/Si599 VCXO utilizes Silicon Laboratories' advanced DSPLL®
circuitry to provide a low-jitter clock at any frequency. They are user-
programmable to any output frequency from 10 to 810 MHz with 28 parts per
trillion (PPT) resolution. The device is programmed via a 2-pin I
2
C compatible
serial interface. The wide frequency range and ultra-fine programming resolution
make these devices ideal for applications that require in-circuit dynamic frequency
adjustments or multi-rate operation with non-integer related rates. Using an
integrated crystal, these devices provide stable low jitter frequency synthesis and
replace multiple XOs, clock generators, and DAC controlled VCXOs.
Functional Block Diagram
I2C programmable output
frequencies from 10 to 810 MHz
0.5 ps RMS phase jitter
Superior power supply rejection:
0.3–0.4 ps additive jitter
Available LVPECL, CMOS, LVDS,
and CML outputs
1.8, 2.5, or 3.3 V supply
Pin- and register-compatible with
Si570/571
Programmable with 28 parts per
trillion frequency resolution
Integrated crystal provides stability
and low phase noise
Frequency changes up to
±3500 ppm are glitchless
–40 to 85 °C operation
Industry-standard 5x7 mm package
SONET / SDH / xDSL
Ethernet / Fibre Channel
3G SDI / HD SDI
Multi-rate PLLs
Multi-rate reference clocks
Frequency margining
Digital PLLs
CPU / FPGA FIFO control
Adaptive synchronization
Agile RF local oscillators
VDD
Fixed
Frequency
Oscillator
CLK+
CLK–
OE
GND
Power Supply Filtering
I2C Interface
SDA SCL
ADC
Vc
(Si599)
Any Frequency
DSPLL®
10 to 810 MHz
Clock Synthesis
Ordering Information:
See page 21.
Pin Assignments:
See page 20.
(Top View)
Si5602
Si598
Si599
1
2
3
6
5
4
NC
GND
OE
VDD
CLK+
CLK–
SDA
SCL
8
7
1
2
3
6
5
4
VC
GND
OE
VDD
CLK+
CLK–
SDA
SCL
8
7
Si598/Si599
Rev. 1.1 2
TABLE OF CONTENTS
Section Page
1. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.1. Programming a New Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.2. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4. Serial Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5. Si598 (XO) Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
6. Si599 (VCXO) Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
7. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
8. Si59x Mark Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
9. Outline Diagram and Suggested Pad Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
10. 8-Pin PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Si598/Si599
Rev. 1.1 3
1. Detailed Block Diagrams
Figure 1. Si598 Detailed Block Diagram
Figure 2. Si599 Detailed Block Diagram
RFREQ
Control
Interface
NVM
÷HS_DIV ÷N1DCO CLKOUT+
CLKOUT–
VDD GND
fXTAL
fosc
SDA
OE
SCL
RAM
M
RFREQ
Control
Interface
NVM
÷HS_DIV ÷N1
+DCO
VCADC
VC
CLKOUT+
CLKOUT–
VDD GND
fXTAL
fosc
SDA
OE
SCL
RAM
ADC M
Si598/Si599
4 Rev. 1.1
2. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Symbol Test Condition Min Typ Max Units
Supply Voltage1VDD
3.3 V option 2.97 3.3 3.63 V
2.5 V option 2.25 2.5 2.75 V
1.8 V option 1.71 1.8 1.89 V
Supply Current IDD
Output enabled
LVPECL
CML
LVDS
CMOS
120
108
99
90
130
120
110
100
mA
mA
mA
mA
Tristate mode 60 75 mA
Output Enable (OE)2,
Serial Data (SDA),
Serial Clock (SCL)
VIH 0.75 x VDD ——V
VIL ——0.5
V
Operating Temperature Range TA–40 85 ºC
Notes:
1. Selectable parameter specified by part number. See Section 7. Ordering Information on page 21 for further details.
2. OE pin includes a 17 k pullup resistor to VDD for OE Active High Option. OE pin includes 17 kpull down for OE
Active Low. See Section “7.Ordering Information”.
Table 2. VC Control Voltage Input (Si599)
(Typical values TA = 25 ºC, VDD = 3.3 V, min/max limits VDD = 1.8 ±5%, 2.5 or 3.3 V ±10%, TA = –40 to 85 ºC unless otherwise
noted)
Parameter Symbol Test Condition Min Typ Max Units
Control Voltage Tuning Slope1,2,3 KV10 to 90% of VDD
45
95
125
185
380
ppm/V
ppm/V
ppm/V
ppm/V
ppm/V
Control Voltage Linearity4LVC BSL –5 ±1 +5 %
Incremental –10 ±5 +10 %
Modulation Bandwidth BW 9.3 10.0 10.7 kHz
VC Input Impedance ZVC 500 k
VC Input Capacitance CVC —50—pF
Nominal Control Voltage VCNOM @ fO—V
DD/2 V
Control Voltage Tuning Range VC0—V
DD V
Notes:
1. Positive slope; selectable option by part number. See 7. Ordering Information on page 21.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. KV variation is ±10% of typical values.
4. BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope
determined with VC ranging from 10 to 90% of VDD.
Si598/Si599
Rev. 1.1 5
Table 3. CLK± Output Frequency Characteristics
(Typical values TA = 25 ºC, VDD= 3.3 V, min/max limits VDD = 1.8 ±5%, 2.5 or 3.3 V ±10%, TA = –40 to 85 ºC unless otherwise
noted)
Parameter Symbol Test Condition Min Typ Max Units
Programmable Frequency
Range1,2,3 fO
LVPECL/LVDS/CML 10 810 MHz
CMOS 10 160 MHz
Total Stability (Si598)1,2,4,5
Temp stability = ±20 ppm ±30 ppm
Temp stability = ±25 ppm ±50 ppm
Temp stability = ±50 ppm ±100 ppm
Temperature Stability (Si599)1,5 TA= –40 to +85 ºC –20
–50
+20
+50 ppm
Absolute Pull Range1,5 (Si599) APR ±10 ±370 ppm
Powerup Time6tOSC ——10ms
Notes:
1. See Section 7. Ordering Information on page 21 for further details.
2. Specified at time of order by part number. Three frequency grades are available:
Grade A covers 10 to 810 MHz.
Grade B covers 10 to 280 MHz.
Grade C covers 10 to 160 MHz.
3. Nominal output frequency set by VCNOM =1/2xV
DD.
4. Includes initial accuracy, temperature drift, shock, vibration, power supply and load drift. ±100 ppm and ±50 ppm
options include 15 years aging at 70 °C. ±30 ppm option includes 10 years aging at 40 °C.
5. Selectable parameter specified by part number. See 7. Ordering Information on page 21.
6. Time from power up or tristate mode to fO.
Si598/Si599
6 Rev. 1.1
Table 4. CLK± Output Levels and Symmetry
(Typical values TA = 25 ºC, VDD = 3.3 V, min/max limits VDD = 1.8 ±5%, 2.5 or 3.3 V ±10%, TA = –40 to 85 ºC unless otherwise
noted)
Parameter Symbol Test Condition Min Typ Max Units
LVPECL Output Option1
VOmid-level VDD – 1.42 VDD – 1.25 V
VOD swing (diff) 1.1 1.9 VPP
VSE swing (single-ended) 0.55 0.95 VPP
LVDS Output Option2
VOmid-level 1.125 1.20 1.275 V
VOD swing (diff) 0.5 0.7 0.9 VPP
CML Output Option2
VO
2.5/3.3 V option mid-level VDD – 1.30 V
1.8 V option mid-level VDD – 0.36 V
VOD
2.5/3.3 V option swing (diff) 1.10 1.50 1.90 VPP
1.8 V option swing (diff) 0.35 0.425 0.50 VPP
CMOS Output Option3VOH IOH =32mA 0.8 x VDD VDD V
VOL IOL =32mA 0.4 V
Rise/Fall Time (20/80 %) tR, tF
LVPECL/LVDS/CML 350 ps
CMOS with CL=15pF 1 ns
Symmetry (duty cycle) SYM
LVPECL: VDD – 1.3 V (diff)
LVDS: 1.25 V (diff)
CMOS: VDD/2
48 52 %
Notes:
1. 50 to VDD – 2.0 V.
2. Rterm =100 (differential).
3. CL= 15 pF sinking or sourcing 12 mA for VDD = 3.3 V, 6 mA for VDD = 2.5 V, 3 mA for VDD =1.8V.
Si598/Si599
Rev. 1.1 7
Table 5. CLK± Output Phase Jitter (Si598)
(Typical values TA = 25 ºC, VDD = 3.3 V, min/max limits VDD = 1.8 ±5%, 2.5 or 3.3 V ±10%, TA = –40 to 85 ºC unless otherwise
noted)
Parameter Symbol Test Condition Min Typ Max Units
Phase Jitter (RMS Random)
12 kHz to 20 MHz Integration Bandwidth
φJ-RANDOM
LVPECL/LVDS/CML1 —0.5—ps
CMOS 3.3 V2—0.6—ps
Phase Jitter (RMS Random)
1.875 to 20 MHz Integration Bandwidth
LVPECL/LVDS/CML1 —0.3—ps
CMOS 3.3 V2 —0.5—ps
Phase Jitter (RMS)
12 kHz to 20 MHz Integration Bandwidth
φJ
LVPECL/LVDS/CML1—0.5 1 ps
CMOS 3.3 V2—0.6 1 ps
Phase Jitter (RMS)
1.875 to 20 MHz Integration Bandwidth
LVPECL/LVDS/CML1—0.5—ps
CMOS 3.3 V2—0.5—ps
Notes:
1. 50 to 810 MHz, 3.3 V/2.5 V only.
2. 50 to 160 MHz, single-ended CMOS output phase jitter measured using 33 series termination into 50 phase noise
test equipment. 3.3 V supply voltage option only.
Table 6. CLK± Output Phase Jitter (Si599)
(Typical values TA = 25 ºC, VDD = 3.3 V, min/max limits VDD = 1.8 ±5%, 2.5 or 3.3 V ±10%, TA = –40 to 85 ºC unless otherwise
noted)
Parameter Symbol Test Condition Min Typ Max Units
Phase Jitter (RMS)1,2
for FOUT of 50 MHz < FOUT
810 MHz
JKv = 45 ppm/V
12 kHz to 20 MHz 0.5 ps
Kv = 95 ppm/V
12 kHz to 20 MHz 0.5 ps
Kv = 125 ppm/V
12 kHz to 20 MHz 0.5 ps
Kv = 185 ppm/V
12 kHz to 20 MHz 0.5 ps
Kv = 380 ppm/V
12 kHz to 20 MHz 0.7 ps
Notes:
1. Differential Modes: LVPECL/LVDS/CML.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
Si598/Si599
8 Rev. 1.1
Table 7. CLK± Output Period Jitter
(Typical values TA = 25 ºC, VDD = 3.3 V unless otherwise noted)
Parameter Symbol Test Condition Min Typ Max Units
Period Jitter* JPER
RMS 3 ps
Peak-to-Peak 35 ps
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles.
Table 8. CLK± Output Phase Noise (Typical, Si599)
(Typical values TA = 25 ºC, VDD =3.3V)
Offset Frequency 74.25 MHz
185 ppm/V
LVPECL
148.5 MHz
185 ppm/V
LVPECL
155.52 MHz
95 ppm/V
LVPECL
Units
100 Hz
1kHz
10 kHz
100 kHz
1MHz
10 MHz
20 MHz
–77
–101
–121
–134
–149
–151
–150
–68
–95
–116
–128
–144
–147
–148
–77
–101
–119
–127
–144
–147
–148
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Table 9. Power Supply Noise Rejection
(Typical values TA = 25 ºC, VDD =3.3V)
Parameter Symbol Test Condition Min Typ Max Units
RMS Additive Jitter due to Power Supply Noise*
φPSRR
100 kHz 0.32 ps
300 kHz 0.36 ps
700 kHz 0.36 ps
1MHz 0.32 ps
*Note: Measured with 100 mVp-p sinusoid applied to power supply pin. VDD = 3.3 V, LVPECL.
Table 10. Spurious Performance
(Typical values TA = 25 ºC, VDD =3.3V)
Parameter Symbol Test Condition Min Typ Max Units
Spurious Free Dynamic Range SFDR
LVPECL, LVDS, CML1—75dB
LVPECL, LVDS, CML2—64dB
CMOS1—77dB
Notes:
1. 10 to 160 MHz.
2. 10 to 810 MHz.
Si598/Si599
Rev. 1.1 9
Table 11. Environmental Compliance
The Si598/599 meets the following qualification test requirements.
Parameter Conditions/Test Method
Mechanical Shock MIL-STD-883, Method 2002
Mechanical Vibration MIL-STD-883, Method 2007
Solderability MIL-STD-883, Method 2003
Gross & Fine Leak MIL-STD-883, Method 1014
Resistance to Solder Heat MIL-STD-883, Method 2036
Moisture Sensitivity Level J-STD-020, MSL1
Contact Pads Gold over Nickel
Table 12. Programming Constraints and Timing
(Typical values TA = 25 ºC, VDD = 3.3 V, min/max limits VDD = 1.8 ±5%, 2.5 or 3.3 V ±10%, TA = –40 to 85 ºC unless
otherwise noted)
Parameter Symbol Test Condition Min Typ Max Unit
Output Frequency Range CKOF10 810 MHz
Frequency Reprogramming
Resolution
MRES —28— ppt
Internal Oscillator Frequency fOSC 4850 5670 MHz
Internal Crystal Frequency
Accuracy
fXTAL Maximum variation is
±2000 ppm
39.17 MHz
Delta Frequency for
Continuous Output
From center frequency –3500 +3500 ppm
Unfreeze to NewFreq
Timeout*
10 ms
Settling Time for Small
Frequency Change
<±3500 ppm from
center frequency
——100µs
Settling Time for Large
Frequency Change
>±3500 ppm from
center frequency after
setting NewFreq bit
——10 ms
*Note: Applies when using large frequency change procedure outlined in section “3.1.2.Reconfiguring the Output Clock for
Large Changes in Output Frequency”.
Si598/Si599
10 Rev. 1.1
Table 13. Thermal Characteristics
(Typical values TA = 25 ºC, VDD =3.3V)
Parameter Symbol Test Condition Min Typ Max Unit
Thermal Resistance Junction to Ambient JA Still Air 84.6 °C/W
Thermal Resistance Junction to Case JC Still Air 38.8 °C/W
Ambient Temperature TA–40 85 °C
Junction Temperature TJ——125°C
Table 14. Absolute Maximum Ratings
Parameter Symbol Rating Units
Supply Voltage, 1.8 V Option VDD –0.5 to +1.9 V
Supply Voltage, 2.5/3.3 V Option VDD –0.5 to +3.8 V
Input Voltage VI–0.5 to VDD + 0.3 V
Storage Temperature TS–55 to +125 ºC
ESD Sensitivity (HBM, per JESD22-A114) ESD 2000 V
Soldering Temperature (lead-free profile) TPEAK 260 ºC
Soldering Temperature Time @ TPEAK (lead-free profile) tP20–40 seconds
Notes:
1. Stresses beyond the absolute maximum ratings may cause permanent damage to the device. Functional operation or
specification compliance is not implied at these conditions.
2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at
www.silabs.com/VCXO for further information, including soldering profiles.
Si598/Si599
11 Rev. 1.1
3. Functional Description
The Si598 XO and the Si599 VCXO are low-jitter
oscillators ideally suited for applications requiring
programmable frequencies. The Si59x can be
programmed to generate any output clock in the range
of 10 to 810 MHz with frequency resolution of 30 parts
per trillion. Output jitter performance exceeds the strict
requirements of high-speed communication systems
including OC-48/STM-16, 3G SDI, and Gigabit
Ethernet.
The Si59x consists of a digitally-controlled oscillator
(DCO) based on Silicon Laboratories' third-generation
DSPLL technology, which is driven by an internal fixed-
frequency crystal reference.
The device's default output frequency is set at the
factory and can be reprogrammed through the two-wire
I2C serial port. Once the device is powered down, it will
return to its factory-set default output frequency.
The Si599 has a pullable output frequency using the
voltage control input pin. This makes the Si599 an ideal
choice for high-performance, low-jitter, phase-locked
loops. The Si598 is digitally pullable using the I2C
interface and is ideal for digital PLL applications.
3.1. Programming a New Output Frequency
The output frequency (fout) is determined by
programming the DCO frequency (fDCO) and the
device's output dividers (HS_DIV, N1). The output
frequency is calculated using the following equation:
The DCO frequency is adjustable in the range of 4.85 to
5.67 GHz by setting the high-resolution 38-bit fractional
multiplier (RFREQ). The DCO frequency is the product
of the internal fixed-frequency crystal (fXTAL) and
RFREQ.
The 38-bit resolution of RFREQ allows the DCO
frequency to have a programmable frequency resolution
of 28 ppt.
As shown in Figure 3, the device allows reprogramming
of the DCO frequency up to ±3500 ppm from the center
frequency configuration without interruption to the
output clock. Changes greater than the ±3500 ppm
window will cause the device to recalibrate its internal
tuning circuitry, forcing the output clock to momentarily
stop and start at any arbitrary point during a clock cycle.
This re-calibration process establishes a new center
frequency and can take up to 10 ms. Circuitry receiving
a clock from the Si59x device that is sensitive to glitches
or runt pulses may have to be reset once the
recalibration process is complete.
3.1.1. Reconfiguring the Output Clock for a Small
Change in Frequency
For output changes less than ±3500 ppm from the
center frequency configuration, the DCO frequency is
the only value that needs reprogramming. Since
fDCO =f
XTAL x RFREQ, and that fXTAL is fixed, changing
the DCO frequency is as simple as reconfiguring the
RFREQ value as outlined below:
1. Using the serial port, read the current RFREQ value
(registers 0x08–0x12).
2. Calculate the new value of RFREQ given the change
in frequency.
3. Using the serial port, write the new RFREQ value
(registers 0x08—0x12). Multi-byte changes to
RFREQ can freeze the DCO to avoid unintended
RFREQ values.
Example:
An Si598 generating a 148.35 MHz clock must be
reconfigured "on-the-fly" to generate a 148.5 MHz clock.
This represents a change of +1011.122 ppm, which is
well within the ±3500 ppm window.
Figure 3. DCO Frequency Range
fout
fDCO
Output Dividers
-----------------------------------------fXTAL RFREQ
HSDIV N1
-------------------------------------------
==
RFREQnew RFREQcurrent
fout_new
fout_current
-------------------------
=
4.85 GHz 5.67 GH z
Center
Frequency
Configuration
-3500 ppm +3500 ppm
small frequency changes can be made
without interruption to the output clock
Si598/Si599
Rev. 1.1 12
A typical frequency configuration for this example:
RFREQcurrent = 0x8858199E9
Fout_current =148.35MHz
Fout_new =148.50MHz
Calculate RFREQnew to change the output frequency
from 148.35 to 148.5 MHz:
Note that performing calculations with RFREQ requires
a minimum of 38-bit arithmetic precision.
Relatively small changes in output frequency may
require writing more than one RFREQ register. Such
multi-register RFREQ writes can impact the output clock
frequency on a register-by-register basis during
updating.
Interim changes to the output clock during RFREQ
writes can be prevented by using the following
procedure:
1. Freeze the "M" value (Set Register 135 bit 5 = 1)
2. Write the new frequency configuration (RFREQ)
3. Unfreeze the "M" value (Set Register 135 bit 5 = 0)
3.1.2. Reconfiguring the Output Clock for Large
Changes in Output Frequency
For output frequency changes outside of ±3500 ppm
from the center frequency, it is likely that both the DCO
frequency and the output dividers need to be
reprogrammed. Note that changing the DCO frequency
outside of the ±3500 ppm window will cause the output
to momentarily stop and restart at any arbitrary point in
a clock cycle. Devices sensitive to glitches or runt
pulses may have to be reset once reconfiguration is
complete.
The process for reconfiguring the output frequency
outside of a ±3500 ppm window is shown below:
1. Using the serial port, read the current values for
RFREQ, HSDIV, and N1.
2. Calculate fXTAL for the device. Note that because of
slight variations of the internal crystal frequency from
one device to another, each device may have a
different RFREQ value or possibly even different
HSDIV or N1 values to maintain the same output
frequency. It is necessary to calculate fXTAL for each
device.
Once fXTAL has been determined, new values for
RFREQ, HSDIV, and N1 are calculated to generate a
new output frequency (fout_new). New values can be
calculated manually or with the Si59x-EVB software,
which provides a user-friendly application to help find
the optimum values.
The first step in manually calculating the frequency
configuration is to determine new frequency divider
values (HSDIV, N1). Given the desired output frequency
(fout_new), find the frequency divider values that will
keep the DCO oscillation frequency in the range of 4.85
to 5.67 GHz.
Valid values of HSDIV are 9 or 11. N1 can be selected
as 1 or any even number up to 128 (i.e., 1, 2, 4, 6, 8, 10
… 128). To help minimize the device's power
consumption, the divider values should be selected to
keep the DCO's oscillation frequency as low as
possible. The lowest value of N1 with the highest value
of HS_DIV also results in the best power savings.
Once HS_DIV and N1 have been determined, the next
step is to calculate the reference frequency multiplier
(RFREQ).
RFREQ is programmable as a 38-bit binary fractional
frequency multiplier with the first 10 most significant bits
(MSBs) representing the integer portion of the multiplier
and the 28 least significant bits (LSBs) representing the
fractional portion.
Before entering a fractional number into the RFREQ
register, it must be converted to a 38-bit integer using a
bitwise left shift operation by 28 bits, which effectively
multiplies RFREQ by 228.
Example:
RFREQ = 136.3441409d
Multiply RFREQ by 228 = 36599601635.42d
Discard the fractional portion = 36599601635d
Convert to hexadecimal = 0x8858199E9
Once the new values for RFREQ, HSDIV, and N1 are
determined, they can be written directly into the device
from the serial port using the following procedure:
1. Freeze the DCO (bit 4 of Register 137)
2. Write the new frequency configuration (RFREQ,
HS_DIV, N1)
RFREQnew 0x8858199E9 148.50 MHz
148.35 MHz
--------------------------------
0x887B6473C
=
=
fXTAL
Fout HSDIVN1
RFREQ
---------------------------------------------------
=
fDCO_new fout_new HSDIVnew
N1new
=
RFREQnew
fDCO_new
fXTAL
-----------------------
=
Si598/Si599
13 Rev. 1.1
3. Unfreeze the DCO and assert the NewFreq bit (bit 6
of Register 135) within the maximum Unfreeze to
NewFreq Timeout in Table 12, “Programming
Constraints and Timing,” on page 9.
The process of freezing and unfreezing the DCO will
cause the output clock to momentarily stop and start at
any arbitrary point during a clock cycle. This process
can take up to 10 ms. Circuitry that is sensitive to
glitches or runt pulses may have to be reset after the
new frequency configuration is written.
Example:
An Si598 generating 156.25 MHz must be re-configured
to generate a 161.1328125 MHz clock (156.25 MHz x
66/64). This frequency change is greater than
±3500 ppm.
fout =156.25MHz
Read the current values for RFREQ, HS_DIV, N1:
RFREQcurrent = 0x7FA611E85 = 34265439877d,
34265439877d / 228 = 127.64871074631810d
HS_DIV = 4
N1 = 8
Calculate fXTAL, fDCO_current
Given fout_new = 161.1328125 MHz, choose output
dividers that will keep fDCO within the range of 4.85 to
5.67 GHz. In this case, keeping the same output
dividers will still keep fDCO within its range limits:
Calculate the new value of RFREQ given the new DCO
frequency:
3.2. I2C Interface
The control interface to the Si598 is an I2C-compatible
2-wire bus for bidirectional communication. The bus
consists of a bidirectional serial data line (SDA) and a
serial clock input (SCL). Both lines must be connected
to the positive supply via an external pullup.Fast mode
operation is supported for transfer rates up to 400 kbps
as specified in the I2C-Bus Specification standard.
Figure 4 shows the command format for both read and
write access. Data is always sent MSB. Data length is 1
byte. Read and write commands support 1 or more data
bytes as illustrated. The master must send a Not
Acknowledge and a Stop after the last read data byte to
terminate the read command. The timing specifications
and timing diagram for the I2C bus can be found in the
I2C-Bus Specification standard (fast mode operation).
The device I2C address is specified in the part number.
Figure 4. I2C Command Format
fDCO_current fout HSDVN15.000000000 GHz==
fXTAL
fDCO_current
RFREQcurrent
---------------------------------------39.17 MHz==
fDCO_new fout_new HSDVnew
N1new
161.1328125 MHz 485.156250000 GHz
=
==
RFREQnew
fDCO_new
fXTAL
-----------------------131.637733d 0x83A342779===
From master to slave From slave to master
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH).
Required after the last data byte to signal the end of the read comand to the slave.
S – START condition
P – STOP condition
P
A
A
Byte AddressA
S Slave Address 0 Data
Write Command
(Optional 2nd data byte and acknowledge illustrated)
A
Byte AddressAS Slave Address 0 SSlave Address 1 A
AData
A
Data Data NP
Read Command
(Optional data byte and acknowledge before the last data byte and not acknowledge illustrated)
Si598/Si599
14 Rev. 1.1
4. Serial Port Registers
Note: Registers not documented are reserved. Values within reserved registers and reserved bits must not be changed.
Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
7 High Speed/
N1 Dividers
HS_DIV[2:0] N1[6:2]
8 Reference
Frequency
N1[1:0] RFREQ[37:32]
9 Reference
Frequency
RFREQ[31:24]
10 Reference
Frequency
RFREQ[23:16]
11 Reference
Frequency
RFREQ[15:8]
12 Reference
Frequency
RFREQ[7:0]
135 NewFreq/
Freeze/
Memory
Control
Reserved NewFreq Freeze M Freeze
VCADC
Reserved RECALL
137 Freeze DCO Reserved Freeze
DCO
Reserved
Si598/Si599
Rev. 1.1 15
Register 7. High Speed/N1 Dividers
BitD7D6D5D4D3D2D1D0
Name HS_DIV[2:0] N1[6:2]
Type R/W R/W
Bit Name Function
7:5 HS_DIV[2:0] DCO High Speed Divider.
Sets value for high speed divider that takes the DCO output fOSC as its clock input.
000 = 4
001 = 5
010 = 6
011 = 7
100 = Not used.
101 = 9
110 = Not used.
111 = 11
4:0 N1[6:2] CLKOUT Output Divider.
Sets value for CLKOUT output divider. Allowed values are [1] and [2, 4, 6, ..., 27]. Illegal
odd divider values will be rounded up to the nearest even value. The value for the N1
register can be calculated by taking the divider ratio minus one. For example, to divide by
10, write 0001001 (9 decimal) to the N1 registers.
0000000 = 1
1111111 = 27
Register 8. Refe ren c e Fre que n cy
BitD7D6D5D4D3D2D1D0
Name N1[1:0] RFREQ[37:32]
Type R/W R/W
Bit Name Function
7:6 N1[1:0] CLKOUT Output Divider.
Sets value for CLKOUT output divider. Allowed values are [1] and [2, 4, 6, ..., 27]. Ille-
gal odd divider values will be rounded up to the nearest even value. The value for the
N1 register can be calculated by taking the divider ratio minus one. For example, to
divide by 10, write 0001001 (9 decimal) to the N1 registers.
0000000 = 1
1111111 = 27
5:0 RFREQ[37:32] Reference Frequency.
Frequency control input to DCO.
Si598/Si599
16 Rev. 1.1
Register 9. Refe ren c e Fre que n cy
BitD7D6D5D4D3D2D1D0
Name RFREQ[31:24]
Type R/W
Bit Name Function
7:0 RFREQ[31:24] Reference Frequency.
Frequency control input to DCO.
Register 10. Reference Frequency
BitD7D6D5D4D3D2D1D0
Name RFREQ[23:16]
Type R/W
Bit Name Function
7:0 RFREQ[23:16] Reference Frequency.
Frequency control input to DCO.
Register 11. Reference Frequency
BitD7D6D5D4D3D2D1D0
Name RFREQ[15:8]
Type R/W
Bit Name Function
7:0 RFREQ[15:8] Reference Frequency.
Frequency control input to DCO.
Si598/Si599
Rev. 1.1 17
Reset settings = 00xxxx00
Register 12. Reference Frequency
BitD7D6D5D4D3D2D1D0
Name RFREQ[7:0]
Type R/W
Bit Name Function
7:0 RFREQ[7:0] Refe rence Frequency.
Frequency control input to DCO.
Register 135. NewFreq/Freeze/Memory Control
BitD7D6D5D4D3D2D1D0
Name NewFreq Freeze M Freeze
VCADC
RECALL
Type R/W R/W R/W R/W R/W R/W R/W R/W
Bit Name Function
7 Reserved This bit should read 0 in normal operation.
6 NewFreq New Frequency Applied.
Alerts the DSPLL that a new frequency configuration has been applied. This bit will
clear itself when the new frequency is applied. Write 0x40 to this register to assert
NewFreq.
5 Freeze M Freezes the M Control Word.
Prevents interim frequency changes when writing RFREQ registers.
4Freeze
VCADC
Freezes the VCDADC Output Word.
May be used to hold the nominal output frequency of the Si599. Do not use with Si598.
3:1 Reserved Always zero.
0 RECALL Recall NVM into RAM.
0 = No operation.
1 = Write NVM bits into RAM. Bit is internally reset following completion of operation.
Si598/Si599
18 Rev. 1.1
Reset settings = Si598: 0000xxxx, Si599: 1000xxxx
Register 137. Freeze DCO
BitD7D6D5 D4 D3D2D1D0
Name Freeze DCO
Type R/W R/W R/W R/W R R R R
Bit Name Function
7 Reserved 0: Si598
1: Si599
6:5 Reserved This bits should read 0 in normal operation.
4 Freeze DCO Freeze DCO.
Freezes the DSPLL so the frequency configuration can be modified.
Si598: Write 0x10 to this register to Freeze DCO.
Si599: Write 0x90 to this register to Freeze DCO.
3:0 Reserved Read only.
Si598/Si599
Rev. 1.1 19
5. Si598 (XO) Pin Descriptions
Table 15. Si598 Pin Descriptions
Pin Name Type Function
1NC N/A No Connect.
Make no external connection to this pin.
2OE Input Output Enable.*
See 7. Ordering Information on page 21.
3GND Ground Electrical and Case Ground.
4CLK+ Output Oscillator Output.
5CLK–
(NC for CMOS)
Output
(N/A for CMOS)
Complementary Output.
(NC for CMOS, do not make external connection).
6 VDD Power Power Supply Voltage.
7SDA Bidirectional
Open Drain I2C Serial Data.
8SCL Input I2C Serial Clock.
*Note: OE pin includes a 17 k resistor to VDD for OE active high option or 17 k to GND for OE active low option.
1
2
3
6
5
4
NC
GND
OE
VDD
CLK+
CLK–
SDA
SCL
8
7
Si598/Si599
20 Rev. 1.1
6. Si599 (VCXO) Pin Descriptions
Table 16. Si599 Pin Descriptions
Pin Name Type Function
1 VCAnalog Input Control Voltage.
2OE Input Output Enable.*
See 7. Ordering Information on page 21.
3GND Ground Electrical and Case Ground.
4CLK+ Output Oscillator Output.
5CLK–
(NC for CMOS)
Output
(N/A for CMOS)
Complementary Output.
(NC for CMOS, do not make external connection).
6 VDD Power Power Supply Voltage.
7SDA Bidirectional
Open Drain I2C Serial Data.
8SCL Input I2C Serial Clock.
*Note: OE pin includes a 17 k resistor to VDD for OE active high option or 17 k to GND for OE active low option.
1
2
3
6
5
4
VC
GND
OE
VDD
CLK+
CLK–
SDA
SCL
8
7
Si598/Si599
Rev. 1.1 21
7. Ordering Information
The Si598/Si599 supports a wide variety of options including frequency range, start-up frequency, temperature
stability, tuning slope, output format, and VDD. Specific device configurations are programmed into the Si598/Si599
at time of shipment. Configurations are specified using the Part Number Configuration chart shown below. Silicon
Labs provides a web browser-based part number configuration utility to simplify this process. Refer to
www.silabs.com/VCXOPartNumber to access this tool and for further ordering instructions. The Si598/Si599 XO/
VCXO series is supplied in an industry-standard, RoHS compliant, 8-pad, 5x7 mm package. Tape and reel
packaging is an ordering option.
Figure 5. Part Number Convention
598 Programmable
XO Product Family
59x X
1st Option Code
VDD Output Format Output Enable Polarity
A 3.3 LVPECL High
B 3.3 LV DS High
C 3.3 CMOS High
D 3.3 CML High
E 2.5 LVPECL High
F 2.5 LVDS High
G 2.5 CMOS High
H 2.5 CML High
J 1.8 CMOS High
K 1.8 CML High
M 3.3 LVPECL Low
N 3.3 LVDS Low
P 3.3 CMOS Low
Q 3.3 CML Low
R 2.5 LVPECL Low
S 2.5 LVDS Low
T 2.5 CMOS Low
U 2.5 CML Low
V 1.8 CMOS Low
W 1.8 CML Low
Note:
CMOS available to 160 MHz.
599 Programmable
VCXO Product Family
R = Tape and Reel
Blank = Coil Tape
Operating Temp Range (°C)
G –40 to +85 °C
Device Revision Letter
X D G R
Six-Digit Start-up Frequency /I2C Address Designator
The Si59x supports a user -defined start-up frequency between
10–810 MHz. The start-up frequency must be in the same frequency range
as that specified by the Frequency Grade 3rd option code.
The Si59x supports a user -defined I 2C 7-bit address. Each unique start-up
frequency/I2C address combination is assigned a six-digit numerical code.
This code can be requested during the part number request process . Refer
to www .silabs.com/VCXOPartNumber to request an Si59x part number .
XXXX XXX
3rd Option Code
Frequency Grade
Code Frequency Range Supported (MHz)
A10-810
B 10-280
C 10-160 (CMOS available to 160 MHz )
2nd Option Code
Temperature Tuning Slope Minimum APR
Stability Kv ppm) for VDD @
Code ± ppm (max) ppm /V (typ) 3.3 V 2.5 V 1 .8 V
A 20 380 370 275 200
B 20 185 160 110 80
C 50 185 130 80 50
D 20 125 100 75 40
E20 95 655025
F 50 125 70 45 10
G 50 95 35 20 N/A
H20 45 15N/AN/A
Notes :
1. For best jitter and phase noise performance , always choose the smallest Kv that meets
the applications minimum APR requirements . See AN266 for more information .
2. APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO with an
APR of ±25 ppm is able to lock to a clock with a ±25 ppm stability over 15 years over all
operating conditions .
3. Nominal pull range (±) = 0.5 x VDD x tuning slope.
4. Minimum APR values noted above include worst case values for all parameters .
Si598
Si599
2nd Option Code
Code Temperature Stability (ppm, max , ±) Total Stablility (ppm, max, ±)
A 50 100
B 25 50
C 20 30
Si598/Si599
22 Rev. 1.1
Table 17. Standard Si598 Part Numbers
Part Number VDD Output
Format Total Stability Frequency
Range Startup
Frequency I2C Address
598CCC000107DG 3.3V CMOS 30 ppm 10–160 MHz 10 MHz 0x55
598BCA000107DG 3.3V LVDS 30 ppm 10–810 MHz 10 MHz 0x55
Si598/Si599
Rev. 1.1 23
8. Si59x Mark Specification
Figure 6 illustrates the mark specification for the Si59x. Table 18 lists the line information.
Figure 6. Mark Specification
Table 18. Si59x Top Mark Description
Line Position Description
1 1–10 “SiLabs"+ Part Family Number, 59x (first 3 characters in part number where x = 8
indicates a 598 device and x = 9 indicates a 599 device).
2 1–10 Option1 + Option2 + Option3 + ConfigNum(6) + Temp
3 Trace Code
Position 1 Pin 1 orientation mark (dot)
Position 2 Product Revision (D)
Position 3–6 Tiny Trace Code (4 alphanumeric characters per assembly release instructions)
Position 7 Year (least significant year digit), to be assigned by assembly site (ex: 2010 = 0)
Position 8–9 Calendar Work Week number (1–53), to be assigned by assembly site
Position 10 “+” to indicate Pb-Free and RoHS-compliant
Si598/Si599
24 Rev. 1.1
9. Outline Diagram and Suggested Pad Layout
Figure 7 illustrates the package details for the Si598/Si599. Table 19 lists the values for the dimensions shown in
the illustration.
Figure 7. Si598/Si599 Outline Diagram
Table 19. Package Diagram Dimensions (mm)
Dimension Min Nom Max
A 1.50 1.65 1.80
b 1.30 1.40 1.50
b1 0.90 1.00 1.10
c 0.50 0.60 0.70
c1 0.30 0.60
D 5.00 BSC
D1 4.30 4.40 4.50
e 2.54 BSC
E 7.00 BSC
E1 6.10 6.20 6.30
H 0.55 0.65 0.75
L 1.17 1.27 1.37
L1 1.07 1.17 1.27
p 1.80 2.60
R0.70 REF
aaa 0.15
bbb 0.15
ccc 0.10
ddd 0.10
eee 0.05
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Si598/Si599
Rev. 1.1 25
10. 8-Pin PCB Land Pattern
Figure 8 illustrates the 8-pin PCB land pattern for the Si598/Si599. Table 20 lists the values for the dimensions
shown in the illustration.
Figure 8. Si598/Si599 PCB Land Pattern
Table 20. PCB Land Pattern Dimensions (mm)
Dimension Min Max
D2 5.08 REF
D3 5.705 REF
e 2.54 BSC
E2 4.20 REF
GD 0.84
GE 2.00
VD 8.20 REF
VE 7.30 REF
X1 1.70 TYP
X2 1.545 TYP
Y1 2.15 REF
Y2 1.3 REF
ZD 6.78
ZE 6.30
Note:
1. Dimensioning and tolerancing per the ANSI Y14.5M-1994
specification.
2. Land pattern design follows IPC-7351 guidelines.
3. All dimensions shown are at maximum material condition
(MMC).
4. Controlling dimension is in millimeters (mm).
Si598/Si599
26 Rev. 1.1
REVISION HISTORY
Revision 1.1
June, 2018
Changed “Trays” to “Coil Tape” in 7. Ordering Information on page 21.
Revision 1.0
Updated Register 135, “NewFreq/Freeze/Memory Control,” on page 17.
Updated Register 137, “Freeze DCO,” on page 18.
Revision 0.9
Updated Si598/599 devices to support frequencies up to 810 MHz for LVPECL, LVDS, and CML outputs.
Added Table 13, “Thermal Characteristics,” on page 10.
Updated ESD HBM sensitivity rating in Table 14 on page 10.
Updated Table 11 on page 9 to include "Moisture Sensitivity Level" and "Contact Pads" rows.
Updated Figure 6 and Table 18 on page 23 to reflect specific marking information.
Corrected pin 7 and pin 8 designation in package diagram in Figure 7 on page 24.
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598CCC000107DG 598CCC000118DG 598CCC000141DG 598BCC000121DG 598BCA000118DG
598ACB000103DG 598BCA000107DG 598DAC000716DG 599CFC000107DG 598AAA000107DG
599ADA000107DG 599PCC000121DG 599PHC000112DG 598PCC000112DG 599PAC000112DG
599CCC000107DG 599ABA000107DG 599NCA000107DG 598JCC000111DG 599ACA000107DG
599ADC000107DG 598PAC000141DG 599KCA000103DG 598FCB000815DG 599KCA000388DG
599BBA000107DG 598ACA000112DG 599CGC001613DG 598BCA001138DG 598BCA001140DG
598BCA001139DG 598BCA001207DG 598BCA001141DG 598BCA000795DG 598ACA001204DG
598BCA000824DG 598BCA001137DG 598BCA001136DG 598BCA001143DG 598BCA001142DG
598BCA001206DG 598BCA001144DG 598BCA001134DG 598EBA000374DG 598BBA000159DG
598BCA001653DG 598MCB000112DG 598MBB000112DG 599PBC000112DG 598DBA000420DG
598CCC000157DG 598CCC000654DG 598CAC000121DG 598PAC001583DG 598BBB000159DG
598BCA000896DG 599AFA000107DG 598ACB000106DG 598FCA000107DG 598JAC000107DG
598HBB000115DG 599BAA001603DG 599CDC000125DG 599BCA000112DG 598ACA000653DG
599PFC000613DG 598FCA000126DG 598BAC000121DG 598BCA000112DG 599MDA000118DG
598FBB000115DG 598CCC000215DG 598AAB000121DG 599CAC000112DG 598CCC001716DG
598BCA001212DG 598BBA000658DG