General Description
The MAX9276/MAX9280 gigabit multimedia serial link
(GMSL) deserializers receive data from a GMSL serializer
over 50Ω coax or 100Ω shielded twisted pair (STP) cable
and output deserialized data on the LVCMOS outputs.
The MAX9280 has HDCP content protection but other-
wise is the same as the MAX9276. The deserializers pair
with any GMSL serializer capable of coax output including
the MAX9293 HDMI/MHL serializer. When programmed
for STP input they are backward compatible with any
GMSL serializer.
The audio channel supports L-PCM I2S stereo and up to
eight channels of L-PCM in TDM mode. Sample rates of
32kHz to 192kHz are supported with sample depth up to
32 bits.
The embedded control channel operates at 9.6kbps to
1Mbps in UART-UART and UART-I2C modes, and up to
1Mbps in I2C-I2C mode. Using the control channel, a µC
can program serializer, deserializer, and peripheral device
registers at any time, independent of video timing, and
manage HDCP operation (MAX9280). Two GPIO ports
are included, allowing display power-up and switching of
the backlight among other uses. A continuously-sampled
GPI input supports touch-screen controller interrupt
requests in display applications.
For use with longer cables, the deserializers have a pro-
grammable cable equalizer. Programmable spread spec-
trum is available on the parallel output. The serial input
meets ISO 10605 and IEC 61000-4-2 ESD standards.
The core supply is 3.0V to 3.6V and the I/O supply is
1.7V to 3.6V.
The devices are in lead-free, 56-lead, 8mm x 8mm TQFN
and QFND packages with exposed pad and 0.5mm lead
pitch.
Applications
● High-Resolution Automotive Navigation
● Rear-Seat Infotainment
● Megapixel Camera Systems
Benets and Features
● Ideal for High-Definition Video Applications
• Works with Low-Cost 50Ω Coax Cable and FAKRA
Connectors or 100Ω STP
• 104MHz High-Bandwidth Mode Supports
1920x720p/60Hz Display With 24-Bit Color
• Equalization Allows 15m Cable at Full Speed
• Up to 192kHz Sample Rate And 32-Bit Sample
Depth For 7.1 Channel HD Audio
• Audio Clock from Audio Source or Audio Sink
• Color Lookup-Table for Gamma Correction
• CNTL[3:0] Control Outputs
● Multiple Data Rates for System Flexibility
• Up to 3.12Gbps Serial-Bit Rate
• 6.25MHz to 104MHz Pixel Clock
• 9.6kbps to 1Mbps Control Channel in UART, Mixed
UART/I2C, or I2C Mode with Clock Stretch
Capability
● Reduces EMI and Shielding Requirements
• Programmable Spread Spectrum Reduces EMI
• Tracks Spread Spectrum on Input
• High-Immunity Mode for Maximum Control-
Channel Noise Rejection
● Peripheral Features for System Power-Up and
Verification
• Built-In PRBS Tester for BER Testing of the Serial
Link
• Programmable Choice of 8 Default Device
Addresses
• Two Dedicated GPIO Ports
• Dedicated “Up/Down” GPI for Touch-Screen
Interrupt and Other Uses
• Remote/Local Wake-Up from Sleep Mode
● Meets Rigorous Automotive and Industrial
Requirements
• -40°C to +105°C Operating Temperature
• ±8kV Contact and ±15kV Air ISO 10605 and
IEC 61000-4-2 ESD Protection
Ordering Information appears at end of data sheet.
19-6623; Rev 1; 11/15
µC
GMSL
SERIALIZER
MAX9276
MAX9280
VIDEO/AUDIO
I
2
C
720p
DISPLAY
VIDEO/AUDIO
I
2
C
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
TABLE OF CONTENTS
General Description ............................................................................ 1
Applications .................................................................................. 1
Benefits and Features .......................................................................... 1
Absolute Maximum Ratings ...................................................................... 7
Package Thermal Characteristics ................................................................. 7
DC Electrical Characteristics ..................................................................... 7
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Typical Operating Characteristics ................................................................ 15
Pin Configuration ............................................................................. 17
Pin Description............................................................................... 17
Functional Diagram ........................................................................... 20
Detailed Description........................................................................... 24
Register Mapping ...........................................................................24
Output Bit Map .............................................................................25
Serial Link Signaling and Data Format ...........................................................25
High-Bandwidth Mode .......................................................................28
Audio Channel..............................................................................28
Audio Channel Input ......................................................................28
Audio Channel Output .....................................................................31
Additional MCLK Output for Audio Applications .................................................32
Audio Output Timing Sources ...............................................................32
Reverse Control Channel .....................................................................32
Control Channel and Register Programming ......................................................33
UART Interface ..........................................................................33
Interfacing Command-Byte-Only I2C Devices with UART .........................................35
UART Bypass Mode ......................................................................35
I2C Interface ...............................................................................36
START and STOP Conditions ...............................................................36
Bit Transfer..............................................................................36
Acknowledge ............................................................................37
Slave Address ...........................................................................37
Bus Reset...............................................................................37
Format for Writing ........................................................................38
Format for Reading .......................................................................39
I2C Communication with Remote Side Devices .................................................39
I2C Address Translation ......................................................................39
GPO/GPI Control ...........................................................................40
Line Equalizer ..............................................................................40
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
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TABLE OF CONTENTS (continued)
Spread Spectrum ...........................................................................40
Manual Programming of the Spread-Spectrum Divider ..............................................40
HS/VS/DE Tracking..........................................................................41
Serial Input ................................................................................41
Coax Splitter Mode ..........................................................................41
Cable Type Configuration Input ................................................................41
Color Lookup Tables.........................................................................42
Programming and Verifying LUT Data.........................................................42
LUT Color Translation .....................................................................42
LUT Bit Width............................................................................42
Recommended LUT Program Procedure ......................................................43
High-Immunity Reverse Control Channel Mode....................................................44
Sleep Mode................................................................................44
Power-Down Mode ..........................................................................44
Configuration Link...........................................................................44
Link Startup Procedure ........................................................................ 45
High-Bandwidth Digital Content Protection (HDCP) .................................................. 47
Encryption Enable...........................................................................47
Synchronization of Encryption .................................................................47
Repeater Support ...........................................................................47
HDCP Authentication Procedures ................................................................ 48
HDCP Protocol Summary.....................................................................48
Example Repeater Network—Two µCs ........................................................52
Detection and Action Upon New Device Connection................................................55
Notification of Start of Authentication and Enable of Encryption to Downstream Links .....................55
Applications Information........................................................................ 56
Self PRBS Test .............................................................................56
Error Checking .............................................................................56
ERR Output ...............................................................................56
Auto Error Reset ............................................................................56
Dual µC Control ............................................................................56
Changing the Clock Frequency.................................................................56
Fast Detection of Loss of Synchronization ........................................................56
Providing a Frame Sync (Camera Applications)....................................................57
Software Programming of the Device Addresses...................................................57
3-Level Configuration Inputs...................................................................57
Configuration Blocking .......................................................................57
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
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TABLE OF CONTENTS (continued)
Compatibility with Other GMSL Devices .........................................................57
Key Memory ...............................................................................57
HS/VS/DE Inversion .........................................................................57
WS/SCK Inversion ..........................................................................57
GPIOs ....................................................................................58
Staggered Parallel Outputs....................................................................58
Internal Input Pulldowns ......................................................................58
Choosing I2C/UART Pullup Resistors ...........................................................58
AC-Coupling ...............................................................................58
Selection of AC-Coupling Capacitors............................................................58
Power-Supply Circuits and Bypassing ...........................................................58
Power-Supply Table .........................................................................59
Cables and Connectors ......................................................................59
Board Layout...............................................................................60
ESD Protection .............................................................................60
Typical Application Circuit ...................................................................... 69
Ordering Information .......................................................................... 69
Chip Information.............................................................................. 69
Package Information .......................................................................... 69
Revision History .............................................................................. 70
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
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LIST OF FIGURES
Figure 1. Reverse Control Channel Output Parameters ............................................... 21
Figure 2a. Test Circuit for Single-Ended Input Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 2. Test Circuit for Differential Input Measurement .............................................. 21
Figure 3. Worst-Case Pattern Output ............................................................. 22
Figure 4. I2C Timing Parameters ................................................................. 22
Figure 5. Parallel Clock Output Requirements ...................................................... 22
Figure 6. Output Rise-and-Fall Times ............................................................. 23
Figure 7. Deserializer Delay ..................................................................... 23
Figure 8. GPI-to-GPO Delay .................................................................... 23
Figure 9. Lock Time ........................................................................... 24
Figure 10. Power-Up Delay ..................................................................... 24
Figure 11. Output I2S Timing Parameters .......................................................... 24
Figure 12. 24-Bit Mode Serial Data Format......................................................... 26
Figure 13. 32-Bit Mode Serial Data Format......................................................... 27
Figure 14. High-Bandwidth Mode Serial Data Format................................................. 27
Figure 15. Audio Channel Input Format............................................................ 28
Figure 16. 8-Channel TDM (24-Bit Samples, Padded With Zeros) ....................................... 30
Figure 17. 6-Channel TDM (24-Bit Samples, No Padding) ............................................. 30
Figure 18. Stereo I2S (24-Bit Samples, Padded With Zeros) ........................................... 30
Figure 19. Stereo I2S (16-Bit Samples, No Padding).................................................. 31
Figure 20. Audio Channel Output Format .......................................................... 31
Figure 21. GMSL UART Protocol for Base Mode .................................................... 33
Figure 22. GMSL UART Data Format for Base Mode................................................. 34
Figure 23. Sync Byte (0x79)..................................................................... 34
Figure 24. ACK Byte (0xC3)..................................................................... 34
Figure 25. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 0)........ 34
Figure 26. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 1)........ 35
Figure 27. START and STOP Conditions........................................................... 36
Figure 28. Bit Transfer ......................................................................... 36
Figure 29. Acknowledge........................................................................ 37
Figure 30. Slave Address....................................................................... 37
Figure 31. Format for I2C Write .................................................................. 38
Figure 32. Format for Write to Multiple Registers .................................................... 38
Figure 33. Format for I2C Read .................................................................. 39
Figure 34. 2:1 Coax Splitter Connection Diagram.....................................................41
Figure 35. Coax Connection Diagram ..............................................................41
Figure 36. LUT Dataflow ....................................................................... 43
Figure 37. State Diagram ....................................................................... 46
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
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LIST OF TABLES
Table 1. Device Address Defaults (Register 0x00, 0x01) .............................................. 25
Table 2. Output Map........................................................................... 26
Table 3. Data-Rate Selection Table............................................................... 28
Table 4. Maximum Audio WS Frequency (kHz) for Various PCLKOUT Frequencies ......................... 29
Table 5. fSRC Settings ........................................................................ 32
Table 6. I2C Bit Rate Ranges.................................................................... 39
Table 7. Cable Equalizer Boost Levels............................................................. 40
Table 8. Output Spread ........................................................................ 40
Table 9. Modulation Coefficients and Maximum SDIV Settings ......................................... 40
Table 10. Configuration Input Map.................................................................41
Table 11. Pixel Data Format ..................................................................... 42
Table 12. Reverse Control Channel Modes ......................................................... 44
Table 13. Fast High-Immunity Mode Requirements................................................... 44
Table 14. Startup Procedure for Video-Display Applications ........................................... 45
Table 15. Startup Procedure for Image-Sensing Applications (CDS = High) ............................... 46
Table 16. Startup, HDCP Authentication, and Normal Operation (Deserializer is Not a Repeater)—First Part of the
HDCP Authentication Protocol................................................................... 48
Table 17. Link Integrity Check (Normal)—Performed Every 128 Frames After Encryption is Enabled ........... 50
Table 18. Optional Enhanced Link Integrity Check—Performed Every 16 Frames After Encryption is Enabled .... 51
Table 19. HDCP Authentication and Normal Operation (One Repeater, Two µCs)—First and Second Parts of the
HDCP Authentication Protocol................................................................... 52
Table 20. MAX9276/MAX9280 Feature Compatibility ................................................. 57
Table 21. Staggered Output Delay................................................................ 58
Table 22. IOVDD Current Simulation Results ....................................................... 59
Table 23. Additional Supply Current from HDCP (MAX9280 Only)....................................... 59
Table 24. Suggested Connectors and Cables for GMSL............................................... 59
Table 25. Register Table ....................................................................... 61
Table 26. HDCP Register Table (MAX9280 Only).................................................... 67
LIST OF FIGURES (continued)
Figure 38. Example Network with One Repeater and Two µCs (Tx = GMSL Serializer’s, Rx = Deserializer’s)..... 52
Figure 39. Human Body Model ESD Test Circuit..................................................... 60
Figure 40. IEC 61000-4-2 Contact Discharge ESD Test Circuit ......................................... 60
Figure 41. ISO 10605 Contact Discharge ESD Test Circuit ............................................ 60
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
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(Note 1)
AVDD to EP ..........................................................-0.5V to +3.9V
DVDD to EP .........................................................-0.5V to +3.9V
IOVDD to EP ........................................................-0.5V to +3.9V
IN+, IN- to EP .......................................................-0.5V to +1.9V
All Other Pins to EP ............................-0.5V to (VIOVDD + 0.5V)
IN+, IN- Short Circuit to Ground or Supply ...............Continuous
Continuous Power Dissipation (TA = +70°C)
TQFN (derate 47.6mW/°C above +70°C)...............3809.5mW
QFND (derate 42.7mW/°C above +70°C) .................3418mW
Junction Temperature ......................................................+150°C
Storage Temperature ........................................ -65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
(Note 2)
TQFN
Junction-to-Case Thermal Resistance (θJC) .................1°C/W
Junction-to-Ambient Thermal Resistance (θJA) ..........21°C/W
QFND
Junction-to-Case Thermal Resistance (θJC)...............1.6°C/W
Junction-to-Ambient Thermal Resistance (θJA) .......23.4°C/W
(VAVDD = VDVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100Ω ±1% (differential), EP connected to PCB ground (GND), TA = -40°C
to +105°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 3.3V, TA = +25°C.)(Note 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SINGLE-ENDED INPUTS (ADD_, HIM, I2CSEL, GPI, PWDN, MS)
High-Level Input Voltage VIH1 0.65 x
VIOVDD V
Low-Level Input Voltage VIL1 0.35 x
VIOVDD V
Input Current IIN1 VIN = 0V to VIOVDD -10 +20 µA
THREE-LEVEL LOGIC INPUTS (BWS, CX/TP)
High-Level Input Voltage VIH 0.7 x
VIOVDD V
Low-Level Input Voltage VIL 0.3 x
VIOVDD V
Mid-Level Input Current IINM (Note 4) -10 10 µA
Input Current IIN -150 150 µA
SINGLE-ENDED OUTPUTS (WS, SCK, SD, DOUT_, CNTL_, INTOUT, PCLKOUT)
High-Level Output Voltage VOH1 IOUT = -2mA
DCS = ‘0’ VIOVDD
- 0.3 V
DCS = ‘1’ VIOVDD
- 0.2
Low-Level Output Voltage VOL1 IOUT = 2mA DCS = ‘0’ 0.3 V
DCS = ‘1’ 0.2
Absolute Maximum Ratings
Note 1: EP connected to PCB ground.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
DC Electrical Characteristics
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
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(VAVDD = VDVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100Ω ±1% (differential), EP connected to PCB ground (GND), TA = -40°C
to +105°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 3.3V, TA = +25°C.) (Note 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
OUTPUT Short-Circuit Current IOS
DOUT_
VO = 0V,
DCS = ‘0’
VIOVDD =
3.0V to 3.6V 15 25 39
mA
VIOVDD =
1.7V to 1.9V 3 7 13
VO = 0V,
DCS = ‘1’
VIOVDD =
3.0V to 3.6V 20 35 63
VIOVDD =
1.7V to 1.9V 510 21
PCLKOUT
VO = 0V,
DCS = ‘0’
VIOVDD =
3.0V to 3.6V 15 33 50
VIOVDD =
1.7V to 1.9V 510 17
VO = 0V,
DCS = ‘1’
VIOVDD =
3.0V to 3.6V 30 54 97
VIOVDD =
1.7V to 1.9V 916 32
OPEN-DRAIN INPUT/OUTPUT (GPIO0, GPIO1, RX/SDA, TX/SCL, ERR, LOCK)
High-Level Input Voltage VIH2 0.7 x
VIOVDD V
Low-Level Input Voltage VIL2 0.3 x
VIOVDD V
Input Current IIN2 (Note 5) RX/SDA, TX/SCL -100 +5 µA
LOCK, ERR, GPIO_ -80 +5
Low-Level Output Voltage VOL2 IOUT = 3mA VIOVDD = 1.7V to 1.9V 0.4 V
VIOVDD = 3.0V to 3.6V 0.3
Input Capacitance CIN Each pin (Note 6) 10 pF
OUTPUT FOR REVERSE CONTROL CHANNEL (IN+, IN-)
Differential High Output Peak
Voltage (VIN+) - (VIN-) VRODH
Forward channel
disabled,
Figure 1
Legacy reverse control
channel mode 30 60 mV
High immunity mode 50 100
Differential Low Output Peak
Voltage (VIN+) - (VIN-) VRODL
Forward channel
disabled,
Figure 1
Legacy reverse control
channel mode -60 -30 mV
High immunity mode -100 -50
Single-Ended High Output Peak
Voltage VROSH Forward channel
disabled
Legacy reverse control
channel mode 30 60 mV
High immunity mode 50 100
Single-Ended Low Output Peak
Voltage VROSL Forward channel
disabled
Legacy reverse control
channel mode -60 -30 mV
High immunity mode -100 -50
DC Electrical Characteristics (continued)
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
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(VAVDD = VDVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100Ω ±1% (differential), EP connected to PCB ground (GND), TA = -40°C
to +105°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 3.3V, TA = +25°C.) (Note 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIFFERENTIAL INPUTS (IN+, IN-)
Differential High Input Threshold
(Peak) Voltage (VIN+) - (VIN-) VIDH(P) Figure 2
Activity detector medium
Threshold, (0x0B D[6:5] = 01) 60
mV
Activity detector low
Threshold, (0x0B D[6:5] = 00) 47.5
Differential Low Input Threshold
(Peak) Voltage (VIN+) - (VIN-) VIDL(P) Figure 2
Activity detector medium
Threshold, (0x0B D[6:5] = 01) -60
mV
Activity detector medium
Threshold, (0x0B D[6:5] = 00) -47.5
Input Common-Mode Voltage
((VIN+) + (VIN-))/2 VCMR 1 1.3 1.6 V
Differential Input Resistance
(Internal) RIN 80 100 130 Ω
SINGLE-ENDED INPUTS (IN+, IN-)
Single-Ended High Input
Threshold (Peak) Voltage VISH(P) Figure 2a
Activity detector medium
threshold, (0x0B D[6:5] = 01) 43
mV
Activity detector low threshold,
(0x0B D[6:5] = 00) 33
Single-Ended Low Input
Threshold (Peak) Voltage VISL(P) Figure 2a
Activity detector medium
threshold, (0x0B D[6:5] = 01) -43
mV
Activity detector medium
threshold, (0x0B D[6:5] = 00) -33
Input Resistance (Internal) RI40 50 65 Ω
POWER SUPPLY
Total Supply Current (AVDD
+ DVDD + IOVDD) (Note 7)
(Worst-Case-Pattern, Figure 3)
IWCS
BWS = low,
fPCLKOUT =
16.6MHz
2% spread
active
CL = 5pF 131 164
mA
CL = 10pF 136 169
Spread
spectrum
disabled
CL = 5pF 122 153
CL = 10pF 127 158
BWS = low,
fPCLKOUT =
33.3MHz
2% spread
active
CL = 5pF 144 179
CL = 10pF 153 189
Spread
spectrum
disabled
CL = 5pF 133 167
CL = 10pF 142 177
BWS = low,
fPCLKOUT =
66.6MHz
2% spread
active
CL = 5pF 175 216
CL = 10pF 190 233
Spread
spectrum
disabled
CL = 5pF 159 197
CL = 10pF 174 214
DC Electrical Characteristics (continued)
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
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(VAVDD = VDVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100Ω ±1% (differential), EP connected to PCB ground (GND), TA = -40°C
to +105°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 3.3V, TA = +25°C.) (Note 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Total Supply Current (AVDD
+ DVDD + IOVDD) (Note 7)
(Worst-Case-Pattern, Figure 3)
IWCS
BWS = low,
fPCLKOUT =
104MHz
2% spread
active
CL = 5pF 212 255
mA
CL = 10pF 234 278
Spread
spectrum
disabled
CL = 5pF 190 228
CL = 10pF 212 251
BWS = mid,
fPCLKOUT =
36.6MHz
2% spread
active
CL = 5pF 154 191
CL = 10pF 164 203
Spread
spectrum
disabled
CL = 5pF 143 177
CL = 10pF 154 189
BWS = mid,
fPCLKOUT =
104MHz
2% spread
active
CL = 5pF 231 277
CL = 10pF 257 305
Spread
spectrum
disabled
CL = 5pF 209 249
CL = 10pF 234 277
Sleep Mode Supply Current ICCS 70 265 µA
Power-Down Current ICCZ PWDN = GND 20 195 µA
ESD PROTECTION
IN+, IN- (Note 8) VESD
Human body model, RD = 1.5kΩ,
CS = 100pF ±8
kV
IEC 61000-4-2, RD =
330Ω, CS = 150pF
Contact discharge ±10
Air discharge ±12
ISO 10605, RD = 2kΩ,
CS = 330pF
Contact discharge ±10
Air discharge ±20
All Other Pins (Note 9) VESD Human body model, RD = 1.5kΩ,
CS = 100pF ±4 kV
DC Electrical Characteristics (continued)
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
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(VAVDD = VDVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100Ω ±1% (differential), EP connected to PCB ground (GND), TA = -40°C
to +105°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 3.3V, TA = +25°C.) (Note 10)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PARALLEL CLOCK OUTPUT (PCLKOUT)
Clock Frequency fPCLKOUT
BWS = low, DRS = ‘1’ 8.33 16.66
MHz
BWS = low, DRS = ‘0’ 16.66 104
BWS = mid, DRS = ‘1’ 18.33 36.66
BWS = mid, DRS = ‘0’ 36.66 104
BWS = high, DRS = ‘1’ 6.25 12.5
BWS = high, DRS = ‘0’ 12.5 78
Clock Duty Cycle DC tHIGH/tT or tLOW/tT (Note 6) 40 50 60 %
Clock Jitter tJ
Period jitter, peak-to-peak, spread off,
3.12Gbps, PRBS pattern, UI = 1/fPCLKOUT
(Note 6)
0.05 UI
I2C/UART PORT TIMING
I2C/UART Bit Rate 9.6 1000 kbps
Output Rise Time tR30% to 70%, CL = 10pF to 100pF, 1kΩ
pullup to VIOVDD 20 150 ns
Output Fall Time tF70% to 30%, CL = 10pF to 100pF, 1kΩ
pullup to VIOVDD 20 150 ns
I2C TIMING (Figure 4)
SCL Clock Frequency fSCL
Low fSCL range:
(I2CMSTBT = 010, I2CSLVSH = 10) 9.6 100
kHz
Mid fSCL range:
(I2CMSTBT 101, I2CSLVSH = 01) > 100 400
High fSCL range:
(I2CMSTBT = 111, I2CSLVSH = 00) > 400 1000
START Condition Hold Time tHD:STA fSCL range
Low 4.0
µsMid 0.6
High 0.26
Low Period of SCL Clock tLOW fSCL range
Low 4.7
µs
Mid 1.3
High
VIOVDD = 1.7V to
< 3V (Note 11) 0.6
VIOVDD = 3.0V to
3.6V 0.5
High Period of SCL Clock tHIGH fSCL range
Low 4.0
µsMid 0.6
High 0.26
Repeated START Condition
Setup Time tSU:STA fSCL range
Low 4.7
µsMid 0.6
High 0.26
AC Electrical Characteristics
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
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11
(VAVDD = VDVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100Ω ±1% (differential), EP connected to PCB ground (GND), TA = -40°C
to +105°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 3.3V, TA = +25°C.) (Note 10)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Data Hold Time tHD:DAT fSCL range
Low 0
µsMid 0
High 0
Data Setup Time tSU:DAT fSCL range
Low 250
µsMid 100
High 50
Setup Time for STOP Condition tSU:STO fSCL range
Low 4.0
µsMid 0.6
High 0.26
Bus Free Time tBUF fSCL range
Low 4.7
µsMid 1.3
High 0.5
Data Valid Time tVD:DAT fSCL range
Low 3.45
µs
Mid 0.9
High
VIOVDD = 1.7V to
< 3V (Note 12) 0.55
VIOVDD = 3.0V to
3.6V 0.45
Data Valid Acknowledge Time tVD:ACK fSCL range
Low 3.45
µs
Mid 0.9
High
VIOVDD = 1.7V to
< 3V (Note 13) 0.55
VIOVDD = 3.0V to
3.6V 0.45
Pulse Width of Spikes
Suppressed tSP fSCL range
Low 50
nsMid 50
High 50
Capacitive Load Each Bus Line Cb100 pF
SWITCHING CHARACTERISTICS
PCLKOUT Rise-and-Fall Time,
Figure 5 tR, tF
20% to 80%,
VIOVDD = 1.7V to
1.9V (Note 6)
DCS = ‘1’, CL = 10pF 0.4 2.2
ns
DCS = ‘0’, CL = 5pF 0.5 2.8
20% to 80%,
VIOVDD = 3.0V to
3.6V (Note 1)
DCS = ‘1’, CL = 10pF 0.25 1.8
DCS = ‘0’, CL = 5pF 0.3 2.0
Parallel Data Rise-and-Fall Time,
Figure 6 tR, tF
20% to 80%,
VIOVDD = 1.7V to
1.9V (Note 1)
DCS = ‘1’, CL = 10pF 0.5 3.1
ns
DCS = ‘0’, CL = 5pF 0.6 3.8
20% to 80%,
VIOVDD = 3.0V to
3.6V (Note 6)
DCS = ‘1’, CL = 10pF 0.3 2.2
DCS = ‘0’, CL = 5pF 0.4 2.4
AC Electrical Characteristics (continued)
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
www.maximintegrated.com Maxim Integrated
│
12
(VAVDD = VDVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100Ω ±1% (differential), EP connected to PCB ground (GND), TA = -40°C
to +105°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 3.3V, TA = +25°C.) (Note 10)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Deserializer Delay tSD (Note 14) Figure 7
Spread spectrum
enabled 6960
Bits
Spread spectrum
disabled 2160
Reverse Control Channel Output
Rise Time tRNo forward channel data transmission,
Figure 1 180 400 ns
Reverse Control Channel Output
Fall Time tFNo forward channel data transmission,
Figure 1 180 400 ns
GPI to GPO Delay tGPIO Deserializer GPI to serializer GPO (cable
delay not included), Figure 8 350 µs
Lock Time tLOCK Figure 9
Spread spectrum
enabled 3
ms
Spread spectrum
disabled 2
Power-Up Time tPU Figure 10 8 ms
I2S/TDM OUTPUT TIMING (Note 6)
WS Jitter tjWS
tWS = 1/fWS,
(cycle-to-cycle),
rising-to-falling
edge or falling-to-
rising edge
fWS = 48kHz or
44.1kHz
1.2e-3
x tWS
1.5e-3
x tWS
nsfWS = 96kHz 1.6e-3
x tWS
2e-3 x
tWS
fWS = 192kHz 1.6e-3
x tWS
2e-3 x
tWS
SCK Jitter (2-Channel I2S) tjSCK1
tSCK = 1/fSCK,
(cycle-to-cycle),
rising-to-rising
edge
nSCK = 16 bits,
fSCK = 48kHz or
44.1kHz
13e-3 x
tSCK
16e-3 x
tSCK
ns
nSCK = 24 bits,
fWS = 96kHz
39e-3 x
tSCK
48e-3 x
tSCK
nSCK = 32 bits,
fWS = 192kHz
0.1 x
tSCK
0.13 x
tSCK
SCK Jitter (8-Channel TDM) tjSCK2
tSCK = 1/fSCK,
(cycle-to-cycle),
rising-to-rising
edge
nSCK = 16 bits,
fWS = 48kHz or
44.1kHz
52e-3 x
tSCK
64e-3 x
tSCK
ns
nSCK = 24 bits,
fWS = 96kHz
156e-3
x tSCK
192e-3
x tSCK
nSCK = 32 bits,
fWS = 192kHz
0.4 x
tSCK
0.52 x
tSCK
Audio Skew Relative to Video tASK Video and audio synchronized 3 x tWS 4 x tWS µs
SCK, SD, WS Rise-and-Fall Time tR, tF20% to 80% CL = 10pF, DCS = 1 0.3 3.1 ns
CL = 5pF, DCS = 0 0.4 3.8
AC Electrical Characteristics (continued)
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
www.maximintegrated.com Maxim Integrated
│
13
(VAVDD = VDVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100Ω ±1% (differential), EP connected to PCB ground (GND), TA = -40°C
to +105°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 3.3V, TA = +25°C.) (Note 10)
Note 3: Limits are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design
and characterization, unless otherwise noted.
Note 4: To provide a mid level, leave the input open, or, if driven, put driver in high impedance. High-impedance leakage current
must be less than ±10µA.
Note 5: IIN MIN due to voltage drop across the internal pullup resistor.
Note 6: Not production tested. Guaranteed by design.
Note 7: HDCP not enabled (MAX9280 only). IOVDD current is not production tested. See Table 23 for additional supply current
when HDCP is enabled
Note 8: Specified pin to ground.
Note 9: Specified pin to all supply/ground.
Note 10: Not production tested, guaranteed by bench characterization.
Note 11: The I2C bus standard tLOW (min) = 0.5µs.
Note 12: The I2C bus standard tVD:DAT (max) = 0.45µs.
Note 13:. The I2C bus standard tVD:ACK (max) = 0.45µs.
Note 14: Measured in serial link bit times. Bit time = 1/(30 x fPCLKIN) for BWS = ‘0’ or open. Bit time = 1/(40 x fPCLKIN)
for BWS = ‘1’.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SD, WS Valid Time Before SCK
(2-Channel I2S) tDVB1 tSCK = 1/fSCK, Figure 11 0.20 x
tSCK
0.5 x
tSCK ns
SD, WS Valid Time After SCK
(2-Channel I2S) tDVA1 tSCK = 1/fSCK, Figure 11 0.20 x
tSCK
0.5 x
tSCK ns
SD, WS Valid Time Before SCK
(8-Channel TDM) tDVB2 tSCK = 1/fSCK, Figure 11 0.20 x
tSCK
0.5 x
tSCK ns
SD, WS Valid Time After SCK
(8-Channel TDM) tDVA2 tSCK = 1/fSCK, Figure 11 0.20 x
tSCK
0.5 x
tSCK ns
AC Electrical Characteristics (continued)
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
www.maximintegrated.com Maxim Integrated
│
14
(VAVDD = VDVDD = VIOVDD = 3.3V, TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. PCLKOUT FREQUENCY (BWS = 0)
MAX9726 toc01
PCLKOUT FREQUENCY (MHz)
SUPPLY CURRENT (mA)
65 75 85 9545 55352515
130
140
150
160
170
180
190
200
120
5 105
PRBS ON, SS OFF,
COAX MODE
EQ ON
EQ OFF
SUPPLY CURRENT
vs. PCLKOUT FREQUENCY (BWS = 1)
MAX9726 toc02
PCLKOUT FREQUENCY (MHz)
SUPPLY CURRENT (mA)
50 653520
130
140
150
160
170
180
190
120
5 80
PRBS ON, SS OFF,
COAX MODE
EQ ON
EQ OFF
SUPPLY CURRENT
vs. PCLKOUT FREQUENCY (BWS = OPEN)
MAX9726 toc03
PCLKOUT FREQUENCY (MHz)
SUPPLY CURRENT (mA)
60 95754530
140
150
160
180
170
190
200
210
130
15 105
PRBS ON, SS OFF,
COAX MODE
EQ ON
EQ OFF
SUPPLY CURRENT
vs. PCLKOUT FREQUENCY (BWS = 1)
MAX9726 toc05
PCLKOUT FREQUENCY (MHz)
SUPPLY CURRENT (mA)
50 653520
140
150
160
180
170
190
200
210
130
5 80
PRBS ON, EQ ON,
COAX MODE
SS ON
SS OFF
SUPPLY CURRENT
vs. PCLKOUT FREQUENCY (BWS = 0)
MAX9726 toc04
PCLKOUT FREQUENCY (MHz)
SUPPLY CURRENT (mA)
65 75 85 9545 55352515
130
140
150
160
170
180
190
200
210
220
120
5 105
PRBS ON, EQ ON,
COAX MODE
SS ON
SS OFF
SUPPLY CURRENT
vs. PCLKOUT FREQUENCY (BWS = OPEN)
MAX9726 toc06
PCLKOUT FREQUENCY (MHz)
SUPPLY CURRENT (mA)
75 90604530
150
160
170
180
190
200
210
220
230
240
140
15 105
PRBS ON, EQ ON,
COAX MODE
SS ON
SS OFF
Typical Operating Characteristics
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
Maxim Integrated
│
15
www.maximintegrated.com
(VAVDD = VDVDD = VIOVDD = 3.3V, TA = +25°C, unless otherwise noted.)
MAXIMUM PCLKOUT FREQUENCY
vs. COAX CABLE LENGTH (BER ≤ 10-10)
MAX9726 toc09
CABLE LENGTH (m)
FREQUENCY (MHz)
10 15 2050 25
BER CAN BE AS LOW AS 10-12 FOR
CABLE LENGTHS LESS THAN 15m
-70
-60
-40
-20
-10
10
-90
OPTIMUM PE/EQ
NO PE, 10.7dB EQ
OUTPUT POWER SPECTRUM
vs. PCLKOUT FREQUENCY (VARIOUS SPREAD)
MAX9726 toc07
PCLKOUT FREQUENCY (MHz)
OUTPUT POWER (dBm)
34.033.0 33.5 35.034.532.532.031.5
-80
-70
-60
-50
-40
-30
-20
-10
0
10
-90
31.0 35.5
0% SPREAD
4% SPREAD
fPCLKOUT = 33.3MHz
2% SPREAD
OUTPUT POWER SPECTRUM
vs. PCLKOUT FREQUENCY (VARIOUS SPREAD)
MAX9726 toc08
PCLKOUT FREQUENCY (MHz)
OUTPUT POWER (dBm)
6866 67 706965646362 71
0% SPREAD
4% SPREAD
fPCLKOUT = 66.7MHz
2% SPREAD
-80
-70
-60
-50
-40
-30
-20
-10
0
10
-90
Typical Operating Characteristics (continued)
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
Maxim Integrated
│
16
www.maximintegrated.com
PIN NAME FUNCTION
1ENABLE
Active-Low Parallel Output-Enable Input With Internal Pulldown to EP. Set ENABLE = low to enable
PCLKOUT DOUT_ and CNTL_ outputs. Set ENABLE = high to put PCLKOUT, DOUT_ and CNTL_ into
high impedance.
2INTOUT/ADD2
A/V Status Register Interrupt Output/Address Selection Input With Internal Pulldown to EP. Functions
as ADD2 input at power-up or when resuming from power-down mode (PWDN = low), and switches to
INTOUT output automatically after power-up.
ADD2: Bit value is latched at power-up or when resuming from power-down mode (PWDN = low). See
Table 1. Connect INTOUT/ADD2 to IOVDD with a 30kΩ resistor to set high or leave open to set low.
INTOUT: Indicates new data in the A/V status registers. INTOUT is reset when the A/V status registers
are read.
3GPI General-Purpose Input With Internal Pulldown to EP. The serializer GPO (or INT) output follows GPI.
4 I2CSEL I2C Select. Control channel interface protocol select input with internal pulldown to EP. Set I2CSEL =
high to select I2C interface. Set I2CSEL = low to select UART interface.
5GPIO0 Open-Drain, General-Purpose Input/Output with Internal 60kΩ Pullup to IOVDD
TOP VIEW
MAX9276
MAX9280
TQFN/QFND
25
26
15
16
17
18
19
20
21
22
23
24
DOUT26
+
DOUT25
27
28
IOVDD
DOUT24
RX/SDA
TX/SCL
PWDN
ERR
LOCK
WS
SCK
SD/HIM
DOUT28/CNTL2
DOUT27/CNTL1
54
53
52
51
50
49
48
47
46
45
44
43
123 4 5 6 7 8 9 10 11 12 13 14
DOUT0
DOUT1
56
55
CX/TP
*CONNECT EP TO GROUND PLANE
AVDD
EP
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
DOUT8
DOUT9
IOVDD
DOUT10
GPIO1
CNTL3/ADD1
CNTL0/ADD0
DVDD
MS
IN-
IN+
AVDD
BWS
GPIO0
I2CSEL
GPI
INTOUT/ADD2
ENABLE
36 35 34 33 32 31 30 2940 39 38 37
PCLKOUT
DOUT15
DOUT14
DOUT13
42 41
DOUT12
DOUT11
DOUT23
DOUT22
DOUT21
DOUT20/DE
DOUT19/VS
DOUT18/HS
DOUT17
DOUT16
Pin Conguration
Pin Description
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
www.maximintegrated.com Maxim Integrated
│
17
PIN NAME FUNCTION
6BWS
Three-Level Bus Width Select Input. Set BWS to the same level on both sides of the serial link. Set
BWS = low for 24 bit mode. Set BWS = high for 32-bit mode. Set BWS = open for high-bandwidth
mode.
7, 55 AVDD 3.3V Analog Power Supply. Bypass AVDD to EP with 0.1µF and 0.001µF capacitors as close as
possible to the device with the smaller capacitor closest to AVDD.
8IN+ Noninverting Coax/Twisted-Pair Serial Input
9IN- Inverting Coax/Twisted-Pair Serial Input
10 MS Mode Select with Internal Pulldown to EP. Set MS = low, to select base mode. Set MS = high to select
the bypass mode.
11 CNTL3/ADD1
Auxiliary Control Signal Output/Address Selection Input With Internal Pulldown to EP. Functions as
ADD1 input at power-up or when resuming from power-down mode (PWDN = low), and switches to
CNTL3 output automatically after power-up.
ADD1: Bit value is latched at power-up or when resuming from power-down mode (PWDN = low). See
Table 1. Connect CNTL3/ADD1 to IOVDD with a 30kΩ resistor to set high or leave open to set low.
CNTL3: Used only in high-bandwidth mode (BWS = open). CNTL3 not encrypted when HDCP is
enabled (MAX9280 only).
12 GPIO1 Open-Drain, General-Purpose Input/Output With Internal 60kΩ Pullup to IOVDD
13 DVDD 3.3V Digital Power Supply. Bypass DVDD to EP with 0.1µF and 0.001µF capacitors as close as
possible to the device with the smaller value capacitor closest to DVDD.
14 CNTL0/ADD0
Auxiliary Control Signal Output/Address Selection Input With Internal Pulldown to EP. Functions as
ADD0 input at power-up or when resuming from power-down mode (PWDN = low), and switches to
CNTL0 output automatically after power-up.
ADD0: Bit value is latched at power-up or when resuming from power-down mode (PWDN = low). See
Table 1. Connect CNTL0/ADD0 to IOVDD with a 30kΩ resistor to set high or leave open to set low.
CNTL0: Used only in high-bandwidth mode (BWS = open). CNTL0 not encrypted when HDCP is
enabled (MAX9280 only).
15 RX/SDA
UART Receive/I2C Serial Data Input/Output with Internal 30kΩ Pullup to IOVDD. Function is
determined by the state of I2CSEL at power-up. RX/SDA has an open-drain driver and requires a
pullup resistor.
RX: Input of the serializer’s UART.
SDA: Data input/output of the serializer’s I2C Master/Slave.
16 TX/SCL
UART Transmit/I2C Serial Clock Input/Output with Internal 30kΩ Pullup to IOVDD. Function is
determined by the state of I2CSEL at power-up. TX/SCL has an open-drain driver and requires a pullup
resistor.
TX: Output of the serializer’s UART.
SCL: Clock input/output of the serializer’s I2C Master/Slave.
17 PWDN Active-Low, Power-Down Input with Internal Pulldown to EP. Set PWDN low to enter power-down mode
to reduce power consumption.
18 ERR Error Output. Open-drain data error detection and/or correction indication output with internal 30kΩ
pullup to IOVDD. ERR is high when PWDN is low
19 LOCK
Open-Drain Lock Output with Internal 30kΩ Pullup to IOVDD. LOCK = high indicates that PLLs are
locked with correct serial-word-boundary alignment. LOCK = low indicates that PLLs are not locked or
an incorrect serial-word-boundary alignment. LOCK is high when PWDN = low.
Pin Description (continued)
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
www.maximintegrated.com Maxim Integrated
│
18
PIN NAME FUNCTION
20 WS
I2S/TDM Word-Select Input/Output. Powers up as an I2S output (deserializer provided clock). Set
AUDIOMODE bit = ‘1’ to change WS to an input with internal pulldown to GND and supply WS
externally (system provided clock).
21 SCK
I2S/TDM Serial-Clock Input/Output. Powers up as an I2S output (deserializer provided clock). Set
AUDIOMODE bit = ‘1’ to change SCK to an input with internal pulldown to GND and supply WS
externally (system provided clock).
22 SD/HIM
I2S/TDM Serial-Data Output/High-Immunity Mode Input.
Functions as HIM input with internal pulldown to EP at power-up or when resuming from power-down
mode (PWDN = low), and switches to SD output automatically after power-up.
HIM: Default HIGHIMM bit value is latched at power-up or when resuming from power-down mode
(PWDN = low) and is active-high. Connect SD/HIM to IOVDD with a 30kΩ resistor to set high or leave
open to set low. HIGHIMM can be programmed to a different value after power-up. HIGHIMM in the
serializer must be set to the same value.
SD: Disable I2S/TDM encoding to serial data to use SD as an additional control/data output valid on the
selected edge of PCLKOUT. Encrypted when HDCP is enabled (MAX9280 only).
23 DOUT28/CNTL2
Parallel Data/Auxiliary Control Signal Output Valid on the Selected Edge of PCLKOUT.
DOUT28/CNTL2 remains high impedance in 24-bit mode (BWS = low)
DOUT28 used only in 32-bit mode (BWS = high). DOUT28 not encrypted when HDCP is enabled
(MAX9280 only).
CNTL2 used only in high-bandwidth mode (BWS = open). CNTL2 not encrypted when HDCP is
enabled (MAX9280 only).
24 DOUT27/CNTL1
Parallel Data/Auxiliary Control Signal Output Valid on the Selected Edge of PCLKOUT.
DOUT27/CNTL1 remains high impedance in 24-bit mode (BWS = low)
DOUT27 used only in 32-bit mode (BWS = high). DOUT27 not encrypted when HDCP is enabled
(MAX9280 only).
CNTL1 used only in high-bandwidth mode (BWS = open). CNTL1 not encrypted when HDCP is
enabled (MAX9280 only)
25, 26,
28–31 DOUT[26:21]
Parallel Data Outputs Valid on the Selected Edge of PCLKOUT. Encrypted when HDCP is enabled
(MAX9280 only). DOUT[26:21] used only in 32-bit and high-bandwidth modes (BWS = high or open).
DOUT[26:21] remains high-impedance in 24-bit mode.
27, 44 IOVDD I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass IOVDD to EP with 0.1µF and 0.001µF
capacitors as close as possible to the device with the smallest value capacitor closest to IOVDD.
32 DOUT20/DE
Parallel Data/Device Enable Output Valid on the Selected Edge of PCLKOUT. Defaults to parallel data
output on power-up.
Device enable output when HDCP is enabled (MAX9280 only) or when in high-bandwidth mode (BWS
= open).
33 DOUT19/VS
Parallel Data/Vertical Sync Output Valid on the Selected Edge of PCLKOUT. Defaults to parallel data
output on power-up.
Vertical sync output when HDCP is enabled (MAX9280 only) or when in high-bandwidth mode (BWS =
open).
34 DOUT18/HS
Parallel Data/Horizontal Sync Output Valid on the Selected Edge of PCLKOUT. Defaults to parallel data
output on power-up.
Horizontal sync output when HDCP is enabled (MAX9280 only) or when in high-bandwidth mode (BWS
= open).
Pin Description (continued)
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
www.maximintegrated.com Maxim Integrated
│
19
PIN NAME FUNCTION
35, 36,
38–43,
45–54
DOUT[17:0] Parallel Data Outputs Valid on the Selected Edge of PCLKOUT. Encrypted when HDCP is enabled
(MAX9280 only)
37 PCLKOUT Parallel Clock Output Used for DOUT[28:0]. Latches parallel data into the input of another device.
56 CX/TP Three-Level Coax/Twisted Pair Select Input. See Table 10 for function.
— EP Exposed Pad. EP is internally connected to device ground. MUST connect EP to the PCB ground plane
through an array of vias for proper thermal and electrical performance.
8b/10b OR
9b10b
DECODE
DESCRAMBLE
SERIAL
TO
PARALLEL
MAX9276
MAX9280
REVERSE
CONTROL
CHANNEL
HDCP
DECRYPT
(MAX9280
ONLY)
HDCP
DECRYPT
CONTROL ADD[2:0]
UART/I
2
C
GPIO_GPISD/HIMINTOUT/
ADD2
SCK WS TX/
SCL
RX/
SDA
I2CSEL PWDN MS BWS
HDCP
KEYS
RGB
HS
VS
DE
HS
VS
DE
ACB
CNTL[3:0]
(9b10b)
DOUT[28:27]
(30-BIT)
FCC
HDCP
CONTROL
I
2
S/TDM
ADD[2:0]
FIFO
CONTROL
(9b10b)
DATA
DESCRIPTION
REGISTERS
SYNC
VIDEO
CLKDIV
SSPLL CDRPLL
CNTL0, CNTL3
(9b10b)
CNTL[2:1]
(9b10b)
DOUT[28:27]
(30-BIT)
CNTL0/ADD0
CNTL3/ADD1
DOUT27/CNTL1
DOUT28/CNTL2
DOUT19/VS
DOUT18/HS
DOUT[26:21]
DOUT[17:0]
PCLKOUT
ENABLE
DOUT20/DE
RGB[23:18]
(30-BIT OR 9b10b)
RGB[17:0]
CML RX
AND EQ
CX/
TP
IN+
IN-
TX
Pin Description (continued)
Functional Diagram
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
www.maximintegrated.com Maxim Integrated
│
20
Figure 1. Reverse Control Channel Output Parameters
Figure 2. Test Circuit for Differential Input Measurement Figure 2a. Test Circuit for Single-Ended Input Measurement
MAX9276
MAX9280
REVERSE
CONTROL-CHANNEL
TRANSMITTER
IN+
IN-
IN-
IN+
IN+
IN-
VOD
RL/2
RL/2
VCMR
VCMR
VROH
(IN+) - (IN-)
tR
0.1 x VROL
0.9 x VROL
t
F
VROL
0.9 x VROH
0.1 x VROH
VIN+
RL/2
RL/2
CIN
CIN
VID(P)
IN+
IN-
VID(P) = | VIN+ - VIN- |
VCMR = (VIN+ + VIN-)/2
VIN-
_
+
_
_
+
C
IN
49.9Ω
+
-
V
IN_
IN_
V
IS(P)
0.22µF
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
www.maximintegrated.com Maxim Integrated
│
21
Figure 3. Worst-Case Pattern Output
Figure 4. I2C Timing Parameters
Figure 5. Parallel Clock Output Requirements
PCLKOUT
DOUT_
NOTE: PCLKOUT PROGRAMMED FOR RISING LATCH EDGE.
PROTOCOL
SCL
SDA
START
CONDITION
(S)
BIT 7
MSB
(A7)
BIT 6
(A6)
BIT 0
(R/W)
ACKNOWLEDGE
(A)
STOP
CONDITION
(P)
VIOVDD x 0.7
VIOVDD x 0.3
VIOVDD x 0.7
VIOVDD x 0.3
tSU;STA tLOW tHIGH
tBUF
tHD;STA
tr
tSP
tf
tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO
1/fSCL
VOL MAX
tHIGH
tLOW
tT
VOH MIN
PCLKOUT
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
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22
Figure 6. Output Rise-and-Fall Times
Figure 7. Deserializer Delay
Figure 8. GPI-to-GPO Delay
0.8 x VI0VDD
0.2 x VI0VDD
tF
tR
CL
SINGLE-ENDED OUTPUT LOAD
FIRST BIT
IN+/-
DOUT_
PCLKOUT
LAST BIT
SERIAL WORD N
SERIAL-WORD LENGTH
SERIAL WORD N+1 SERIAL WORD N+2
tSD
PARALLEL WORD N-2 PARALLEL WORD N-1 PARALLEL WORD N
NOTE: PCLKOUT PROGRAMMED FOR RISING LATCHING EDGE.
tGPIO tGPIO
VOH_MIN
VOL_MAX
VIH_MIN
VIL_MAX
DESERIALIZER
GPI
SERIALIZER
GPO
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
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Detailed Description
The MAX9276/MAX9280 deserializers, when paired with
the MAX9275/MAX9277/MAX9279/MAX9281 serializers,
provides the full set of operating features, but is back-
ward-compatible with the MAX9249–MAX9270 family of
gigabit multimedia serial link (GMSL) devices, and have
basic functionality when paired with any GMSL device.
The MAX9280 has high-bandwidth digital content protec-
tion (HDCP) while the MAX9276 does not.
The deserializer has a maximum serial-bit rate of 3.12Gbps
for up to 15m of cable and operates up to a maximum out-
put clock of 104MHz in 24-bit mode and 27-bit high-band-
width mode, or 78MHz in 32-bit mode. This bit rate and
output flexibility support a wide range of displays, from
QVGA (320 x 240) to 1920 x 720 and higher with 24-bit
color, as well as megapixel image sensors. An encoded
audio channel supports L-PCM I2S stereo and up to eight
channels of L-PCM in TDM mode. Sample rates of 32kHz
to 192kHz are supported with sample depth from 8 to 32
bits. Input equalization, combined with GMSL serializer
pre/deemphasis, extends the cable length and enhances
link reliability
The control channel enables a µC to program the serial-
izer and deserializer registers and program registers on
peripherals. The control channel is also used to perform
HDCP functions (MAX9280 only). The µC can be located
at either end of the link, or when using two µCs, at both
ends. Two modes of control-channel operation are avail-
able. Base mode uses either I2C or GMSL UART protocol,
while bypass mode uses a user-defined UART protocol.
UART protocol allows full-duplex communication, while
I2C allows half-duplex communication.
Spread spectrum is available to reduce EMI on the paral-
lel output. The serial input complies with ISO 10605 and
IEC 61000-4-2 ESD protection standards.
Register Mapping
Registers set the operating conditions of the deserializers
and are programmed using the control channel in base
mode. The MAX9276/MAX9280 holds its own device
address and the device address of the serializer it is
paired with. Similarly, the serializer holds its own device
address and the address of the MAX9276/MAX9280.
Whenever a device address is changed be sure to write
the new address to both devices. The default device
address of the deserializer is set by the ADD[2:0] and
CX/TP inputs (see Table 1). Registers 0x00 and 0x01 in
both devices hold the device addresses.
Figure 9. Lock Time
Figure 10. Power-Up Delay
Figure 11. Output I2S Timing Parameters
WS
tDVA
tDVB tDVA
tF
tDVB
tR
SCK
SD
IN+ - IN-
LOCK
tLOCK
PWDN MUST BE HIGH
VOH
IN+/-
LOCK
tPU
PWDN
VOH
VIH1
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
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Output Bit Map
The output bit width depends on settings of the bus width
(BWS) pin. Table 2 lists the bit map. Unused output bits
are pulled low.
Serial Link Signaling and Data Format
The serializer uses differential CML signaling to drive twist-
ed-pair cable and single-ended CML to drive coaxial cable
with programmable pre/deemphasis and AC-coupling.
The deserializer uses AC-coupling and programmable
channel equalization.
Input data is scrambled and then 8b/10b coded (9b10b
in high-bandwidth mode). The deserializer recovers the
embedded serial clock, then samples, decodes, and
descrambles the data. In 24-bit mode, the first 21 bits
contain video data. In 32-bit mode, the first 29 bits contain
video data. In high-bandwidth mode, the first 24 bits con-
tain video data, or special control signal packets. The last
3 bits contain the embedded audio channel, the embed-
ded forward control channel, the parity bit of the serial
word (Figure 12, Figure 13).
Table 1. Device Address Defaults (Register 0x00, 0x01)
*X = 0 for the serializer address, X = 1 for the deserializer address
**CX/TP determine the serial cable type CX/TP = open addresses only for coax mode.
PIN DEVICE ADDRESS
(BIN)
SERIALIZER
DEVICE
ADDRESS
(hex)
DESERIALIZER
DEVICE
ADDRESS
(hex)
CX/TP** ADD2 ADD1 ADD0 D7 D6 D5 D4 D3 D2 D1 D0
High/Low Low Low Low 1 0 0 X* 0 0 0 RW 80 90
High/Low Low Low High 10 0 X* 0 10R//W 84 94
High/Low Low High Low 1 0 0 X* 10 0 R//W 88 98
High/Low Low High High 0 10 X* 0 10R//W 44 54
High/Low High Low Low 1 1 0 X* 0 0 0 R//W C0 D0
High/Low High Low High 110 X* 0 10R//W C4 D4
High/Low High High Low 1 1 0X*10 0 R//W C8 D8
High/Low High High High 0 10X*10 0 R//W 48 58
Open Low Low Low 1 0 0 X* 0 0 X* R//W 80 92
Open Low Low High 10 0 X* 0 1X* R//W 84 96
Open Low High Low 1 0 0 X* 10 X* R//W 88 9A
Open Low High High 0 10 X* 0 1X* R//W 44 56
Open High Low Low 1 1 0 X* 0 0 X* R//W C0 D2
Open High Low High 110 X* 0 1X* R//W C4 D6
Open High High Low 1 1 0X*10 X* R//W C8 DA
Open High High High 0 10X*10 X* R//W 48 5A
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
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Table 2. Output Map
*See the High-Bandwidth Mode section for details on timing requirements.
+Outputs used only when the respective color lookup tables are enabled.
**Not encrypted when HDCP is enabled (MAX9280 only).
Figure 12. 24-Bit Mode Serial Data Format
SIGNAL OUTPUT PIN
MODE
24-BIT MODE
(BWS = LOW)
HIGH-BANDWIDTH
MODE (BWS = MID
32-BIT MODE
(BWS = HIGH)
R[5:0] DOUT[5:0] Used Used Used
G[5:0] DOUT [11:6] Used Used Used
B[5:0] DOUT [17:12] Used Used Used
HS, VS, DE DOUT18/HS, DOUT19/VS,
DOUT20/DE Used** Used** Used**
R[7:6] DOUT [22:21] Used+ Used Used
G[7:6] DOUT [24:23] Used+ Used Used
B[7:6] DOUT [26:25] Used+ Used Used
CNTL[2:1] DOUT [28:27]/CNTL[2:1] Not used Used*,** Used**
CNTL3, CNTL0 CNTL3/ADD1, CNTL0/ADD0 Not used Used*,** Not used
I2S/TDM WS, SCK, SD/HIM Used Used Used
AUX SIGNAL Used Used Used
D0
SERIAL DATA
OUTPUT PIN
OUTPUT
SIGNAL
D1
DOUT
0
R0 R1 B5 HS VS DE
DOUT
1
D17 D18
24 BITS
D19 D20 ACB
AUDIO DECODE
FORWARD
CONTROL
CHANNEL BIT
PACKET
PARITY
CHECK BIT
FCC PCB
DOUT
17
DOUT
18/HS
DOUT
19/VS
DOUT
20/DE WS SCK SD RX/
SDA
TX/
SCL
RGB DATA CONTROL BITS I2S/TDM
AUDIO
UART/I2C
MAX9280 NOTE: VS/HS MUST BE SET AT DOUT[19:18] FOR HDCP
FUNCTIONALITY.
ONLY DOUT[17:0] AND ACB HAVE HDCP DECRYPTION.
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
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Figure 13. 32-Bit Mode Serial Data Format
Figure 14. High-Bandwidth Mode Serial Data Format
D0
SERIAL DATA
OUTPUT PIN
OUTPUT
SIGNAL
D1
DOUT
0
R0 R1 B5
DOUT
1
D17 D18
DOUT
17
DOUT
18/HS
D19 D20
DOUT
19/VS
DOUT
20/DE
D21 D22
DOUT
21
DOUT
22
D23
32 BITS
D24
DOUT
23
DOUT
24
D25 D26
DOUT
25
DOUT
26
D27 D28
DOUT27/
CNTL1
DOUT28/
CNTL2 WS
ACB FCC
SCK
PCB
SD RX/
SDA
TX/
SCL
AUDIO DECODE
FORWARD
CONTROL
CHANNEL BIT
PACKET
PARITY
CHECK BIT
HS VS DE R6 R7 G6 G7 B6 B7
RGB DATA CONTROL BITS RGB DATA
MAX9280 NOTE: VS/HS MUST BE SET AT DOUT[19:18] FOR HDCP
FUNCTIONALITY.
ONLY DOUT[17:0], DOUT[26:21] AND ACB HAVE HDCP ENCRYPTION.
I2S/TDM
AUDIO
UART/I2CAUX
CONTROL
BITS
D0
SERIAL DATA D1
27 BITS
INPUT PIN DOUT
0
DOUT
1
D17 D18 D19 D20 D21 D22 D23 ACB FCC PCB
DOUT
17
DOUT
21
DOUT
22
DOUT
23
DOUT
24
DOUT
25
DOUT
26 WS SCK SD RX/
SDA
TX/
SCL
INPUT
SIGNAL R0 R1 B5 R6 R7 G6 G7 B6 B7 HS VS DE
RGB DATA RGB DATA I2S/TDM
AUDIO
UART/I2C
MAX9280 NOTE: VS/HS MUST BE SET AT DOUT[20:18].
ONLY DOUT[17:0], DOUT[26:21] AND ACB HAVE HDCP ENCRYPTION.
AUDIO DECODE
FORWARD
CONTROL
CHANNEL BIT
PACKET
PARITY
CHECK BIT
SPECIAL SERIAL DATA PACKET
CNTL0/
ADD0
DOUT27/
CNTL1
DOUT28/
CNTL2
CNTL3
ADD1
DOUT
18/HS
DOUT
19/VS
DOUT
20/DE
AUX
CONTROL
BITS
CONTROL BITS
CONTROL SIGNAL DECODING
27 BITS
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
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The deserializer uses the DRS bit and the BWS input to
set the PCLKOUT frequency range (Table 3). Set DRS = 1
for low data rate PCLKOUT frequency range of 6.25MHz
to 16.66MHz. Set DRS = 0 for high data rate PCLKOUT
frequency range of 12.5MHz to 104MHz.
High-Bandwidth Mode
The deserializer uses a 27-bit high-bandwidth mode to
support 24-bit RGB at 104MHz pixel clock. Set BWS =
open in both the serializer and deserializer to use high-
bandwidth mode. In high-bandwidth mode, the deserial-
izer decodes HS, VS, DE and CNTL[3:0] from special
packets. Packets are sent by replacing a pixel before
the rising edge and after the falling edge of the HS, VS,
and DE signals. However, for CNTL[3:0], packets always
replace a pixel before the transition of CNTL[3:0]. Keep
HS, VS, and DE low pulse widths at least 2 pixel clock
cycles. By default, CNTL[3:0] are sampled continuously
when DE is low. CNTL[3:0] are sampled only on HS/VS
transitions when DE is high. If DE triggering of encoded
packets is not desired, set the serializer’s DISDETRIG
= 0 and the CNTLTRIG bits to their desired value (reg-
ister 0x15) to change the CNTL triggering behavior. Set
DETREN = 0 on the deserializer when DE is not periodic.
Audio Channel
The audio channel supports 8kHz to 192kHz audio
sampling rates and audio word lengths from 8 bits to
32 bits (2 channel I2S) or 64 to 256 bits (TDM64 to
TDM256). The audio bit clock (SCK) does not have to be
synchronized with PCLKOUT. The serializer automatically
encodes audio data into a single-bit stream synchronous
with PCLKOUT. The deserializer decodes the audio
stream and stores audio words in a FIFO. Audio rate
detection uses an internal oscillator to continuously
determine the audio data rate and output the audio in I2S
format. The audio channel is enabled by default. When
the audio channel is disabled, the SD/HIM is treated as
an auxiliary control signal.
Since the audio data sent through the serial link is syn-
chronized with PCLKOUT, low PCLKOUT frequencies
limit the maximum audio sampling rate. Table 3 lists the
maximum audio sampling rate for various PCLKOUT fre-
quencies. Spread-spectrum settings do not affect the I2S/
TDM data rate or WS clock frequency.
Audio Channel Input
The audio channel input works with 8-channel TDM and
stereo I2S, as well as non-standard formats. The input
format is shown in Figure 15.
Table 3. Data-Rate Selection Table
Figure 15. Audio Channel Input Format
DRS BIT SETTING BWS PIN SETTING PCLKOUT RANGE (MHz)
0 (high data rate)
Low (24-bit mode) 16.66 to 104
Mid (high bandwidth mode) 36.66 to 104
High (32-bit mode) 12.5 to 78
1 (low data rate)
Low 8.33 to 16.66
Mid 18.33 to 36.66
High 6.25 to 12.5
FRAME
16 TO 256 BITS
012
SCK
SD
WS
N
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
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Table 4. Maximum Audio WS Frequency (kHz) for Various PCLKOUT Frequencies
+Max WS rate is greater than 192kHz.
*DRS = 0 PCLKOUT frequency is equal to 2x the DRS = 1 PCLKOUT frequency.
CHANNELS
BITS PER
CHANNEL
PCLKOUT FREQUENCY
(DRS = 0*)
(MHz)
12.5 15.0 16.6 20.0 25.0 30.0 35.0 40.0 45.0 50.0 100
2
8+++++++++++
16 +++++++++++
18 185.5 + + + + + + + + + +
20 174.6++++++++++
24 152.2 182.7 + + + + + + + + +
32 123.7 148.4 164.3 + + + + + + + +
4
8+++++++++++
16 123.7 148.4 164.3 + + + + + + + +
18 112.0 134.4 148.8 179.2 + + + + + + +
20 104.2 125.0 138.3 166.7 + + + + + + +
24 88.6 106.3 117.7 141.8 177.2 + + + + + +
32 69.9 83.8 92.8 111.8 139.7 167.6 + + + + +
6
8152.2 182.7 + + + + + + + + +
16 88.6 106.3 117.7 141.8 177.2 + + + + + +
18 80.2 93.3 106.6 128.4 160.5 + + + + + +
20 73.3 88.0 97.3 117.3 146.6 175.9 + + + + +
24 62.5 75.0 83.0 100 125 150 175 + + + +
32 48.3 57.9 64.1 77.2 96.5 115.9 135.2 154.5 173.8 + +
8
8123.7 148.4 164.3 + + + + + + + +
16 69.9 83.8 92.8 111.8 139.7 167.6 + + + + +
18 62.5 75.0 83.0 100.0 125.0 150.0 175.0 + + + +
20 57.1 68.5 75.8 91.3 114.2 137.0 159.9 182.7 + + +
24 48.3 57.9 64.1 77.2 96.5 115.9 135.2 154.5 173.8 + +
32 37.1 44.5 49.3 59.4 74.2 89.1 103.9 118.8 133.6 148.4 +
COLOR CODING
< 48kHz
48kHz to 96kHz
96kHz to 192kHz
> 192kHz
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
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The period of the WS can be 8 to 256 SCK periods. The
WS frame starts with the falling edge and can be low for
1 to 255 SCK periods. SD is one SCK period, sampled
on the rising edge. MSB/LSB order, zero padding or any
other significance assigned to the serial data does not
affect operation of the audio channel. The polarity for WS
and SCK edges is programmable.
Figure 16, Figure 17, Figure 18, and Figure 19 are exam-
ples of acceptable input formats.
Figure 16. 8-Channel TDM (24-Bit Samples, Padded With Zeros)
Figure 17. 6-Channel TDM (24-Bit Samples, No Padding)
Figure 18. Stereo I2S (24-Bit Samples, Padded With Zeros)
WS
SCK
SD CH1
32 SCK
CH2 CH3 CH4 CH5
256 SCK
CH6 CH7 CH8
MSB 24-BIT DATA
LSB 8 BITS ZERO
WS
SCK
SD CH1 CH2 CH3 CH4 CH5 CH6
24 SCK
24-BIT DATA
144 SCK
32 SCK
64 SCK
LEFT CHANNEL RIGHT CHANNEL
WS
SCK
SD
MSB 24-BIT DATA
LSB 8 BITS ZERO
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
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Audio Channel Output
WS, SCK, and SD are output with the same timing rela-
tionship they had at the audio input, except that WS is
always 50% duty cycle (regardless of the duty cycle of
WS at the input).
The output format is shown in Figure 20.
WS and SCK can be driven by the audio source (clock
master) or the audio sink (clock slave). Buffer underflow
and overflow flags are available to the sink as clock slave
via I2C for clock frequency adjustment. Data are sampled
on the rising edge. WS and SCK polarity is programmable.
Figure 19. Stereo I2S (16-Bit Samples, No Padding)
Figure 20. Audio Channel Output Format
32 SCK
LEFT CHANNEL RIGHT CHANNEL
16 SCK
16-BIT DATA
WS
SCK
SD
I2S TDM 256
SCK
SD/HIM
WS
SCK
SD/HIM
WS
8 TO 32 BITS 256 BITS
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
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Additional MCLK Output for Audio Applications
Some audio DACs, such as the MAX9850, do not
require a synchronous main clock (MCLK), while other
DACs require a separate MCLK for operation. For audio
applications that cannot use WS or PCLKOUT directly,
the deserializer provides a divided MCLK output at
either DOUT28/CNTL2 or CNTL0/ADD0 (determined by
MCLKPIN bit setting) at the expense of one less control
line. By default, MCLK is turned off. Set MCLKDIV (dese-
rializer register 0x12, D[6:0]) to a nonzero value to enable
the MCLK output. Set MCLKDIV to 0x00 to disable MCLK
and set DOUT28/CNTL2 or CNTL0/ADD0 as a control
output.
The output MCLK frequency is:
SRC
MCLK
f
f
MCLKDIV
=
where:
fSRC is the MCLK source frequency (see Table 5)
MCLKDIV is the divider ratio from 1 to 127
Choose MCLKDIV values so that fMCLK is not greater
than 60MHz. MCLK frequencies derived from PCLKOUT
(MCLKSRC = 0) are not affected by spread-spectrum
settings in the deserializer. Enabling spread spectrum
in the serializer, however, introduces spread spectrum
into MCLK. Spread-spectrum settings of either device
do not affect MCLK frequencies derived from the internal
oscillator. The internal oscillator frequency ranges
from 100MHz to 150MHz over all process corners and
operating conditions. Alternatively, set MCLKWS = 1
(0x15 D1) to output WS from MCLK.
Audio Output Timing Sources
The deserializer has multiple options for audio data output
timing. By default, the deserializer provides the output
timing based on the incoming data rate (through a FIFO)
and an internal oscillator.
To use a system sourced clock, set the AUDIOMODE bit
to 1 (D5 of register 0x02) to set WS and SCK as inputs
on the deserializer side. The deserializer uses a FIFO to
smooth out the differences in input and output audio tim-
ing. Registers 0x78 and 0x79 store the FIFO overflow/
underflow information for use with external WS/SCK tim-
ing. The FIFO drops data packets during FIFO overflow.
By default, the FIFO repeats the last audio packet during
FIFO underflow when no audio data is available. Set the
AUDUFBEH bit (D2 of register 0x01D) to 1 to output all
zeroes during underflow.
Reverse Control Channel
The serializer uses the reverse control channel to receive
I2C/UART and GPO signals from the deserializer in
the opposite direction of the video stream. The reverse
control channel and forward video data coexist on the
same serial cable forming a bidirectional link. The reverse
control channel operates independently from the forward
control channel. The reverse control channel is available
2ms after power-up. The serializer temporarily disables
the reverse control channel for 500µs after starting/
stopping the forward serial link.
Table 5. fSRC Settings
*MCLK is not divided when using WS as the MCLK source. MCLK divider must still be set to a nonzero number for MCLK to be
enabled.
MCLKWS SETTING
(REGISTER 0x15, D1)
MCLKSRC SETTING
(REGISTER 0x12, D7)
DATA RATE
SETTING BIT-WIDTH SETTING MCLK SOURCE
FREQUENCY (fSRC)
0
0
High speed
(DRS = 0)
24-bit or high-bandwidth mode 3 x fCLKOUT
32-bit mode 4 x fCLKOUT
Low speed
(DRS = 1)
24-bit or high-bandwidth mode 6 x fCLKOUT
32-bit mode 8 x fCLKOUT
1 — — Internal oscillator
(120MHz typ)
1 — — — WS*
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
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32
Control Channel and Register Programming
The control channel is available for the µC to send and
receive control data over the serial link simultaneously
with the high-speed data. The µC controls the link from
either the serializer or the deserializer side to support
video-display or image-sensing applications. The control
channel between the µC and serializer or deserializer
runs in base mode or bypass mode according to the
mode selection (MS) input of the device connected to the
µC. Base mode is a half-duplex control channel and the
bypass mode is a full-duplex control channel. The total
maximum forward or reverse control channel delay is 2µs
(UART) or 2-bit times (I2C) from the input of one device
to the output of the other. I2C delay is measured from a
START condition to START condition.
UART Interface
In base mode, the µC is the host and can access the
registers of both the serializer and deserializer from either
side of the link using the GMSL UART protocol. The µC
can also program the peripherals on the remote side by
sending the UART packets to the serializer or deserializer,
with the UART packets converted to I2C by the device
on the remote side of the link. The µC communicates
with a UART peripheral in base mode (through INTTYPE
register settings), using the half-duplex default GMSL
UART protocol of the serializer/deserializer. The device
addresses of the serializer and deserializer in base mode
are programmable.
When the peripheral interface is I2C, the serializer/
deserializer converts UART packets to I2C that have
device addresses different from those of the serializer or
deserializer. The converted I2C bit rate is the same as the
original UART bit rate.
The deserializer uses differential line coding to send sig-
nals over the reverse channel to the serializer. The bit rate
of the control channel is 9.6kbps to 1Mbps in both direc-
tions. The serializer and deserializer automatically detect
the control-channel bit rate in base mode. Packet bit rate
changes can be made in steps of up to 3.5 times higher
or lower than the previous bit rate. See the Changing the
Clock Frequency section for more information.
Figure 21 shows the UART protocol for writing and read-
ing in base mode between the µC and the serializer/
deserializer.
Figure 22 shows the UART data format. Even parity is
used. Figure 23 and Figure 24 detail the formats of the
SYNC byte (0x79) and the ACK byte (0xC3). The µC and
the connected slave chip generate the SYNC byte and
ACK byte, respectively. Events such as device wake-up
and GPI generate transitions on the control channel that
can be ignored by the µC. Data written to the deserial-
izer registers do not take effect until after the acknowl-
edge byte is sent. This allows the µC to verify that write
commands are received without error, even if the result
of the write command directly affects the serial link. The
slave uses the SYNC byte to synchronize with the host
UART’s data rate. If the GPI or MS inputs of the deserial-
izer toggle while there is control-channel communication,
or if a line fault occurs, the control-channel communica-
tion will be corrupted. In the event of a missed or delayed
acknowledge (~1ms due to control channel timeout), the
µC should assume there was an error in the packet. In
base mode, the µC must keep the UART Tx/Rx lines high
no more than 4 bit times between bytes in a packet. Keep
the UART Rx/Tx lines high for at least 16 bit times before
starting to send a new packet.
Figure 21. GMSL UART Protocol for Base Mode
WRITE DATA FORMAT
SYNC DEV ADDR + R/W REG ADDR NUMBER OF BYTES
SYNC DEV ADDR + R/W REG ADDR NUMBER OF BYTES BYTE 1 BYTE N
ACK
BYTE NBYTE 1ACK
MASTER READS FROM SLAVE
READ DATA FORMAT
MASTER WRITES TO SLAVE
MASTER WRITES TO SLAVE
MASTER READS FROM SLAVE
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
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As shown in Figure 25, the remote-side device converts
packets going to or coming from the peripherals from
UART format to I2C format and vice versa. The remote
device removes the byte number count and adds or
receives the ACK between the data bytes of I2C. The I2C
bit rate is the same as the UART bit rate.
Figure 22. GMSL UART Data Format for Base Mode
Figure 25. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 0)
Figure 23. Sync Byte (0x79) Figure 24. ACK Byte (0xC3)
START D0 D1 D2 D3 D4 D5 D6 D7 PARITY STOP
1 UART FRAME
FRAME 1 FRAME 2 FRAME 3
STOPBASE MODE USES EVEN PARITY START STOP START
START
D0
10011110
D1 D2 D3 D4 D5 D6 D7
PARITY STOP START
D0
11000011
D1 D2 D3 D4 D5 D6 D7
PARITY STOP
11
SYNC FRAME REGISTER ADDRESS NUMBER OF BYTESDEVICE ID + WR DATA 0
DEV ID A
11 11 11 11
DATA N
11 11
S
1 11
ACK FRAME
7
: MASTER TO SLAVE
8
SERIALIZER/DESERIALIZER PERIPHERAL
W
1
REG ADDR
8
A
1 1 8 1
11
SYNC FRAME REGISTER ADDRESS NUMBER OF BYTESDEVICE ID + RD
11 11 11 11
ACK FRAME DATA 0
11
DATA N
11
UART-TO-I2C CONVERSION OF WRITE PACKET (I2CMETHOD = 0)
UART-TO-I2C CONVERSION OF READ PACKET (I2CMETHOD = 0)
S: START P: STOP A: ACKNOWLEDGE
: SLAVE TO MASTER
DATA 0 ADATA N A P
DEV ID AS
1 17
W
1
DEV ID AS
1 17
R
1
DATA N P
18
A
1
DATA 0
8
A
1
REG ADDR
8
A
1
µC SERIALIZER/DESERIALIZER
µC SERIALIZER/DESERIALIZER
SERIALIZER/DESERIALIZER PERIPHERAL
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
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Interfacing Command-Byte-Only I2C Devices with
UART
The deserializers’ UART-to-I2C conversion can interface
with devices that do not require register addresses, such
as the MAX7324 GPIO expander. In this mode, the I2C
master ignores the register address byte and directly reads/
writes the subsequent data bytes (Figure 26). Change
the communication method of the I2C master using the
I2CMETHOD bit. I2CMETHOD = 1 sets command-byte-
only mode, while I2CMETHOD = 0 sets normal mode
where the first byte in the data stream is the register
address.
UART Bypass Mode
In bypass mode, the deserializers ignore UART com-
mands from the µC and the µC communicates with the
peripherals directly using its own defined UART protocol.
The µC cannot access the serializer/deserializer’s reg-
isters in this mode. Peripherals accessed through the
forward control channel using the UART interface need
to handle at least one PCLKOUT period ±10ns of jitter
due to the asynchronous sampling of the UART signal
by PCLKOUT. Set MS/HVEN = high to put the control
channel into bypass mode. For applications with the µC
connected to the deserializer, there is a 1ms wait time
between setting MS high and the bypass control channel
being active. There is no delay time when switching to
bypass mode when the µC is connected to the serial-
izer. Do not send a logic-low value longer than 100µs to
ensure proper GPO functionality. Bypass mode accepts
bit rates down to 10kbps in either direction. See the
GPO/GPI Control section for GPI functionality limitations.
The control-channel data pattern should not be held low
longer than 100µs if GPI control is used.
Figure 26. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 1)
: MASTER TO SLAVE
SERIALIZER/DESERIALIZER
SERIALIZER/DESERIALIZER
SERIALIZER/DESERIALIZER
UART-TO-I2C CONVERSION OF READ PACKET (I2CMETHOD = 1)
UART-TO-I2C CONVERSION OF WRITE PACKET (I2CMETHOD = 1)
µC
SERIALIZER/DESERIALIZERµC
SYNC FRAME
11 11 11 11 11 11 11
1111 11 11 11 11 11
DEVICE ID + RD REGISTER ADDRESS NUMBER OF BYTES
SYNC FRAME DEVICE ID + WR REGISTER ADDRESS NUMBER OF BYTES DATA 0 DATA N ACK FRAME
ACK FRAME DATA 0 DATA N
DATA NADATA 0W ADEV IDS A P
PERIPHERAL
PERIPHERAL
S
1 1 1 8
8 81111 7 1 1
8
1 1 17
DEV ID R A A A PDATA 0 DATA N
: SLAVE TO MASTER S: START P: STOP A: ACKNOWLEDGE
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
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I2C Interface
In I2C to I2C mode, the deserializer’s control channel
interface sends and receives data through an I2C-
compatible 2-wire interface. The interface uses a serial-
data line (SDA) and a serial-clock line (SCL) to achieve
bidirectional communication between master and slave(s).
A µC master initiates all data transfers to and from the
device and generates the SCL clock that synchronizes
the data transfer. When an I2C transaction starts on the
local side device’s control channel port, the remote side
device’s control channel port becomes an I2C master
that interfaces with remote side I2C peripherals. The I2C
master must accept clock-stretching which is imposed by
the deserializer (holding SCL LOW) The SDA and SCL
lines operate as both an input and an open-drain output.
Pullup resistors are required on SDA and SCL. Each
transmission consists of a START condition (Figure 4)
sent by a master, followed by the device’s 7-bit slave
address plus a R/W bit, a register address byte, one or
more data bytes, and finally a STOP condition.
START and STOP Conditions
Both SCL and SDA remain high when the interface is not
busy. A master signals the beginning of a transmission
with a START (S) condition by transitioning SDA from high
to low while SCL is high (see Figure 27). When the mas-
ter has finished communicating with the slave, it issues
a STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission.
Bit Transfer
One data bit is transferred during each clock pulse
(Figure 28). The data on SDA must remain stable while
SCL is high.
Figure 27. START and STOP Conditions
Figure 28. Bit Transfer
SDA
SCL
START
CONDITION
STOP
CONDITION
S P
SDA
SCL
DATA LINE STABLE;
DATA VALID
CHANGE OF DATA
ALLOWED
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
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Acknowledge
The acknowledge bit is a clocked 9th bit that the recipient
uses to handshake receipt of each byte of data (Figure 29).
Thus, each byte transferred effectively requires nine bits.
The master generates the 9th clock pulse, and the recipi-
ent pulls down SDA during the acknowledge clock pulse.
The SDA line is stable low during the high period of the
clock pulse. When the master is transmitting to the slave
device, the slave device generates the acknowledge bit
because the slave device is the recipient. When the slave
device is transmitting to the master, the master generates
the acknowledge bit because the master is the recipient.
The device generates an acknowledge even when the
forward control channel is not active. To prevent acknowl-
edge generation when the forward control channel is not
active, set the I2CLOCACK bit low.
Slave Address
The deserializers have 7-bit long slave addresses. The
bit following a 7-bit slave address is the R/W bit, which is
low for a write command and high for a read command.
The slave address for the deserializer is XX01XXX1 for
read commands and XX01XXX0 for write commands.
See Figure 30.
Bus Reset
The device resets the bus with the I2C START condition
for reads. When the R/W bit is set to 1, the deserializers
transmit data to the master, thus the master is reading
from the device.
Figure 29. Acknowledge
Figure 30. Slave Address
SCL
SDA
BY
TRANSMITTER
CLOCK PULSE FOR
ACKNOWLEDGE
START
CONDITION
SDA
BY
RECEIVER
1 2 8 9
S
SDA XACK
SCL
MSB LSB
XX R/W
0 1 X X
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
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Format for Writing
Writes to the deserializers comprise the transmission of
the slave address with the R/W bit set to zero, followed by
at least one byte of information. The first byte of informa-
tion is the register address or command byte. The register
address determines which register of the device is to be
written by the next byte, if received. If a STOP (P) condi-
tion is detected after the register address is received, the
device takes no further action beyond storing the register
address (Figure 31). Any bytes received after the register
address are data bytes. The first data byte goes into the
register selected by the register address, and subsequent
data bytes go into subsequent registers (Figure 32). If
multiple data bytes are transmitted before a STOP con-
dition, these bytes are stored in subsequent registers
because the register addresses autoincrements.
Figure 31. Format for I2C Write
Figure 32. Format for Write to Multiple Registers
S 1 0 0 0
ADDRESS = 0x80
0 = WRITE
0 0 0 0 A 0 0 0 0
REGISTER ADDRESS = 0x00
0 0 0 0 A PD7 D6 D5 D4
REGISTER 0x00 WRITE DATA
D3 D2 D1 D0 A
S = START BIT
P = STOP BIT
A = ACK
D_ = DATA BIT
S = START BIT
P = STOP BIT
A = ACK
N = NACK
D_ = DATA BIT
S 1 0 0 0
ADDRESS = 0x80
0 = WRITE
0 0 0 0 A 0 0 0 0
REGISTER ADDRESS = 0x00
0 0 0 0 A
D7 D6 D5 D4
REGISTER 0x00 WRITE DATA
D3 D2 D1 D0 A D7 PD6 D5 D4
REGISTER 0x01 WRITE DATA
D3 D2 D1 D0 N
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
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Format for Reading
The deserializers are read using the internally stored
register address as an address pointer, the same way the
stored register address is used as an address pointer for
a write. The pointer autoincrements after each data byte
is read using the same rules as for a write. Thus, a read
is initiated by first configuring the register address by
performing a write (Figure 33). The master can now read
consecutive bytes from the device, with the first data byte
being read from the register address pointed by the previ-
ously written register address. Once the master sends a
NACK, the device stops sending valid data.
I2C Communication with Remote Side Devices
The deserializers support I2C communication with a
peripheral on the remote side of the communication link
using SCL clock stretching. While multiple masters can
reside on either side of the communication link, arbitration
is not provided. The connected masters need to support
SCL clock stretching. The remote side I2C bit rate range
must be set according to the local side I2C bit rate.
Supported remote side bit rates can be found in Table 6.
Set the I2CMSTBT (register 0x1C) to set the remote I2C
bit rate. If using a bit rate different from 400kbps, local and
remote side I2C setup and hold times should be adjusted
by setting the I2CSLVSH register settings on both sides.
I2C Address Translation
The deserializers support I2C address translation for up to
two device addresses. Use address translation to assign
unique device addresses to peripherals with limited
I2C addresses. Source addresses (address to translate
from) are stored in registers 0x18 and 0x1A. Destination
addresses (address to translate to) are stored in registers
0x19 and 0x1B.
In a multilink situation where there are multiple deserial-
izers and/or peripheral devices connected to these serial-
izers, the deserializers support broadcast commands to
control these multiple devices. Select an unused device
address to use as a broadcast device address. Program
all the remote side serializer devices to translate the
broadcast device address (source address stored in reg-
isters 0x0F, 0x11) to the peripherals’ address (destination
address stored in registers 0x10, 0x12). Any commands
sent to the broadcast address (selected unused address)
will be sent to all deserializers and/or peripheral devices
connected to the deserializers whose addresses match
the translated broadcast address.
Figure 33. Format for I2C Read
Table 6. I2C Bit Rate Ranges
LOCAL BIT RATE REMOTE BIT RATE RANGE I2CMSTBT SETTING
f > 50kbps Up to 1Mbps ANY
20kbps > f > 50kbps Up to 400kbps Up to 110
f < 20kbps Up to 10kbps 000
S = START BIT
P = STOP BIT
A = ACK
N = NACK
D_ = DATA BIT
S
S
1 0 0 0
ADDRESS = 0x80
0 = WRITE
0 0 0 0 A
1 = READ
REPEATED START
0 0 0 0
REGISTER ADDRESS = 0x00
0 0 0 0 A
1 0 0 0
ADDRESS = 0x81
0 0 0 1 A D7 PD6 D5 D4
REGISTER 0x00 READ DATA
D3 D2 D1 D0 N
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
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GPO/GPI Control
GPO on the serializer follows GPI transitions on the dese-
rializer. This GPO/GPI function can be used to transmit
signals such as a frame sync in a surround-view camera
system. The GPI to GPO delay is 0.35ms max. Keep
time between GPI transitions to a minimum 0.35ms. This
includes transitions from the other deserializer in coax
splitter mode. Bit D4 of register 0x06 in the deserializer
stores the GPI input state. GPO is low after power-up.
The µC can set GPO by writing to the SETGPO register
bit. Do not send a logic-low value on the deserializer RX/
SDA input (UART mode) longer than 100µs in either base
or bypass mode to ensure proper GPO/GPI functionality.
Line Equalizer
The deserializer includes an adjustable line equalizer to
further compensate cable attenuation at high frequencies.
The cable equalizer has 11 selectable levels of com-
pensation from 2.1dB to 13dB (Table 7). To select other
equalization levels, set the corresponding register bits
in the deserializer (0x05 D[3:0]). Use equalization in the
deserializer, together with preemphasis in the serializer, to
create the most reliable link for a given cable.
Spread Spectrum
To reduce the EMI generated by the transitions on
the serial link, the deserializer output is programmable
for spread spectrum. If the serializer, paired with the
MAX9276/MAX9280, has programmable spread spec-
trum, do not enable spread for both at the same time or
their interaction will cancel benefits. The deserializer will
track the serializer spread and will pass the spread to the
deserializer output. The programmable spread-spectrum
amplitudes are ±2%,and ±4% (Table 8).
The deserializer includes a sawtooth divider to control the
spread modulation rate. Autodetection of the PCLKOUT
operation range guarantees a spread-spectrum modu-
lation frequency within 20kHz to 40kHz. Additionally,
manual configuration of the sawtooth divider (SDIV: 0x03,
D[5:0]) allows the user to set a modulation frequency
according to the PCLKOUT frequency. When ranges are
manually selected, program the SDIV value for a fixed
modulation frequency around 20kHz.
Manual Programming of the Spread-Spectrum
Divider
The modulation rate relates to the PCLKOUT frequency
as follows:
( )
PCLKOUT
M
f
f 1 DRS
MOD SDIV
= +
×
where:
fM = Modulation frequency
DRS = DRS value (0 or 1)
fPCLKOUT = PCLKOUT frequency
MOD = Modulation coefficient given in Table 9
SDIV = 5-bit SDIV setting, manually programmed by the µC
To program the SDIV setting, first look up the modulation
coefficient according to the desired bus-width and spread-
spectrum settings. Solve the above equation for SDIV
using the desired pixel clock and modulation frequencies.
If the calculated SDIV value is larger than the maximum
allowed SDIV value in Table 9, set SDIV to the maximum
value.
Table 7. Cable Equalizer Boost Levels
Table 8. Output Spread
Table 9. Modulation Coefficients and
Maximum SDIV Settings
BOOST SETTING
(0x05 D[3:0]) TYPICAL BOOST GAIN (dB)
0000 2.1
0001 2.8
0010 3.4
0011 4.2
0100 5.2
0101 6.2
0110 7
0111 8.2
1000 9.4
1001 10.7
Power-up default
1010 11.7
1011 13
SS SPREAD (%)
00 No spread spectrum. Power-up default
01 ±2% spread spectrum.
10 No spread spectrum
11 ±4% spread spectrum
SPREAD-
SPECTRUM
SETTING (%)
MODULATION
COEFFICIENT
MOD (DECIMAL)
SDIV UPPER
LIMIT (DECIMAL)
4208 15
2 208 30
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
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HS/VS/DE Tracking
The deserializer has tracking to filter out HS/VS/DE bit or
packet errors. HS/VS/DE tracking is on by default when
the device is in high-bandwidth mode (BWS = open),
and off by default when in 24-bit or 32-bit mode (BWS =
low or high). Set/clear HVTREN (D6 of register 0x15) to
enable/disable HS/VS tracking. Set/clear DETREN (D5 of
register 0x15) to enable/disable DE tracking. By default,
the device uses a partial and full periodic tracking of
HS/DE. Set HVTRMODE = 0 (D4 of register 0x15) to
disable full periodic tracking. HS/VS/DE tracking can be
turned on in 24-bit and 32-bit modes to track and correct
against bit errors in HS/VS/DE link bits.
Serial Input
The device can receive serial data from two kinds of
cable: 100Ω twisted pair and 50Ω coax. (Contact the fac-
tory for devices compatible with 75Ω cables).
Coax Splitter Mode
In coax mode, OUT+ and OUT- of the serializer are active.
This enables the use as a 1:2 splitter (Figure 34). In coax
mode, connect OUT+ to IN+ of the deserializer. Connect
OUT- to IN- of the second deserializer. Control channel
data is broadcast from the serializer to both deserializers
and their attached peripherals. Assign a unique address
to send control data to one deserializer. Leave all unused
IN_ pins unconnected, or connect them to ground through
50Ω and a capacitor for increased power-supply rejection.
If OUT- is not used, connect OUT- to VDD through a 50Ω
resistor (Figure 35). When there are µCs at the serializer,
and at each deserializer, only one µC can communicate
at a time. Disable forward and reverse channel links
according to the communicating deserializer connection
to prevent contention in I2C to I2C mode. Use ENREVP
or ENREVN register bits to disable/enable the control
channel link. In UART mode, the serializer provides
arbitration of the control channel link.
Cable Type Conguration Input
CX/TP determine the power-up state of the serial input.
In coax mode, CX/TP also determine which coax input is
active, along with the default device address (Table 10).
Figure 34. 2:1 Coax Splitter Connection Diagram
Figure 35. Coax Connection Diagram
Table 10. Configuration Input Map
CX/TP FUNCTION
High Coax+ input. 7-bit device address is XXXXXX0 (bin).
Mid Coax- input. 7-bit device address is XXXXXX1 (bin).
Low Twisted pair input. 7-bit device address is
XXXXXX0 (bin).
OUT+
OUT-
OPTIONAL
COMPONENTS
FOR INCREASED
POWER-SUPPLY
REJECTION
IN+
IN-
IN+
IN-
MAX9276
MAX9280
MAX9276
MAX9280
GMSL
SERIALIZER
OUT+
OUT-
IN+
OPTIONAL COMPONENTS FOR
INCREASED POWER-SUPPLY
REJECTION
IN-
AVDD
50Ω
MAX9276
MAX9280
GMSL
SERIALIZER
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
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41
Color Lookup Tables
The deserializer includes 3 color lookup tables (LUT) to
support automatic translation of RGB pixel values. This
feature can be used for color gamma correction, bright-
ness/contrast or for other purposes. There are 3 lookup
tables, each 8 bits wide and 256 entries deep, enabling a
1 to 1 translation of 8-bit input values to any 8-bit output
value for each color (24-bits total).
Programming and Verifying LUT Data
The µC must set the LUTPROG register bit to 1 before
programming and verifying the tables. To program a LUT,
the µC generates a write packet with register address
set to the assigned register address for respective LUT
(0x7D, 0x7E, or 0x7F). The deserializer writes data in
the packet to the respective LUT starting from the LUT
address location set in LUTADDR register. Successive
bytes in the data packet are written to the next LUT
address location, however each new data packet write
starts from the address location stored in the LUTADDR
register. Use 0x00 for LUTADDR and 0x00 as the number
of bytes field in UART packet, when writing a 256 byte
data-block, because 8-bit wide number of bytes field
cannot normally represent 9-bit wide “256” value. There
is no number of bytes field in I2C-to-I2C modes.
To readback the contents of an LUT, the µC generates
a read packet with register address set to the assigned
register address for respective LUT (0x7D, 0x7E, or
0x7F). the deserializer outputs read data from the respec-
tive LUT starting from the LUT address location set in
LUT_ADDR register. Similar to the write operation, use
0x00 for LUTADDR and 0x00 as the number of bytes field
in UART packet, when reading a 256-byte data block.
LUT Color Translation
After power-up or going out of sleep or power-down
modes, LUT translation is disabled and LUT contents
are unknown. After program and verify operations
are finished, in order to enable LUT translations, set
LUTPROG bit to 0 and set the respective LUT enable bits
(RED_LUT_EN, GRN_LUT_EN, BLU_LUT_EN) to 1 to
enable the desired LUT translation function. Only the
selected colors are translated by the LUT (the other col-
ors are not touched). The µC does not need to fill in all
three color lookup tables if all 3 color translations are not
needed.
After a pixel is deserialized decoded and decrypted (if
necessary) it is segmented into its color components Red,
Green and Blue according to Table 11 and Figure 36. If
LUT translation is enabled, each 8-bit pre-translation color
value is used as address to the respective LUT table to
look up the corresponding (translated) 8-bit color value.
LUT Bit Width
In 32-bit mode and high-bandwidth mode, 24 bits are
available for color data (8 bits per color) and each LUT will
be used for 8-bit to 8-bit color translation. In 24-bit mode,
the deserializer can receive only up to 18-bit color (6 bits
per color). The LUT tables can translate from 6-bit to 6-bit,
using the first 64 locations (0x00 to 0x3F). program the
MSB 2 bits of each LUT value to 00. Alternatively, pro-
gram full 8-bit values to each LUT for 6-bit to 8-bit color
translation.
Table 11. Pixel Data Format
DOUT
[5:0]
DOUT
[11:6]
DOUT
[17:12]
DOUT
18
DOUT
19
DOUT
20
DOUT
[22:21]
DOUT
[24:23]
DOUT
[26:25]
R[5:0] G[5:0] B[5:0] HS VS DE R[7:6] G[7:6] B[7:6]
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
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Recommended LUT Program Procedure
1) Write LUTPROG = 1 to register 0x7C. Keep
BLULUTEN = 0, GRNLUTEN = 0, REDLUTEN = 0
(write 0x08 to register 0x7C).
2) Write contents of red LUT with a single write packet.
For 24-bit RGB, use 0x7D as register address and
0x00 as number of bytes (UART only) and write 256
bytes. For 18-bit RGB, use 0x7D as register address
and 0x40 as number of bytes (UART only) and write 64
bytes. (Optional: Multiple write packets can be used if
LUTADDR is set before each LUT write packet.)
3) Read contents of red LUT and verify that they are
correct. Use the same register address and number
of bytes used in the previous step.
4) Repeat steps 2 and 3 for the green LUT, using 0x7E
as the register address
5) Repeat steps 2 and 3 for the blue LUT, using 0x7F as
the register address
6a) To finish the program and verify routine, without
enabling the LUT color translation, write LUTPROG =
0 (Write 0x00 to register 0x7C).
6b) To finish the program and verify routine, and start LUT
color translation, write LUTPROG = 0, BLULUTEN =
1, GRNLUTEN = 1, REDLUTEN = 1 (Write 0x07 to
register 0x7C).
Figure 36. LUT Dataflow
ADDR
R5 R4 R3 R2 R1 R0
24-BIT MODE
32-BIT OR HIGH-
BANDWIDTH MODE
R7 R6
0 0
RED LUT
DATA
MSB LSB
MSB LSB
DOUT3 DOUT9 DOUT8 DOUT7 DOUT6DOUT2 DOUT1 DOUT0DOUT4DOUT5
R5 R4 R3 R2 R1 R0R6R7
ADDR
G5 G4 G3 G2 G1 G0
G7 G6
0 0
GREEN LUT
DATA
MSB LSB
MSB LSB
G5 G4 G3 G2 G1 G0G6G7
ADDR
B5 B4 B3 B2 B1 B0
B7 B6
0 0
BLUE LUT
DATA
MSB LSB
MSB LSB
B5 B4 B3 B2 B1 B0B6B7
EN REDLUTEN
EN GRNLUTEN EN BLULUTEN
DOUT
22
DOUT
24
DOUT
26
DOUT
25
DOUT
17
DOUT
16
DOUT
15
DOUT
14
DOUT
13
DOUT
12
DOUT
23
DOUT
11
DOUT
10
DOUT
21
OUTPUT
PIN
OUTPUT
SIGNAL
24-BIT MODE
32-BIT OR HIGH-
BANDWIDTH MODE
24-BIT MODE
32-BIT OR HIGH-
BANDWIDTH MODE
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
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High-Immunity Reverse Control Channel Mode
The deserializer contains a high-immunity reverse con-
trol channel mode, which has increased robustness at
half the bit rate over the standard GMSL reverse control
channel link (Table 12). Connect a 30kΩ resistor to GPO/
HIM on the serializer, and SD/HIM on the deserializer to
use high-immunity mode at power-up. Set the HIGHIMM
bit high in both the serializer and deserializer to enable
high-immunity mode at any time after power-up. Set the
HIGHIMM bit low in both the serializer and deserializer
to use the legacy reverse control channel mode. The
deserializer reverse channel mode is not available for
500µs/1.92ms after the reverse control channel mode is
changed through the serializer/deserializer’s HIGHIMM
bit setting respectively. The user must set SD/HIM and
GPO/HIM or the HIGHIMM bits to the same value for
proper reverse control channel communication.
In high-immunity mode, Set HPFTUNE = 00 in the equal-
izer, if the serial bit rate = [PCLKOUT x 30 (BWS = low
or open) or 40 (BWS = high)] is larger than 1Gbps when
BWS is low or high. When BWS = open, set HPFTUNE =
00 when the serial bit rate is larger than 2GBps. In addi-
tion, use 47nF AC-coupling capacitors. Note that legacy
reverse-control channel mode may not function when
using 47nF AC-coupling capacitors.
By default, high-immunity mode uses a 500kbps bit rate.
Set REVFAST =1 (D7 in register 0x1A in the serializer and
register 0x11 in the deserializer) in both devices to use a
1Mbps bit rate. Certain limitations apply when using the
fast high-immunity mode (Table 13).
Sleep Mode
The deserializers have sleep mode to reduce power
consumption. The devices enter or exit sleep mode by a
command from a remote µC using the control channel.
Set the SLEEP bit to 1 to initiate sleep mode. Entering
sleep mode resets the HDCP registers, but not the con-
figuration registers. The deserializer sleeps after serial
link inactivity or 8ms (whichever arrives first) after setting
its SLEEP = 1. See the Link Startup Procedure section
for details on waking up the device for different µC and
starting conditions.
To wake up from the local side, send an arbitrary control
channel command to deserializer, wait for 5ms for the
chip to power up and then write 0 to SLEEP register bit
to make the wake-up permanent. To wake up from the
remote side, enable serialization. The deserializer will
detect the activity on serial link and then when it locks, it
will automatically set its SLEEP register bit to 0.
Power-Down Mode
The deserializers have a power-down mode which fur-
ther reduces power consumption compared to Sleep
Mode. Set PWDN low to enter power-down mode. In
power-down, the parallel outputs remain high impedance.
Entering power-down resets the device’s registers. Upon
exiting power-down, the state of external pins ADD[2:0],
CX/TP, I2CSEL, SD/HIM, and BWS are latched.
Conguration Link
The control channel can operate in a low-speed mode
called configuration link in the absence of a clock input.
This allows a microprocessor to program configuration
registers before starting the video link. An internal oscil-
lator provides the clock for the configuration link. Set
CLINKEN = 1 on the serializer to enable configuration
link. Configuration link is active until the video link is
enabled. The video link overrides the configuration link
and attempts to lock when SEREN = 1.
Table 12. Reverse Control-Channel Modes
Fast high-immunity mode requires DRS = 0
X = Don’t care
Table 13. Fast High-Immunity Mode
Requirements
HIGHIMM BIT OR
SD/HIM PIN SETTING
REVFAST
BIT REVERSE CONTROL-CHANNEL MODE MAX UART/I2C BIT RATE
(kbps)
LOW (1) XLegacy reverse control-channel mode
(compatible with all GMSL devices) 1000
HIGH (1) 0High-immunity mode 500
1 Fast high-immunity mode 1000
BWS SETTING ALLOWED PCLKOUT FREQUENCY
(MHz)
Low > 41.66
High > 30
Open > 83.33
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Link Startup Procedure
Table 14 lists the startup procedure for display applica-
tions. Table 15 lists the startup procedure for image-
sensing applications. The control channel is available
after the video link or the configuration link is established.
If the deserializer powers up after the serializer, the con-
trol channel becomes unavailable for 2ms after power-up.
Table 14. Startup Procedure for Video-Display Applications
NO. µC SERIALIZER DESERIALIZER
(AUTOSTART ENABLED) (AUTOSTART DISABLED)
— µC connected to serializer
Sets all conguration
inputs. If any conguration
inputs are available on one
end of the link but not the
other, always connects that
conguration input low.
Sets all conguration
inputs. If any conguration
inputs are available on one
end of the link but not the
other, always connects that
conguration input low.
Sets all conguration
inputs. If any conguration
inputs are available on one
end of the link but not the
other, always connects that
conguration input low
1 Powers up
Powers up and loads default
settings. Establishes video
link when valid PCLK
available
Powers up and loads default
settings
Powers up and loads default
settings. Locks to video link
signal if available.
2
Enables serial link by setting
SEREN = 1 or conguration
link by setting SEREN = 0
and CLINKEN = 1 (if valid
PCLK not available) and gets
an acknowledge. Waits for
link to be establish (~3ms)
Establishes conguration or
video link
Locks to conguration or
video link signal
3
Writes conguration bits in
the serializer/deserializer and
gets an acknowledge.
Conguration changed from default settings Conguration changed from
default settings
4
If not already enabled,
sets SEREN = 1, gets an
acknowledge and waits for
video link to be established
(~3ms)
Establishes video link when valid PCLK available (if not
already enabled)
Locks to video link signal (if
not already locked)
5Begin sending video data to
input Video data serialized and sent across serial link Video data received and
deserialized
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Table 15. Startup Procedure for Image-Sensing Applications (CDS = High)
Figure 37. State Diagram
NO. µC SERIALIZER DESERIALIZER
(AUTOSTART ENABLED) (AUTOSTART DISABLED)
— µC connected to deserializer Sets all conguration inputs Sets all conguration inputs Sets all conguration
inputs
1 Powers up
Powers up and loads
default settings.
Establishes video link when
valid PCLK available.
Powers up and loads
default settings. Goes to
sleep after 8ms.
Powers up and loads
default settings.
Locks to video link
signal if available.
2Writes deserializer conguration bits
and gets an acknowledge
Conguration
changed from default
settings
3
Wakes up the serializer by sending
dummy packet, and then writing
SLEEP = 0 within 8ms. May not get
an acknowledge (or gets a dummy
acknowledge) if not locked.
Wakes up
4
Writes serializer conguration bits.
May not get an acknowledge (or gets
a dummy acknowledge) if not locked.
Conguration changed from default settings
5
If not already enabled, sets SEREN =
1, gets an acknowledge and waits for
serial link to be established (~3ms)
Establishes video link when valid PCLK available (if not
already enabled)
Locks to video link
signal (if not already
locked)
6Begin sending video data to input Video data serialized and sent across serial link Video data received
and deserialized
SLEEP
CONFIG LINK
OPERATING
PROGRAM
REGISTERS
POWER-OFF
HIGH TO LOW
SLEEP = 1, VIDEO LINK OR CONFIG
LINK NOT LOCKED AFTER 8ms
POWER-ON
IDLE
WAKE-UP
SIGNAL
SERIAL PORT
LOCKING
SIGNAL
DETECTED
CONFIG LINK
UNLOCKED
CONFIG LINK
LOCKED
VIDEO LINK
LOCKED
VIDEO LINK
UNLOCKED
0 SLEEP
0 SLEEP
ALL STATES
GPI CHANGES FROM
LOW TO HIGH OR
PWDN = LOW OR
SEND GPI TO
GMSL
SERIALIZER
PWDN = HIGH,
POWER-ON
POWER-DOWN
OR
POWER-OFF
SERIAL LINK ACTIVITY STOPS OR 8ms ELAPSES AFTER
µC SETS SLEEP = 1
VIDEO LINK
OPERATING
PRBSEN = 0
PRBSEN = 1
VIDEO LINK
PRBS TEST
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High-Bandwidth Digital Content
Protection (HDCP)
Note: The explanation of HDCP operation in this data
sheet is provided as a guide for general understanding.
Implementation of HDCP in a product must meet the
requirements given in the HDCP System v1.3 Amendment
for GMSL, which is available from DCP.
HDCP has two main phases of operation: authentication
and the link integrity check. The µC starts authentica-
tion by writing to the START_AUTHENTICATION bit in
the GMSL serializer. The GMSL serializer generates a
64-bit random number. The host µC first reads the 64-bit
random number from the GMSL serializer and writes it
to the deserializer. The µC then reads the GMSL serial-
izer public key selection vector (AKSV) and writes it to
the deserializer. The µC then reads the deserializer KSV
(BKSV) and writes it to the GMSL serializer. The µC
begins checking BKSV against the revocation list. Using
the cipher, the GMSL serializer and deserializer calculate
a 16-bit response value, R0 and R0’, respectively. The
GMSL amendment for HDCP reduces the 100ms mini-
mum wait time allowed for the receiver to generate R0’
(specified in HDCP rev 1.3) to 128 pixel clock cycles in
the GMSL amendment.
There are two response-value comparison modes: internal
comparison and µC comparison. Set EN_INT_COMP = 1
to select internal comparison mode. Set EN_INT_COMP
= 0 to select µC comparison mode. In internal compari-
son mode, the µC reads the deserializer response R0’
and writes it to the GMSL serializer. The GMSL serializer
compares R0’ to its internally generated response value
R0, and sets R0_RI_MATCHED. In µC comparison mode,
the µC reads and compares the R0/R0’ values from the
GMSL serializer/deserializer.
During response-value generation and comparison, the
host µC checks for a valid BKSV (having 20 1s and 20
0s is also reported in BKSV_INVALID) and checks BKSV
against the revocation list. If BKSV is not on the list and
the response values match, the host authenticates the
link. If the response values do not match, the µC resam-
ples the response values (as described in HDCP rev 1.3,
Appendix C). If resampling fails, the µC restarts authen-
tication by setting the RESET_HDCP bit in the GMSL
serializer. If BKSV appears on the revocation list, the host
cannot transmit data that requires protection. The host
knows when the link is authenticated and decides when
to output data requiring protection. The µC performs a link
integrity check every 128 frames or every 2s ±0.5s. The
GMSL serializer/deserializer generate response values
every 128 frames. These values are compared internally
(internal comparison mode) or can be compared in the
host µC.
In addition, the GMSL serializer/deserializer provide
response values for the enhanced link verification.
Enhanced link verification is an optional method of link
verification for faster detection of loss-of-synchronization.
For this option, the GMSL serializer and deserializer
generate 8-bit enhanced link-verification response values
(PJ and PJ’) every 16 frames. The host must detect three
consecutive PJ/PJ’ mismatches before resampling.
Encryption Enable
The GMSL link transfers either encrypted or nonen-
crypted data. To encrypt data, the host µC sets the
encryption enable (ENCRYPTION_ENABLE) bit in both
the GMSL serializer and deserializer. The µC must set
ENCRYPTION_ENABLE in the same VSYNC cycle in
both the GMSL serializer and deserializer (no internal
VSYNC falling edges between the two writes). The same
timing applies when clearing ENCRYPTION_ENABLE to
disable encryption.
Note: ENCRYPTION_ENABLE enables/disables encryp-
tion on the GMSL irrespective of the content. To comply
with HDCP, the µC must not allow content requiring
encryption to cross the GMSL unencrypted.
The µC must complete the authentication process before
enabling encryption. In addition, encryption must be dis-
abled before starting a new authentication session.
Synchronization of Encryption
The video vertical sync (VSYNC) synchronizes the start
of encryption. Once encryption has started, the GMSL
generates a new encryption key for each frame and each
line, with the internal falling edge of VSYNC and HSYNC.
Rekeying is transparent to data and does not disrupt the
encryption of video or audio data.
Repeater Support
The GMSL serializer/deserializer include features to build
an HDCP repeater. An HDCP repeater receives and
decrypts HDCP content and then encrypts and transmits
on one or more downstream links. A repeater can also use
decrypted HDCP content (e.g., to display on a screen).
To support HDCP repeater-authentication protocol, the
deserializer has a REPEATER register bit. This register
bit must be set to 1 by a µC (most likely on the repeater
module). Both the GMSL serializer and deserializer use
SHA-1 hash-value calculation over the assembled KSV
lists. HDCP GMSL links support a maximum of 15 receiv-
ers (total number including the ones in repeater modules).
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If the total number of downstream receivers exceeds 14,
the µC must set the MAX_DEVS_EXCEEDED register bit
when it assembles the KSV list.
HDCP Authentication Procedures
The GMSL serializer generates a 64-bit random number
exceeding the HDCP requirement. The GMSL serial-
izer/deserializer internal one-time programmable (OTP)
memories contain a unique HDCP keyset programmed at
the factory. The host µC initiates and controls the HDCP
authentication procedure. The GMSL serializer and dese-
rializer generate HDCP authentication response values
for the verification of authentication. Use the following
procedures to authenticate the HDCP GMSL encryption
(refer to the HDCP 1.3 Amendment for GMSL for details).
The µC must perform link integrity checks while encryp-
tion is enabled (see Table 17). Any event that indicates
that the deserializer has lost link synchronization should
retrigger authentication. The µC must first write 1 to the
RESET_HDCP bit in the GMSL serializer before starting
a new authentication attempt.
HDCP Protocol Summary
Table 10, Table 11, and Table 12 list the summaries of the
HDCP protocol. These tables serve as an implementation
guide only. Meet the requirements in the GMSL amend-
ment for HDCP to be in full compliance.
Table 16. Startup, HDCP Authentication, and Normal Operation (Deserializer is Not a
Repeater)—First Part of the HDCP Authentication Protocol
NO. µC HDCP GMSL SERIALIZER HDCP GMSL DESERIALIZER
1 Initial state after power-up. Powers up waiting for HDCP
authentication.
Powers up waiting for HDCP
authentication.
2
Makes sure that A/V data not requiring
protection (low-value content) is available at
the GMSL serializer inputs (such as blue or
informative screen). Alternatively, uses the
FORCE_VIDEO and FORCE_AUDIO bits of
the GMSL serializer to mask A/V data at the
input of the GMSL serializer. Starts the link by
writing SEREN = H or link starts automatically
if AUTOS is low.
— —
3—Starts serialization and transmits
low-value content A/V data.
Locks to incoming data stream and
outputs low-value content A/V data.
4Reads the locked bit of the deserializer and
makes sure the link is established. — —
5Optionally writes a random-number seed to
the GMSL serializer.
Combines seed with internally
generated random number. If
no seed provided, only internal
random number is used.
—
6
If HDCP encryption is required, starts
authentication by writing 1 to the
START_AUTHENTICATION bit of the GMSL
serializer.
Generates (stores) AN, and
resets the
START_AUTHENTICATION bit
to 0.
—
7Reads AN and AKSV from the GMSL serializer
and writes to the deserializer. —Generates R0’ triggered by the µC’s
write of AKSV.
8Reads the BKSV and REPEATER bit from
deserializer and writes to the GMSL serializer.
Generates R0, triggered by the
µC’s write of BKSV. —
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Table 16. Startup, HDCP Authentication, and Normal Operation (Deserializer is Not a
Repeater)—First Part of the HDCP Authentication Protocol (continued)
NO. µC HDCP GMSL SERIALIZER HDCP GMSL DESERIALIZER
9
Reads the INVALID_BKSV bit of the GMSL
serializer and continues with authentication
if it is 0. Authentication can be restarted if it
fails (set RESET_HDCP = 1 before restarting
authentication).
— —
10
Reads R0’ from the deserializer and reads
R0 from the GMSL serializer. If they match,
continues with authentication; otherwise,
retries up to two more times (optionally, GMSL
serializer comparison can be used to detect if
R0/R0’ match). Authentication can be restarted
if it fails (set RESET_HDCP = 1 before
restarting authentication).
— —
11
Waits for the VSYNC falling edge (internal to
the GMSL serializer) and then sets the
ENCRYPTION_ENABLE bit to 1 in the
deserializer and GMSL serializer (if the FC is
not able to monitor VSYNC, it can utilize the
VSYNC_DET bit in the GMSL serializer).
Encryption enabled after the
next VSYNC falling edge.
Decryption enabled after the next
VSYNC falling edge.
12
Checks that BKSV is not in the Key
Revocation list and continues if it is not.
Authentication can be restarted if it fails.
Note: Revocation list check can start after
BKSV is read in step 8.
— —
13 Starts transmission of A/V content that needs
protection.
Performs HDCP encryption on
high-value content A/V data.
Performs HDCP decryption on high-
value content A/V data.
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Table 17. Link Integrity Check (Normal)—Performed Every 128 Frames After Encryption
is Enabled
NO. µC HDCP GMSL SERIALIZER HDCP GMSL DESERIALIZER
1 —
Generates Ri and updates the
RI register every 128 VSYNC
cycles.
Generates Ri’ and updates the RI’
register every 128 VSYNC cycles.
2—Continues to encrypt and
transmit A/V data.
Continues to receive, decrypt, and
output A/V data.
3Every 128 video frames (VSYNC cycles) or
every 2s. — —
4 Reads RI from the GMSL serializer. — —
5Reads RI’ from the deserializer. — —
6
Reads RI again from the GMSL serializer and
makes sure it is stable (matches the previous
RI that it has read from the GMSL serializer). If
RI is not stable, go back to step 5.
— —
7If RI matches RI’, the link integrity check is
successful; go back to step 3. — —
8
If RI does not match RI’, the link integrity
check fails. After the detection of failure of
link integrity check, the FC makes sure that
A/V data not requiring protection (low-value
content) is available at the GMSL serializer
inputs (such as blue or informative screen).
Alternatively, the FORCE_VIDEO and
FORCE_AUDIO bits of the GMSL serializer
can be used to mask A/V data input of the
GMSL serializer.
— —
9Writes 0 to the ENCRYPTION_ENABLE bit of
the GMSL serializer and deserializer.
Disables encryption and
transmits low-value content A/V
data.
Disables decryption and outputs low-
value content A/V data.
10
Restarts authentication by writing 1 to the
RESET_HDCP bit followed by writing 1 to the
START_AUTHENTICATION bit in the GMSL
serializer.
— —
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Table 18. Optional Enhanced Link Integrity Check—Performed Every 16 Frames After
Encryption is Enabled
NO. µC HDCP GMSL SERIALIZER HDCP GMSL DESERIALIZER
1 —
Generates PJ and updates the
PJ register every 16 VSYNC
cycles.
Generates PJ’ and updates the PJ’
register every 16 VSYNC cycles.
2—Continues to encrypt and
transmit A/V data.
Continues to receive, decrypt, and
output A/V data.
3Every 16 video frames, reads PJ from the
GMSL serializer and PJ’ from the deserializer. — —
4If PJ matches PJ’, the enhanced link integrity
check is successful; go back to step 3. — —
5
If there is a mismatch, retry up to two more
times from step 3. Enhanced link integrity
check fails after 3 mismatches. After the
detection of failure of enhanced link integrity
check, the µC makes sure that A/V data not
requiring protection (low-value content) is
available at the GMSL serializer inputs (such
as blue or informative screen). Alternatively,
the FORCE_VIDEO and FORCE_AUDIO bits
of the GMSL serializer can be used to mask
A/V data input of the GMSL serializer.
— —
6Writes 0 to the ENCRYPTION_ENABLE bit of
the GMSL serializer and deserializer.
Disables encryption and
transmits low-value content A/V
data.
Disables decryption and outputs low-
value content A/V data.
7
Restarts authentication by writing 1 to the
RESET_HDCP bit followed by writing 1 to the
START_AUTHENTICATION bit in the GMSL
serializer.
— —
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Example Repeater Network—Two µCs
The example shown in Figure 38 has one repeater and two µCs. Table 19 summarizes the authentication operation.
Table 19. HDCP Authentication and Normal Operation (One Repeater, Two µCs)—First
and Second Parts of the HDCP Authentication Protocol
Figure 38. Example Network with One Repeater and Two µCs (Tx = GMSL Serializer’s, Rx = Deserializer’s)
NO. µC_B µC_R
HDCP GMSL
SERIALIZER
(TX_B1, TX_R1,
TX_R2)
HDCP GMSL
DESERIALIZER
(RX_R1, RX_D1,
RX_D2)
TX_B1 CDS = 0
TX_R1 CDS = 0
TX_R2 CDS = 0
RX_R1 CDS = 1
RX_D1 CDS = 0
RX_D2 CDS = 0
1 Initial state after power-up. Initial state after power-up. All: Power-up waiting for
HDCP authentication.
All: Power-up waiting for
HDCP authentication.
2—
Writes REPEATER = 1 in
RX_R1. Retries until proper
acknowledge frame received.
Note: This step must be
completed before the rst part
of authentication is started
between TX_B1 and RX_R1 by
the µC_B (step 7). For example,
to satisfy this requirement,
RX_R1 can be held at power-
down until µC_R is ready to
write the REPEATER bit, or
µC_B can poll µC_R before
starting authentication.
— —
BD-DRIVE
RX_R1
µC_B
TX_B1
DISPLAY 1
RX_D1
DISPLAY 2
RX_D2
REPEATER
TX_R1
TX_R2
RX_R2 µC_R
VIDEO
ROUTING
MEMORY
WITH SRM
VIDEO CONNECTION
CONTROL CONNECTION 1 (µC_B IN BD-DRIVE IS MASTER)
CONTROL CONNECTION 2 (µC_R IN REPEATER IS MASTER)
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Table 19. HDCP Authentication and Normal Operation (One Repeater, Two µCs)—First
and Second Parts of the HDCP Authentication Protocol (continued)
NO. µC_B µC_R
HDCP GMSL
SERIALIZER
(TX_B1, TX_R1,
TX_R2)
HDCP GMSL
DESERIALIZER
(RX_R1, RX_D1,
RX_D2)
TX_B1 CDS = 0
TX_R1 CDS = 0
TX_R2 CDS = 0
RX_R1 CDS = 1
RX_D1 CDS = 0
RX_D2 CDS = 0
3
Makes sure that A/V data
not requiring protection (low-
value content) is available at
the TX_B1 inputs (such as
blue or informative screen).
Alternatively, the FORCE_
VIDEO and FORCE_AUDIO
bits of TX_B1 can be used to
mask A/V data input of TX_B1.
Starts the link between TX_B1
and RX_R1 by writing SEREN
= H to TX_B1, or link starts
automatically if AUTOS is low.
—
TX_B1: Starts
serialization and
transmits low-value
content A/V data.
RX_R1: Locks to
incoming data stream
and outputs low-value
content A/V data.
4 —
Starts all downstream links
by writing SEREN = H to
TX_R1, TX_R2, or links start
automatically if AUTOS of
transmitters are low.
TX_R1, TX_R2: Starts
serialization and
transmits low-value
content A/V data.
RX_D1, RX_D2: Locks
to incoming data stream
and outputs low-value
content A/V data.
5
Reads the locked bit of RX_R1
and makes sure the link
between TX_B1 and RX_R1 is
established.
Reads the locked bit of RX_D1
and makes sure the link
between TX_R1 and RX_D1 is
established. Reads the locked
bit of RX_D2 and makes sure
the link between TX_R2 and
RX_D2 is established.
— —
6Optionally, writes a random
number seed to TX_B1.
Writes 1 to the
GPIO_0_FUNCTION and
GPIO_1_FUNCTION bits
in RX_R1 to change GPIO
functionality used for HDCP
purpose. Optionally, writes a
random-number seed to TX_R1
and TX_R2.
— —
7
Starts and completes the
rst part of the authentication
protocol between TX_B1, RX_R1
(see steps 6–10 in Table 10).
—
TX_B1: According
to commands from
µC_B, generates AN,
computes R0.
RX_R1: According to
commands from µC_B,
computes R0’.
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Table 19. HDCP Authentication and Normal Operation (One Repeater, Two µCs)—First
and Second Parts of the HDCP Authentication Protocol (continued)
NO. µC_B µC_R
HDCP GMSL
SERIALIZER
(TX_B1, TX_R1,
TX_R2)
HDCP GMSL
DESERIALIZER
(RX_R1, RX_D1,
RX_D2)
TX_B1 CDS = 0
TX_R1 CDS = 0
TX_R2 CDS = 0
RX_R1 CDS = 1
RX_D1 CDS = 0
RX_D2 CDS = 0
8—
When GPIO_1 = 1 is detected,
starts and completes the rst part
of the authentication protocol
between the (TX_R1, RX_D1)
and (TX_R2, RX_D2) links (see
steps 6–10 in Table 10).
TX_R1, TX_R2:
According to commands
from µC_R, generates
AN, computes R0.
RX_D1, RX_D2:
According to commands
from µC_R, computes
R0’.
9
Waits for the VSYNC falling
edge and then enables
encryption on the (TX_B1,
RX_R1) link. Full authentication
is not complete yet so it makes
sure A/V content that needs
protection is not transmitted.
Since REPEATER = 1 was read
from RX_R1, the second part of
authentication is required.
—
TX_B1: Encryption
enabled after next
VSYNC falling edge.
RX_R1: Decryption
enabled after next
VSYNC falling edge.
10 —
When GPIO_0 = 1 is detected,
enables encryption on the
(TX_R1, RX_D1) and (TX_R2,
RX_D2) links.
TX_R1, TX_R2:
Encryption enabled
after next VSYNC
falling edge.
RX_D1, RX_D2:
Decryption enabled
after next VSYNC
falling edge.
11
Waits for some time to allow
µC_R to make the KSV list
ready in RX_R1. Then polls
(reads) the KSV_LIST_READY
bit of RX_R1 regularly until
proper acknowledge frame is
received and bit is read as 1.
Blocks control channel
from µC_B side by setting
REVCCEN = FWDCCEN = 0
in RX_R1. Retries until proper
acknowledge frame received.
—
RX_R1: Control
channel from serializer
side (TX_B1) is blocked
after FWDCCEN =
REVCCEN = 0 is
written.
12
Writes BKSVs of RX_D1 and
RX_D2 to the KSV list in RX_
R1. Then, calculates and writes
the BINFO register of RX_R1.
—
RX_R1: Triggered by
µC_R’s write of BINFO,
calculates hash value
(V’) on the KSV list,
BINFO and the secret-
value M0’.
13
Writes 1 to the KSV_LIST_
READY bit of RX_R1 and then
unblocks the control channel
from the µC_B side by setting
REVCCEN = FWDCCEN = 1 in
RX_R1.
—
RX_R1: Control channel
from the serializer side
(TX_B1) is unblocked
after FWDCCEN =
REVCCEN = 1 is
written.
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
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Detection and Action Upon New Device
Connection
When a new device is connected to the system, the
device must be authenticated and the device’s KSV
checked against the revocation list. The downstream
µCs can set the NEW_DEV_CONN bit of the upstream
receiver and invoke an interrupt to notify upstream µCs.
Notication of Start of Authentication and
Enable of Encryption to Downstream Links
HDCP repeaters do not immediately begin authentication
upon startup or detection of a new device, but instead wait
for an authentication request from the upstream transmit-
ter/repeaters.
Use the following procedure to notify downstream links of
the start of a new authentication request:
1) Host µC begins authentication with the HDCP repeat-
er’s input receiver.
2) When AKSV is written to HDCP repeater’s input
receiver, its AUTH_STARTED bit is automatically set
and its GPIO1 goes high (if GPIO1_FUNCTION is set
to high).
3) HDCP repeater’s µC waits for a low-to-high transition
on HDCP repeater input receiver’s AUTH_STARTED
bit and/or GPIO1 (if configured) and starts authentica-
tion downstream.
4) HDCP repeater’s µC resets the AUTH_STARTED bit.
Table 19. HDCP Authentication and Normal Operation (One Repeater, Two µCs)—First
and Second Parts of the HDCP Authentication Protocol (continued)
NO. µC_B µC_R
HDCP GMSL
SERIALIZER
(TX_B1, TX_R1,
TX_R2)
HDCP GMSL
DESERIALIZER
(RX_R1, RX_D1,
RX_D2)
TX_B1 CDS = 0
TX_R1 CDS = 0
TX_R2 CDS = 0
RX_R1 CDS = 1
RX_D1 CDS = 0
RX_D2 CDS = 0
14
Reads the KSV list and BINFO
from RX_R1 and writes them
to TX_B1. If any of the MAX_
DEVS_EXCEEDED or MAX_
CASCADE_EXCEEDED bits
is 1, then authentication fails.
Note: BINFO must be written
after the KSV list.
—
TX_B1: Triggered by
µC_B’s write of BINFO,
calculates hash value
(V) on the KSV list,
BINFO and the secret-
value M0.
—
15
Reads V from TX_B1 and V’
from RX_R1. If they match,
continues with authentication;
otherwise, retries up to two
more times.
— — —
16
Searches for each KSV in the
KSV list and BKSV of RX_R1 in
the Key Revocation list.
— — —
17
If keys are not revoked,
the second part of the
authentication protocol is
completed.
— — —
18 Starts transmission of A/V
content that needs protection. —
All: Perform HDCP
encryption on high-
value A/V data.
All: Perform HDCP
decryption on high-
value A/V data.
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Set GPIO0_FUNCTION to high to have GPIO0 follow the
ENCRYPTION_ENABLE bit of the receiver. The repeater
µC can use this function for notification when encryption
is enabled/disabled by an upstream µC.
Applications Information
Self PRBS Test
The serializers include a PRBS pattern generator which
works with bit-error verification in the deserializer. To
run the PRBS test, disable encryption (if used), set
DISHSFILT, DISVSFILT, and DISDEFILT to ‘1’, to disable
glitch filter in the deserializer. Then, set PRBSEN = 1
(0x04, D5) in the serializer and then in the deserializer.
To exit the PRBS test, set PRBSEN = 0 (0x04, D5) in the
deserializer and then in the serializer.
Error Checking
The deserializers check the serial link for errors and
store the number of decoding errors in the 8-bit registers
DECERR (0x0D). If a large number of decoding errors
are detected within a short duration (error rate ≥ 1/4), the
deserializers lose lock and stop the error counter. The
deserializers then attempt to relock to the serial data.
DECERR reset upon successful video link lock, suc-
cessful readout of the register (through µC), or whenever
auto error reset is enabled. The deserializers use a sepa-
rate PRBS Register during the internal PRBS test, and
DECERR are reset to 0x00.
ERR Output
The deserializers have an open-drain ERR output. This
output asserts low whenever the number of decoding
errors exceeds the error thresholds during normal opera-
tion, or when at least 1 PRBS error is detected during
PRBS test. ERR reasserts high whenever DECERR
resets, due to DECERR readout, video link lock, or auto
error reset.
Auto Error Reset
The default method to reset errors is to read the respec-
tive error registers in the deserializers (0x0D and 0x0E).
Auto error reset clears the error counters DECERR and
the ERR output ~1µs after ERR goes low. Auto error reset
is disabled on power-up. Enable auto error reset through
AUTORST (0x06, D5). Auto error reset does not run when
the device is in PRBS test mode.
Dual µC Control
Usually systems have one microcontroller to run the
control channel, located on the serializer side for display
applications or on the deserializer side for image-sensing
applications. However, a µC can reside on each side
simultaneously, and trade off running the control channel.
In this case, each µC can communicate with the serializer
and deserializer and any peripheral devices.
Contention will occur if both µCs attempt to use the
control channel at the same time. It is up to the user
to prevent this contention by implementing a higher
level protocol. In addition, the control channel does not
provide arbitration between I2C masters on both sides of
the link. An acknowledge frame is not generated when
communication fails due to contention. If communication
across the serial link is not required, the µCs can disable
the forward and reverse control channel using the
FWDCCEN and REVCCEN bits (0x04, D[1:0]) in the
serializer/deserializer. Communication across the serial
link is stopped and contention between µCs cannot occur.
As an example of dual µC use in an image-sensing
application, the serializer can be in sleep mode and
waiting for wake-up by µC on the deserializer side. After
wake-up, the serializer-side µC assumes master control
of the serializer’s registers.
Changing the Clock Frequency
It is recommended that the serial link be enabled after
the video clock (fPCLKOUT) and the control-channel
clock (fUART/fI2C) are stable. When changing the clock
frequency, stop the video clock for 5µs, apply the clock
at the new frequency, then restart the serial link or toggle
SEREN. On-the-fly changes in clock frequency are
possible if the new frequency is immediately stable and
without glitches. The reverse control channel remains
unavailable for 500µs after serial link start or stop. When
using the UART interface, limit on-the-fly changes in
fUART to factors of less than 3.5 at a time to ensure
that the device recognizes the UART sync pattern. For
example, when lowering the UART frequency from 1Mbps
to 100kbps, first send data at 333kbps then at 100kbps for
reduction ratios of 3 and 3.333, respectively.
Fast Detection of Loss of Synchronization
A measure of link quality is the recovery time from loss of
synchronization. The host can be quickly notified of loss-
of-lock by connecting the deserializer’s LOCK output to
the GPI input. If other sources use the GPI input, such as
a touch-screen controller, the µC can implement a routine
to distinguish between interrupts from loss-of-sync and
normal interrupts. Reverse control-channel communica-
tion does not require an active forward link to operate
and accurately tracks the LOCK status of the GMSL link.
LOCK asserts for video link only and not for the configura-
tion link.
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Providing a Frame Sync (Camera
Applications)
The GPI/GPO provide a simple solution for camera
applications that require a Frame Sync signal from the
ECU (e.g. surround view systems). Connect the ECU
Frame Sync signal to the GPI input, and connect GPO
output to the camera Frame Sync input. GPI/GPO has
a typical delay of 275µs. Skew between multiple GPI/
GPO channels is typically 115µs. If a lower skew signal
is required, connect the camera’s frame sync input one of
the deserializer’s GPIOs and use an I2C broadcast write
command to change the GPIO output state. This has a
maximum skew of 1.5µs, independent from the used I2C
bit rate.
Software Programming of the Device
Addresses
The serializers and deserializers have programmable
device addresses. This allows multiple GMSL devices,
along with I2C peripherals, to coexist on the same control
channel. The serializer device address is in register 0x00
of each device, while the deserializer device address is in
register 0x01 of each device. To change a device address,
first write to the device whose address changes (register
0x00 of the serializer for serializer device address change,
or register 0x01 of the deserializer for deserializer device
address change). Then write the same address into the
corresponding register on the other device (register 0x00
of the deserializer for serializer device address change,
or register 0x01 of the serializer for deserializer device
address change).
3-Level Conguration Inputs
CX/TP and BWS are 3-level inputs that control the serial
interface configuration and power-up defaults. Connect
3-level inputs through a pullup resistor to IOVDD to set a
high level, a pulldown resistor to GND to set a low level, or
open to set a mid level. For digital control, use three-state
logic to drive the 3-level logic input.
Conguration Blocking
The deserializers can block changes to registers. Set
CFGBLOCK to make registers 0x00 to registers 0x1F as
read only. Once set, the registers remain blocked until the
supplies are removed or until PWDN is low.
Compatibility with Other GMSL Devices
The deserializers are designed to pair with the MAX9275–
MAX9281 serializers but interoperates with any GMSL
serializers. See the Table 20 for operating limitations
Key Memory
Each device has a unique HDCP key set that is stored
in secure nonvolatile memory (NVM). The HDCP key set
consists of forty 56-bit private keys and one 40-bit public
key. The NVM is qualified for automotive applications.
HS/VS/DE Inversion
The deserializer uses an active-high HS, VS, and DE
for encoding and HDCP encryption. Set INVHSYNC,
INVVSYNC, and INVDE in the serializer (registers 0x0D,
0x0E) to invert active-low input signals for use with the
GMSL devices. Set INVHSYNC, INVVSYNC, and INVDE
in the deserializer (register 0x0E) to output active-low
signals for use with downstream devices.
WS/SCK Inversion
The deserializer uses standard polarities for I2S. Set
INVWS, INVSCK in the serializer (register 0x1B) to invert
opposite polarity signals for use with the GMSL devices.
Set INVWS, INVSCK in the deserializer (register 0x1D) to
output reverse-polarity signals for downstream use.
Table 20. MAX9276/MAX9280 Feature Compatibility
MAX9276/MAX9280 FEATURE GMSL SERIALIZER
HDCP (MAX9280 only) If feature not supported in serializer, must not be turned on in the MAX9280
High-bandwidth mode If feature not supported in serializer, must only use 24-bit and 32-bit modes
I2C to I2C If feature not supported in serializer, must use UART to I2C or UART to UART
Coax If feature not supported in serializer, must connect unused serial output through 200nF and
50Ω in series to VDD and set the reverse control channel amplitude to 100mV.
High-immunity control channel If feature not supported in serializer, must use the legacy reverse control channel mode
TDM encoding If feature not supported in serializer, must use I2S encoding (with 50% WS duty cycle), if
supported
I2S encoding If feature not supported in serializer must disable I2S in the MAX9276/MAX9280
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GPIOs
The deserializers have two open-drain GPIOs available
when not used for HDCP purposes (see the Notification
of Start of Authentication and Enable of Encryption to
Downstream Links section), GPIO1OUT and GPIO0OUT
(0x06, D3 and D1) set the output state of the GPIOs.
Setting the GPIO output bits to ‘0’ low pulls the output low,
while setting the bits to ‘1’ leaves the output undriven, and
pulled high through internal/external pullup resistors. The
GPIO input buffers are always enabled. The input states
are stored in GPIO1 and GPIO0 (0x06, D2 and D0). Set
GPIO1OUT/GPIO0OUT to 1 when using GPIO1/GPIO0
as an input.
Staggered Parallel Outputs
The deserializers stagger the parallel data outputs to
reduce EMI and noise. Staggering outputs also reduces
the power-supply transient requirements. By default,
the deserializers stagger outputs according to Table 21.
Disable output staggering through the DISSTAG bit (0x06,
D7).
Internal Input Pulldowns
The control and configuration inputs (except 3-level
inputs) include a pulldown resistor to GND. External pull-
down resistors are not needed.
Choosing I2C/UART Pullup Resistors
I2C and UART open-drain lines require a pullup resistor
to provide a logic-high level. There are tradeoffs between
power dissipation and speed, and a compromise may
be required when choosing pullup resistor values. Every
device connected to the bus introduces some capacitance
even when the device is not in operation. I2C specifies
300ns rise times (30% to 70%) for fast mode, which
is defined for data rates up to 400kbps (see the I2C
specifications in the AC Electrical Characteristics table
for details). To meet the fast-mode rise-time requirement,
choose the pullup resistors so that rise time tR = 0.85
x RPULLUP x C
BUS < 300ns. The waveforms are not
recognized if the transition time becomes too slow. The
device supports I2C/UART rates up to 1Mbps.
AC-Coupling
AC-coupling isolates the receiver from DC voltages up
to the voltage rating of the capacitor. Capacitors at the
serializer output and at the deserializer input are needed
for proper link operation and to provide protection if either
end of the cable is shorted to a battery. AC-coupling
blocks low-frequency ground shifts and low-frequency
common-mode noise.
Selection of AC-Coupling Capacitors
Voltage droop and the digital sum variation (DSV) of
transmitted symbols cause signal transitions to start from
different voltage levels. Because the transition time is fixed,
starting the signal transition from different voltage levels
causes timing jitter. The time constant for an AC-coupled
link needs to be chosen to reduce droop and jitter to an
acceptable level. The RC network for an AC-coupled link
consists of the CML/coax receiver termination resistor
(RTR), the CML/coax driver termination resistor (RTD),
and the series AC-coupling capacitors (C). The RC
time constant for four equal-value series capacitors
is (C x (RTD + R
TR))/4. RTD and RTR are required to
match the transmission line impedance (usually 100Ω
differential, 50Ω single ended). This leaves the capacitor
selection to change the system time constant. Use at
0.22μF (using legacy reverse control channel), 47nF
(using high-immunity reverse control channel), or larger
high-frequency surface-mount ceramic capacitors, with
sufficient voltage rating to withstand a short to battery, to
pass the lower speed reverse control-channel signal. Use
capacitors with a case size less than 3.2mm x 1.6mm to
have lower parasitic effects to the high-speed signal.
Power-Supply Circuits and Bypassing
The deserializers use an AVDD and DVDD of 3.0V to
3.6V. All single-ended inputs and outputs except for the
serial input derive power from an IOVDD of 1.7V to 3.6V,
which scale with IOVDD. Proper voltage-supply bypass-
ing is essential for high-frequency circuit stability.
Table 21. Staggered Output Delay
OUTPUT
OUTPUT DELAY RELATIVE
TO DOUT0 (ns)
DISSTAG = 0 DISSTAG = 1
DOUT0–DOUT5,
DOUT21, DOUT22 0 0
DOUT6–DOUT10,
DOUT23, DOUT24 0.5 0
DOUT11–DOUT15,
DOUT25, DOUT26 10
DOUT16–DOUT20,
DOUT27, DOUT28 1.5 0
PCLKOUT 0.75 0
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
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Power-Supply Table
Power-supply currents shown in the DC Electrical
Characteristics table is the sum of the currents from
AVDD, DVDD, and IOVDD. IOVDD is measured at
VIOVDD = 3.6V. If using a different IOVDD voltage, the
IOVDD worst-case supply current will vary according to
Table 22. HDCP operation (MAX9280 only) draws addi-
tional current. This is shown in Table 23.
Cables and Connectors
Interconnect for CML typically has a differential imped-
ance of 100Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities. Coax cables typically have a characteristic
impedance of 50Ω, contact the factory for 75Ω operation).
Table 24 lists the suggested cables and connectors used
in the GMSL link.
Table 24. Suggested Connectors and Cables for GMSL
Table 22. IOVDD Current Simulation Results
Table 23. Additional Supply Current from HDCP (MAX9280 Only)
VENDOR CONNECTOR CABLE TYPE
Rosenberger 59S2AX-400A5-Y RG174 Coax
Rosenberger D4S10A-40ML5-Z Dacar 538 STP
Nissei GT11L-2S F-2WME AWG28 STP
JAE MX38-FF A-BW-Lxxxxx STP
IOVDD WORST-CASE SUPPLY CURRENT IOVDD SUPPLY VOLTAGE
1.9V 3.3V* 3.6V
BWS = low,
fPCLKOUT = 16.6MHz
CL = 5pF 4.4 7.9 8.6
mA
CL = 10pF 6.4 12.4 13.5
BWS = low,
fPCLKOUT = 33.3MHz
CL = 5pF 814.5 15.8
CL = 10pF 13.2 23.1 25.2
BWS = low,
fPCLKOUT = 66.6MHz
CL = 5pF 14.9 25.6 27.9
CL = 10pF 23.4 40.7 44.4
BWS = low,
fPCLKOUT = 104MHz
CL = 5pF 21.6 38.7 42.2
CL = 10pF 34.8 60.3 65.8
BWS = mid,
fPCLKOUT = 36.6MHz
CL = 5pF 10.2 18.2 19.8
CL = 10pF 16.6 28.9 31.5
BWS = mid,
fPCLKOUT = 104MHz
CL = 5pF 25.1 45 49
CL = 10pF 40.4 70.2 76.5
PCLK
(MHz)
MAXIMUM HDCP CURRENT
(mA)
16.6 6
33.3 9
36.6 9
66.6 12
104 18
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Board Layout
Separate LVCMOS logic signals and CML/coax high-
speed signals to prevent crosstalk. Use a four-layer PCB
with separate layers for power, ground, CML/coax, and
LVCMOS logic signals. Layout PCB traces close to each
other for a 100Ω differential characteristic impedance for
STP. The trace dimensions depend on the type of trace
used (microstrip or stripline). Note that two 50Ω PCB
traces do not have 100Ω differential impedance when
brought close together—the impedance goes down when
the traces are brought closer. Use a 50Ω trace for the
single-ended output when driving coax.
Route the PCB traces for differential CML channel in par-
allel to maintain the differential characteristic impedance.
Avoid vias. Keep PCB traces that make up a differential
pair equal length to avoid skew within the differential pair.
ESD Protection
ESD tolerance is rated for Human Body Model, IEC
61000-4-2, and ISO 10605. The ISO 10605 and IEC
61000-4-2 standards specify ESD tolerance for electronic
systems. The serial link inputs are rated for ISO 10605
ESD protection and IEC 61000-4-2 ESD protection. All
pins are tested for the Human Body Model. The Human
Body Model discharge components are CS = 100pF and
RD = 1.5kΩ (Figure 39). The IEC 61000-4-2 discharge
components are CS = 150pF and RD = 330Ω (Figure 40).
The ISO 10605 discharge components are CS = 330pF
and RD = 2kΩ (Figure 41).
Figure 39. Human Body Model ESD Test Circuit
Figure 40. IEC 61000-4-2 Contact Discharge ESD Test Circuit
Figure 41. ISO 10605 Contact Discharge ESD Test Circuit
CS
150pF
STORAGE
CAPACITOR
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
RD
330Ω
STORAGE
CAPACITOR
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
1MΩ
RD
1.5kΩ
CS
100pF
STORAGE
CAPACITOR
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
RD
2kΩ
CS
330pF
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Table 25. Register Table
REGISTER
ADDRESS BITS NAME VALUE FUNCTION DEFAULT
VALUE
0x00 D[7:1] SERID XXXXXXX Serializer device address (power-up default value
depends on latched address pin level) XX00XX0
D0 —0Reserved 0
0x01
D[7:1] DESID XXXXXXX Deserializer device address (power-up default
value depends on latched address pin level). XX01XXX
D0 CFGBLOCK 0Normal operation 0
1 Registers 0x00 to 0x1F are read only
0x02
D[7:6] SS
00 No spread spectrum.
00
01 ±2% spread spectrum
10 No spread spectrum
11 ±4% spread spectrum
D5 AUDIOMODE
0WS, SCK congured as output (deserializer
sourced clock) 0
1WS, SCK congured as input (system sourced
clock)
D4 AUDIOEN 0 Disable I2S/TDM channel 1
1 Enable I2S/TDM channel
D[3:2] PRNG
00 12.5MHz to 25MHz pixel clock
11
01 25MHz to 50MHz pixel clock
10 50MHz to 104MHz pixel clock
11 Automatically detect the pixel clock range
D[1:0] SRNG
00 0.5 to 1Gbps serial data rate
11
01 1 to 2Gbps serial data rate
10 2 to 3.12Gbps serial data rate
11 Automatically detect serial data rate
0x03
D[7:6] AUTOFM
00 Calibrate spread modulation rate only once after
locking
00
01 Calibrate spread modulation rate every 2ms after
locking
10 Calibrate spread modulation rate every 16ms after
locking
11 Calibrate spread modulation rate every 256ms
after locking
D5 —0Reserved 0
D[4:0] SDIV
00000 Auto calibrate sawtooth divider
00000
XXXXX
Manual SDIV setting. See the Manual
Programming of the Spread-Spectrum Divider
section.
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Table 25. Register Table (continued)
REGISTER
ADDRESS BITS NAME VALUE FUNCTION DEFAULT
VALUE
0x04
D7 LOCKED 0LOCK output is low 0
(Read only)
1 LOCK output is high
D6 OUTENB
0Enable outputs (power-up default value depends
on ENABLE pin value at power-up) 0, 1
1Disable outputs (power-up default value depends
on ENABLE pin value at power-up)
D5 PRBSEN 0Disable PRBS test 0
1 Enable PRBS test
D4 SLEEP
0Normal mode (power-up default value depends on
MS pin value at power-up) 0, 1
1Activate sleep mode (power-up default value
depends on MS pin value at power-up)
D[3:2] INTTYPE
00 Local control channel uses I2C when I2CSEL = 0
0101 Local control channel uses UART when I2CSEL = 0
10, 11 Local control channel disabled
D1 REVCCEN 0Disable reverse control channel to serializer (sending) 1
1Enable reverse control channel to serializer (sending)
D0 FWDCCEN
0Disable forward control channel from serializer
(receiving) 1
1Enable forward control channel from serializer
(receiving)
0x05
D7 I2CMETHOD
0I2C conversion sends the register address when
converting UART to I2C0
1Disable sending of I2C register address when
converting UART to I2C (command-byte-only mode)
D[6:5] HPFTUNE
00 7.5MHz equalizer highpass lter cutoff frequency
01
01 3.75MHz equalizer highpass lter cutoff frequency
10 2.5MHz equalizer highpass lter cutoff frequency
11 1.87MHz equalizer highpass lter cutoff frequency
D4 PDEQ 0Enable equalizer 0
1Disable equalizer
D[3:0] EQTUNE
0000 2.1dB equalizer boost gain
1001
0001 2.8dB equalizer boost gain
0010 3.4dB equalizer boost gain
0011 4.2dB equalizer boost gain
0100 5.2dB equalizer boost gain
0101 6.2dB equalizer boost gain
0110 7dB equalizer boost gain
0111 8.2dB equalizer boost gain
1000 9.4dB equalizer boost gain
1001 10.7dB equalizer boost gain. Power-up default
1010 11.7dB equalizer boost gain
1011 13dB equalizer boost gain
11XX Do not use
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Table 25. Register Table (continued)
REGISTER
ADDRESS BITS NAME VALUE FUNCTION DEFAULT
VALUE
0x06
D7 DISSTAG 0Enable staggered outputs 0
1 Disable staggered outputs
D6 AUTORST
0Do not automatically reset error registers and
outputs 0
1Automatically reset DECERR register 1µs after
ERR asserts
D5 DISGPI
0Enable GPI to GPO signal transmission to
serializer 0
1Disable GPI to GPO signal transmission to
serializer
D4 GPIIN 0GPI input is low 0
(Read only)
1 GPI input is high
D3 GPIO1OUT 0Set GPIO1 to low 1
1 Set GPIO1 to high
D2 GPIO1IN 0GPIO1 input is low 0
(Read only)
1 GPIO1 input is high
D1 GPIO0OUT 0Set GPIO0 to low 1
1 Set GPIO0 to high
D0 GPIO0IN 0GPIO0 input is low 0
(Read only)
1 GPIO0 input is high
0x07 D[7:0] — 01010100 Reserved 01010100
0x08
D[7:3] — 00110 Reserved 00110
D2 DISDEFILT 0Enable DE glitch lter 0
1 Disable DE glitch lter
D1 DISVSFILT 0Enable VS glitch lter 0
1 Disable VS glitch lter
D0 DISHSFILT 0Enable HS glitch lter 0
1 Disable HS glitch lter
0x09 D[7:0] — 11001000 Reserved 11001000
0x0A D[7:0] — 00010XXX Reserved 00010XXX
0x0B D[7:0] — 00100000 Reserved 00100000
0x0C D[7:0] ERRTHR XXXXXXXX Error threshold for decoding errors. 00000000
0x0D D[7:0] DECERR XXXXXXXX Decoding error counter 00000000
(Read only)
0x0E D[7:0] PRBSERR XXXXXXXX PRBS error counter 00000000
(Read only)
0x0F D[7:0] — XXXXXXXX Reserved (Read only)
0x10 D[7:0] — XXXXXXXX Reserved (Read only)
0x11 D7 REVFAST
0High-immunity reverse channel mode uses
500kbps bit rate 0
1High-immunity reverse channel mode uses 1Mbps
bit rate
D[6:0] — 0100010 Reserved 0100010
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Table 25. Register Table (continued)
REGISTER
ADDRESS BITS NAME VALUE FUNCTION DEFAULT
VALUE
0x12
D7 MCLKSRC 0MCLK derived from PCLKOUT. See Table 5. 0
1 MCLK derived from internal oscillator
D[6:0] MCLKDIV 0000000 MCLK disabled 0000000
XXXXXXX MCLK divider
0x13 D[7:0] — 0X000000 Reserved 0X000000
0x14
D7 INVVSYNC 0No VS inversion at the output 0
1 Invert VS at the output
D6 INVHSYNC 0No HS inversion at the output 0
1 Invert HS at the output
D5 INVDE 0No DE inversion at the output 0
1 Invert DE at the output
D4 DRS 0 High data rate mode 0
1 Low data rate mode
D3 DCS 0Normal parallel output driver current 0
1 Boosted parallel output driver current
D2 DISRWAKE 0Enable remote wake-up 0
1 Disable remote wake-up
D1 ES 0Output data valid on rising edge of PCLKOUT 0
1 Output data valid on falling edge of PCLKOUT
D0 INTOUT 0Drive INTOUT low 0
1 Drive INTOUT high
0x15
D7 AUTOINT
0INTOUT pin output controlled by INTOUT bit above
1
1Writes to any AVINFO bytes sets INTOUT to high.
Reads to any AVINFO bytes sets INTOUT to low
D6 HVTREN
0Disable HS/VS tracking (power-up default value
depends on state of BWS input value at power-up) 0, 1
1Enable HS/VS tracking (power-up default value
depends on state of BWS input value at power-up)
D5 DETREN
0Disable DE tracking (power-up default value
depends on state of BWS input value at power-up) 0, 1
1Enable DE tracking (power-up default value
depends on state of BWS input value at power-up)
D4 HVTRMODE 0Partial periodic HS/VS and DE tracking 1
1 Partial and full periodic HS/VS and DE tracking
D[3:2] — 00 Reserved 00
D1 MCLKWS 0MCLK output operates normally 0
1 WS is output from MCLK (MCLK mirrors WS)
D0 MCLKPIN 0MCLK output on DOUT28/CNTL2 0
1 MCLK output on CNTL0/ADD0
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Table 25. Register Table (continued)
REGISTER
ADDRESS BITS NAME VALUE FUNCTION DEFAULT
VALUE
0x16 D7 HIGHIMM
0Legacy reverse control channel mode (power-up
default value depends on SD/HIM at power-up)
0, 1
1
High-immunity reverse control channel mode
(power-up default value depends on SD/HIM at
power-up)
D[6:0] — 1011010 Reserved 1011010
0x17 D[7:0] — 000XXXXX Reserved 000XXXXX
0x18 D[7:1] I2CSRCA XXXXXXX I2C Address translator source A 0000000
D0 —0Reserved 0
0x19 D[7:1] I2CDSTA XXXXXXX I2C Address translator destination A 0000000
D0 —0Reserved 0
0x1A D[7:1] I2CSRCB XXXXXXX I2C Address translator source B 0000000
D0 —0Reserved 0
0x1B D[7:1] I2CDSTB XXXXXXX I2C Address translator destination B 0000000
D0 —0Reserved 0
0x1C
D7 I2CLOCACK
0Acknowledge not generated when forward
channel is not available 1
1I2C to I2C-slave generates local acknowledge
when forward channel is not available
D[6:5] I2CSLVSH
00 352ns/117ns I2C setup/hold time
01
01 469ns/234ns I2C setup/hold time
10 938ns/352ns I2C setup/hold time
11 1046ns/469ns I2C setup/hold time
D[4:2] I2CMSTBT
000 8.47kbps (typ) I2C to I2C-Master bit-rate setting
101
001 28.3kbps (typ) I2C to I2C-Master bit-rate setting
010 84.7kbps (typ) I2C to I2C-Master bit-rate setting
011 105kbps (typ) I2C to I2C-Master bit-rate setting
100 173kbps (typ) I2C to I2C-Master bit-rate setting
101 339kbps (typ) I2C to I2C-Master bit-rate setting
110 533kbps (typ) I2C to I2C-Master bit-rate setting
111 837kbps (typ) I2C to I2C-Master bit-rate setting
D[1:0] I2CSLVTO
00 64µs (typ) I2C to I2C-Slave remote timeout
10
01 256µs (typ) I2C to I2C-Slave remote timeout
10 1024µs (typ) I2C to I2C-Slave remote timeout
11 No I2C to I2C-Slave remote timeout
0x1D
D[7:3] — 00000 Reserved 00000
D2 AUDUFBEH 0Audio FIFO repeats last audio word when FIFO is
empty 0
1Audio FIFO outputs all zeroes when FIFO is empty
D1 INVSCK 0Do not invert SCK at output 0
1 Invert SCK at output
D0 INVWS 0Do not invert WS at output 0
1 Invert WS at output
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Table 25. Register Table (continued)
X = Don’t care
REGISTER
ADDRESS BITS NAME VALUE FUNCTION DEFAULT
VALUE
0x1E D[7:0] ID 00100X10
Device identier
(MAX9276 = 0x22)
(MAX9280 = 0x26)
00100X10
(Read only)
0x1F
D[7:5] — 000 Reserved 000
(Read only)
D4 CAPS 0Not HDCP capable (MAX9276) (Read only)
1 HDCP capable (MAX9280)
D[3:0] REVISION XXXX Device revision (Read only)
0x40 to 0x59 D[7:0] AVINFO XXXXXXXX Video/Audio format/status/information bytes All zeroes
0x77 D[7:0] — XXXXXXXX (Read only)
0x78 D[7:0] AUDOUPER XXXXXXXX Audio FIFO last overow/underow period
(AUDIOMODE = 1 only) (Read only)
0x79
D7 AUDOU 0Audio FIFO is in underow (AUDIOMODE = 1 only) (Read only)
1 Audio FIFO is in overow (AUDIOMODE = 1 only)
D[6:0] — 0000XXX Reserved 0000XXX
(Read only)
0x7B D[7:0] LUTADDR XXXXXXXX LUT start address for write and read 00000000
0x7C
D[7:4] — 0000 Reserved 0000
D3 LUTPROG 0Disable LUT write and read 0
1 Enable LUT write and read
D2 BLULUTEN 0Disable blue LUT 0
1 Enable blue LUT
D1 GRNLUTEN 0Disable green LUT 0
1 Enable green LUT
D0 REDLUTEN 0Disable red LUT 0
1 Enable red LUT
0x7D D[7:0] REDLUT XXXXXXXX Red LUT value (see Table 11) 00000000
0x7E D[7:0] GREENLUT XXXXXXXX Green LUT value (see Table 11) 00000000
0x7F D[7:0] BLUELUT XXXXXXXX Blue LUT value (see Table 11) 00000000
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Table 26. HDCP Register Table (MAX9280 Only)
REGISTER
ADDRESS
SIZE
(Bytes) NAME READ/
WRITE FUNCTION DEFAULT VALUE
(hex)
0X80 to 0x84 5BKSV Read only HDCP receiver KSV (Read only)
0X85 to 0x86 2RI’ Read only Link verication response (Read only)
0X87 1 PJ’ Read only Enhanced link verication response (Read only)
0X88 to 0x8F 8AN Read/write Session random number 0x0000000000000000
0X90 to 0x94 5AKSV Read/write HDCP transmitter KSV 0x0000000000
0x95 1 BCTRL Read/write
D7 = PD_HDCP
1 = Power down HDCP circuits
0 = HDCP circuits normal
0x00
D[6:4] = Reserved
D3 = GPIO1_FUNCTION
1 = GPIO1 mirrors AUTH_STARTED
0 = normal GPIO1 operation
D2 = GPIO0_FUNCTION
1 = GPIO0 mirrors ENCRYPTION_ENABLE
0 = normal GPIO0 operation
D1 = AUTH_STARTED
1 = Authentication started (triggered by write
to AKSV)
0 = Authentication not started
D0 = ENCRYPTION_ENABLE
1 = Enable encryption
0 = Disable encryption
0x96 1 BSTATUS Read/write
D[7:2] = Reserved
0x00
D1 = NEW_DEV_CONN
1 = Set to 1 if a new connected device is
detected
0 = Set to 0 if no new device is connected
D0 = KSV_LIST_READY
1 = Set to 1 if KSV list and BINFO is ready
0 = Set to 0 if KSV list or BINFO is not ready
0x97 1 BCAPS Read/write
D[7:1] = Reserved
0x00
D0 = REPEATER
1 = Set to one if device is a repeater
0 = Set to zero if device is not a repeater
0x98 to 0x9F 8— Read only Reserved 0x0000000000000000
(Read only)
0XA0 to 0xA3 4 V’.H0 Read/write H0 part of SHA-1 hash value 0x00000000
0XA4 to 0xA7 4 V’.H1 Read/write H1 part of SHA-1 hash value 0x00000000
0XA8 to 0xAB 4 V’.H2 Read/write H2 part of SHA-1 hash value 0x00000000
0XAC to 0xAF 4 V’.H3 Read/write H3 part of SHA-1 hash value 0x00000000
0XB0 to 0xB3 4 V’.H4 Read/write H4 part of SHA-1 hash value 0x00000000
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Table 26. HDCP Register Table (MAX9280 Only) (continued)
REGISTER
ADDRESS
SIZE
(Bytes) NAME READ/
WRITE FUNCTION DEFAULT VALUE
(hex)
0XB4 to 0xB5 2BINFO Read/write
D[15:12] = Reserved
0x0000
D11 = MAX_CASCADE_EXCEEDED
1 = Set to one if more than seven cascaded
devices attached
0 = Set to zero if seven or fewer cascaded
devices attached
D[10:8] = DEPTH
Depth of cascaded devices
D7 = MAX_DEVS_EXCEEDED
1 = Set to one if more than 14 devices
attached
0 = Set to zero if 14 or fewer devices
attached
D[6:0] = DEVICE_COUNT
Number of devices attached
0xB6 1 GPMEM Read/write General-purpose memory byte 0x00
0xB7 to 0xB9 3— Read only Reserved 0x000000
0xBA to 0xFF 70 KSV_LIST Read/write List of KSVs downstream repeaters and
receivers (maximum of 14 devices) All zero
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/V denotes an automotive qualified product.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
**HDCP parts require registration with Digital Content
Protection, LLC..
PART TEMP RANGE PIN-
PACKAGE HDCP
MAX9276GTN+ -40°C to +105°C 56 TQFN-EP* NO
MAX9276GTN/V+ -40°C to +105°C 56 TQFN-EP* NO
MAX9276GGN/VY+ -40°C to +105°C 56 QFND-EP* NO
MAX9280GTN+ -40°C to +105°C 56 TQFN-EP* YES**
MAX9280GTN/V+ -40°C to +105°C 56 TQFN-EP* YES**
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
56 TQFN-EP T5688+2 21-0135 90-0046
56 QFND-EP G5688Y+1 21-0704 90-0423
PCLK
RGBHV
GPU
ECU
UART TX
RX
INT
IMS
AUDIO
WS
SCK
SD
PCLKIN
DIN(26:0)
CDS/CNTL3
LMN0
LMN1
OUT-
CONF3
CONF2
CONF0
CONF1
OUT+
RX/SDA
TX/SCL
GPO/HIM
WS
MS/CNTLO
SD
SCK
SCL
SDA
PCLKOUT
DOUT(26:0)
I2CSEL
INT
RX/SDA
TX/SCL
LOCK
IN+
INTOUT/ADD2
CNTL3/ADD1
CNTL0/ADD0
IN-
WS
SD/HIM
SCK
DOUT28/MCLK
4.99kΩ4.99kΩ
45.3kΩ45.3kΩ
49.9kΩ49.9kΩ
WS
SD
SCK
MCLK
PCLK
RGB
TO PERIPHERALS
DISPLAY
MAX9850
MAX9276
MAX9280
MAX9275
MAX9279
NOTE: NOT ALL PULLUP/PULLDOWN RESISTORS ARE SHOWN. SEE PIN DESCRIPTION FOR DETAILS.
VIDEO-DISPLAY APPLICATION
LFLT LFLT
CX/TP
Typical Application Circuit
Ordering Information Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
Chip Information
PROCESS: CMOS
MAX9276/MAX9280 3.12Gbps GMSL Deserializers
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REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
03/13 Initial release —
111/15
Fixed typos, claried functions, added new simplied diagram and Figure 2a,
deleted Table 1 renumbering remaining tables, added QFND package, and
removed future product designations from Ordering Information table
1, 7, 9, 13, 17, 21,
25–30, 32, 33,
36–38, 43–50,
52–63, 65–73
Revision History
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.