I2C Bus Interface Slave - Base version ver 1.12 OVERVIEW I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data transmission over a short distance between many devices. The DI2CSB provides an interface between a passive target device e.g. memory, LCD display, pressure sensors etc. and an I2C bus. It can works as a slave receiver or transmitter depending on working mode determined by a master device. Very simple interface, composed with the read, write and data signals, allows easy connection to the target devices. The core doesn't required programming and is ready to work after power up/reset. The read, write, burst read, burst write and repeated start transmissions are automatically recognized by the core. The core incorporates all features required by I2C specification. The DI2CSB supports the following transmission modes: Standard, Fast and High Speed. KEY FEATURES Conforms to v.2.1 of the I2C specification Slave operation Slave transmitter Slave receiver Support for reads, writes, burst reads, burst writes, and repeated start 7-bit addressing No programming required Simple interface allows easy connection to target device e.g. memory, LCD display, pressure sensors etc. Fully synthesizable Static synchronous design with positive edge clocking and synchronous reset No internal tri-states Scan test ready APPLICATIONS Embedded microprocessor boards Consumer and professional audio/video Home and automotive radio Low-power applications Communication systems Cost-effective reliable automotive systems DELIVERABLES Supports 3 transmission speed modes Standard (up to 100 kb/s) Fast (up to 400 kb/s) High Speed (up to 3,4 Mb/s) Allows operation from a wide range of input clock frequencies All trademarks mentioned in this document are trademarks of their respective owners. Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. Tests with reference responses Technical documentation Installation notes HDL core specification Datasheet Synthesis scripts Example application Technical support IP Core implementation support 3 months maintenance SYMBOL datai(7:0) datao(7:0) rd wr scli sdai sdao clk rst Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support LICENSING PINS DESCRIPTION PIN TYPE DESCRIPTION clk input Global clock rst input Global reset datai(7:0) input Data bus from target device Single Design license allows use IP Core in single FPGA bitstream and ASIC implementation. scli input I C bus clock line (input) sdai input I C bus data line (input) datao(7:0) output Data bus to target device Unlimited Designs, One Year licenses allow use IP Core in unlimited number of FPGA bitstreams and ASIC implementations. wr output Write strobe for target device Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simply. 2 2 rd output Read strobe for target device sdao output I C bus data line (output) 2 In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited. There is no time restriction except One Year license where time of use is limited to 12 months. Single Design license for VHDL, Verilog source code called HDL Source Encrypted, or plain text EDIF called Netlist One Year license for Encrypted Netlist only Unlimited Designs license for HDL Source Netlist Upgrade from HDL Source to Netlist Single Design to Unlimited Designs All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. BLOCK DIAGRAM PERFORMANCE Figure below shows the DI2CSB IP Core block diagram. The following table gives a survey about the Core area and performance in the LATTICE(R) devices after Place & Route (all key features have been included): Target device Interface - Performs the interface functions between DI2CSB internal blocks and target device. Allows easy connection of the core to a passive devices e.g. memory, LCD display, pressure sensors, I/O devices etc.. Receive Data datai(7:0) datao(7:0) we rd Shift Register Target device Interface Send Data Input Filter sdai Output Register sdao Speed LUTs/PFUs Fmax grade ispXPGA -4 80/21 149 MHz ORCA 4 -3 90/15 101 MHz Core performance in LATTICE(R) devices Device Own address detection Control Logic rst clk Synchronization Logic Input Filter scli Control Logic - Manages execution of all commands sent via interface. Synchronizes internal data flow. Shift Register - Controls SDA line, performs data and address shifts during the data transmission and reception. Input Filter - Performs spike filtering. Synchronization Logic - Synchronizes data and address shifts during the data transmission and reception. SCLI spikes are filtered by this unit. All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. - Spike filtering User defined timing High-speed mode Fast mode - Standard mode - - 10-bit addressing - - 7-bit addressing Arbitration - Clock synchronization Passive device interface CPU interface - Interrupt generation DI2CM DI2CS DI2CSB Slave operation Master operation 2.1 2.1 2.1 2 Design I C specification version The main features of each Digital Core Design I2C compliant cores have been summarized in table below. It gives a briefly member characterization helping user to select the most suitable IP Core for its application. - 2 I C cores summary table CONTACTS For any modification or special request please contact to Digital Core Design or local distributors. Headquarters: Wroclawska 94 41-902 Bytom, POLAND @ddccdd..ppll e-mail: iinnffoo@ tel. : +48 32 282 82 66 fax : +48 32 282 74 37 Field Office: Texas Research Park 14815 Omicron Dr. suite 100 San Antonio, TX 78245,USA e-mail: iinnffooU USS@ @ddccdd..ppll tel. : +1 210 422 8268 fax : +1 210 679 7511 Distributors: MTC - Micro Tech Components GmbH AM Reitweg 15 89407 Dillingen, GERMANY MTTC Ciinnffoo@ @m mttcc..ddee e-mail : M tel. : +49 9071 7945-0 fax : +49 9071 7945-20 Territory: Germany, Austria, Switzerland All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.