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are trademarks of their respective owners. http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
I2C Bus Interface Slave - Base version
ver 1.12
OVERVIEW
I2C is a two-wire, bi-directional serial bus that
provides a simple and efficient method of
data transmission over a short distance be-
tween many devices. The DI2CSB provides
an interface between a passive target device
e.g. memory, LCD display, pressure sensors
etc. and an I2C bus. It can works as a slave
receiver or transmitter depending on working
mode determined by a master device. Very
simple interface, composed with the read,
write and data signals, allows easy connec-
tion to the target devices. The core doesn’t
required programming and is ready to work
after power up/reset. The read, write, burst
read, burst write and repeated start transmis-
sions are automatically recognized by the
core. The core incorporates all features re-
quired by I2C specification. The DI2CSB sup-
ports the following transmission modes:
Standard, Fast and High Speed.
KEY FEATURES
● Conforms to v.2.1 of the I2C specification
● Slave operation
○ Slave transmitter
○ Slave receiver
● Supports 3 transmission speed modes
○ Standard (up to 100 kb/s)
○ Fast (up to 400 kb/s)
○ High Speed (up to 3,4 Mb/s)
● Allows operation from a wide range of
input clock frequencies
● Support for reads, writes, burst reads,
burst writes, and repeated start
● 7-bit addressing
● No programming required
● Simple interface allows easy connection
to target device e.g. memory, LCD dis-
play, pressure sensors etc.
● Fully synthesizable
● Static synchronous design with positive
edge clocking and synchronous reset
● No internal tri-states
● Scan test ready
APPLICATIONS
● Embedded microprocessor boards
● Consumer and professional audio/video
● Home and automotive radio
● Low-power applications
● Communication systems
● Cost-effective reliable automotive sys-
tems
DELIVERABLES
♦ Source code:
◊ VHDL Source Code or/and
◊ VERILOG Source Code or/and
◊ Encrypted, or plain text EDIF netlist
♦ VHDL & VERILOG test bench environ-
ment
◊ Active-HDL automatic simulation mac-
ros
◊ ModelSim automatic simulation macros
All trademarks mentioned in this document http://www.DigitalCoreDesign.com
are trademarks of their respective owners. http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
◊ Tests with reference responses
♦ Technical documentation
◊ Installation notes
◊ HDL core specification
◊ Datasheet
♦ Synthesis scripts
♦ Example application
♦ Technical support
◊ IP Core implementation support
◊ 3 months maintenance
● Delivery the IP Core updates, minor
and major versions changes
● Delivery the documentation updates
● Phone & email support
LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of
IP Core easy and simply.
Single Design license allows use IP Core in
single FPGA bitstream and ASIC implemen-
tation.
Unlimited Designs, One Year licenses allow
use IP Core in unlimited number of FPGA
bitstreams and ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time restric-
tion except One Year license where time of
use is limited to 12 months.
● Single Design license for
○ VHDL, Verilog source code called HDL
Source
○ Encrypted, or plain text EDIF called Netlist
● One Year license for
○ Encrypted N et lis t only
● Unlimited Designs license for
○ HDL Source
○ Netlist
● Upgrade from
○ HDL Source to Netlist
○ Single Design to Unlimited Designs
SYMBOL
datai(7:0)
rd
wr
clk
rst
scli
sdai sdao
datao(7:0)
PINS DESCRIPTION
PIN TYPE DESCRIPTION
clk input Global clock
rst input Global reset
datai(7:0) input Data bus from target device
scli input I2C bus clock line (input)
sdai input I2C bus data line (input)
datao(7:0) output Data bus to target device
wr output Write strobe for target device
rd output Read strobe for target device
sdao output I2C bus data line (output)
All trademarks mentioned in this document http://www.DigitalCoreDesign.com
are trademarks of their respective owners. http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
BLOCK DIAGRAM
Figure below shows the DI2CSB IP Core
block diagram.
Target device Interface – Performs the inter-
face functions between DI2CSB internal
blocks and target device. Allows easy con-
nection of the core to a passive devices e.g.
memory, LCD display, pressure sensors, I/O
devices etc..
datai
(
7:0
)
datao
(
7:0
)
rd
we
rst
clk
Target device
Interface
sdai
sdao
scli
Input
Filter
Output
Register
Shift
Register
Input
Filter
Control
Logic
Synchronization
Logic
Send
Data
Receive
Data
Receive
Data
Own
address
detection
Control Logic – Manages execution of all
commands sent via interface. Synchronizes
internal data flow.
Shift Register – Controls SDA line, performs
data and address shifts during the data
transmission and reception.
Input Filt er – Performs spike filtering.
Synchronization Logic – Synchronizes data
and address shifts during the data transmis-
sion and reception. SCLI spikes are filtered
by this unit.
PERFORMANCE
The following table gives a survey about the
Core area and performance in the LATTICE®
devices after Place & Route (all key features
have been included):
Device Speed
grade LUTs/PFUs Fmax
ispXPGA -4 80/21 149 MHz
ORCA 4 -3 90/15 101 MHz
Core performance in LATTICE® devices
All trademarks mentioned in this document http://www.DigitalCoreDesign.com
are trademarks of their respective owners. http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
The main features of each Digital Core Design I2C compliant cores have been summarized in table
below. It gives a briefly member characterization helping user to select the most suitable IP Core
for its application.
Design
I2C specification
version
Master operation
Slave operation
CPU interface
Passive device
interface
Interrupt genera-
tion
Clock synchroni-
zation
Arbitration
7-bit addressing
10-bit addressing
Standard mode
Fast mode
High-speed mode
User defined tim-
ing
Spike filtering
DI2CM 2.1 - -
DI2CS 2.1 - - - -
DI2CSB 2.1 - - - - - - -
I2C cores summary table
CONTACTS
For any modification or special request
please contact to Digital Core Design or local
distributors.
Headquarters:
Wroclawska 94
41-902 Bytom, POLAND
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tel. : +48 32 282 82 66
fax : +48 32 282 74 37
Field Office:
Texas Research Park
14815 Omicron Dr. suite 100
San Antonio, TX 78245,USA
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tel. : +1 210 422 8268
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Distributors:
MTC - Micro Tech Components GmbH
AM Reitweg 15
89407 Dillingen, GERMANY
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