January 2017
DocID18093 Rev 7
1/26
This is information on a product in full production.
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54AC164245
Rad-hard 16-bit transceiver 3.3 V to 5 V bidirectional level shifter
Datasheet - production data
Features
Fully compatible with 54ACS164245
Dual supply bidirectional level shifter
Extended voltage range from 2.3 V to 5.5 V
Separated enable pin for 3-state output
Schmidt-triggered I/Os: 100 mV hysteresis
Internal 26 Ω limiting resistor on each I/O
High speed: Tpd = 8 ns maximum
Fail safe
Cold spare
Hermetic package
100 krad (Si) at any Mil1019 dose rate
SEL immune to 110 MeV.cm2/mg LET ions
RHA QML-V qualified
Description
The 54AC164245 is a rad-hard advanced high-
speed CMOS, Schmitt trigger, 16-bit,
bidirectional, multi-purpose transceiver with
3-state outputs and cold sparing.
Designed for use as an interface between a 5 V
bus and a 3.3 V bus in mixed 5 V/3.3 V supply
systems, it achieves high-speed operation while
maintaining the CMOS low-power dissipation.
All pins have cold spare buffers to change them
to high impedance when VDD is tied to ground.
This IC is intended for two-way asynchronous
communication between the data buses. The
direction of the data transmission is determined
by the nDIR inputs.
The A port interfaces with the 3.3 V bus but can
also operate at 2.3 V. The B port operates with
the 5 V bus.
Table 1: Device summary
Parameter
RHRAC164245K1
RHRAC164245K01V
SMD
—
5962R9858008VYC
Quality level
Engineering model
QML-V flight
Package
Flat-48
Lead finish
Gold
Mass
1.50 g
EPPL (1)
—
Yes
Temp. range
-55 °C to 125 °C
Notes:
(1)EPPL = ESA preferred part list
Contents
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Contents
1 Functional description .................................................................... 3
1.1 Cold spare ......................................................................................... 4
1.2 Power-up ........................................................................................... 5
1.3 Pin connections ................................................................................. 6
2 Absolute maximum ratings and operating conditions ................. 7
3 Electrical characteristics ................................................................ 9
4 Radiations ...................................................................................... 17
5 Test circuit ..................................................................................... 18
6 Package information ..................................................................... 21
6.1 Ceramic Flat-48 package information ............................................. 22
7 Ordering information ..................................................................... 23
8 Other information .......................................................................... 24
8.1 Data code ........................................................................................ 24
8.2 Documentation ................................................................................ 24
9 Revision history ............................................................................ 25
54AC164245
Functional description
DocID18093 Rev 7
3/26
1 Functional description
Figure 1: Logic diagram
Table 2: Function table
Enable, OEx
Direction, DIRx
Operation
L
L
B data to A bus
H
A data to B bus
H
X
Isolation
Functional description
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1.1 Cold spare
The 54AC164245 features a cold spare input and output buffer. In high reliability
applications, cold sparing enables a redundant device to be tied to the data bus with its
power supply at 0 V (VDD = VSS = 0 V, VDD - VSS = 0 V) without affecting the bus signals or
injecting current from the I/Os to the power supplies. Cold sparing also allows redundant
devices that are not powered to be switched on only when required. Power consumption is
therefore reduced by switching off the redundant circuit. This has no impact on the
application. Cold sparing is achieved by implementing a high impedance between I/Os and
VDD. The ESD protection is ensured through a non-conventional dedicated structure. Using
cold spare on Bus A and Bus B separately is not allowed. In cold spare, both VDD1 and VDD2
must be at 0 V.
Figure 2: Cold spare and cold redundancy
1. R = Ioff/VDD
54AC164245
Functional description
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1.2 Power-up
During power-up, all outputs are forced to high impedance. The high-impedance state is
maintained approximately until VDD is high, thus avoiding any transient and erroneous
signals during power-up.
However, the 54AC164245 must be supplied with VDD1 higher or equal to VDD2.
Figure 3: Power-up
1. In operating mode, VDD1 must be higher than or equal to VDD2 (VDD2 higher than VDD1 is forbidden)
2. In power-up, VDD1 must be powered up before VDD2
3. In power-down, VDD2 must be powered down before VDD1
Functional description
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1.3 Pin connections
Figure 4: Pin connections
Table 3: Pin descriptions
Pin number
Symbol
Name and function
1
DIR1
Direction control inputs
2, 3, 5, 6, 8, 9, 11, 12
1B1 to 1B8
Side B inputs or 3-state outputs (5 V port)
4,10, 15, 21, 28, 34, 39, 45
VSS
Reference voltage to ground
7, 18
VDD1
Supply voltage (5 V)
13, 14, 16, 17, 19, 20, 22, 23
2B1 to 2B8
Side B inputs or 3-state outputs (5 V port)
24
DIR2
Direction control inputs
25
nG2
Output enable inputs (active low)
31, 42
VDD2
Supply voltage (3.3 V)
47, 46, 44, 43, 41, 40, 38, 37
1A1 to 1A8
Side A inputs or 3-state outputs (3.3 V port)
36, 35, 33, 32, 30, 29, 27, 26
2A1 to 2A8
Side A inputs or 3-state outputs (3.3 V port)
48
nG1
Output enable inputs (active low)
54AC164245
Absolute maximum ratings and operating
conditions
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2 Absolute maximum ratings and operating conditions
Absolute maximum ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied.
Stresses above the absolute maximum rating may cause permanent damage to the device.
Extended operation at the maximum levels may degrade performance and affect reliability.
Unless otherwise noted, all voltages are referenced to VSS.
The limits for the parameters specified in Table 4: "Absolute maximum ratings" apply over
the full specified VDD range and case temperature range of -55 °C to 125 °C.
Table 4: Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDD1
5 V supply voltage (1)
-0.3 to 7
V
VDD2
3 V supply voltage
VIA
DC input voltage range port A
-0.3 to VDD1 + 0.3 V
VIB
DC input voltage range port B
VOA
DC output voltage range port A
VOB
DC output voltage range port B
IIA
DC input currents port A, anyone input
± 10
mA
IIB
DC input currents port B, anyone input
Tstg
Storage temperature range
-65 to 150
°C
TL
Lead temperature (10 s)
300
TJ
Junction temperature range
175
Rthjc
Thermal resistance junction to case (2)
8
°C/W
ESD
HBM: human body model (3)
2
kV
Notes:
(1)VDD1 must be higher or equal to VDD2 (VDD2 higher than VDD1 is forbidden).
(2)Short-circuits can cause excessive heating and destructive dissipation. Values are typical.
(3)Human body model: a 100 pF capacitor is charged to the specified voltage, then discharged through a
1.5 kΩ resistor between two pins of the device. This is done for all couples of connected pin combinations
while the other pins are floating.
Absolute maximum ratings and operating
conditions
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In Table 5: "Operating conditions", unless otherwise noted, all voltages are referenced to
VSS.
Table 5: Operating conditions
Symbol
Parameter
Value
Unit
VDD1
Supply voltage (1)
4.5 to 5.5 or 2.3 to 3.6
V
VDD2
2.3 to 3.6 or 4.5 to 5.5
VI
Input voltage
0 to VDD1
VO
Output voltage
Top
Operating temperature
-55 to 125
°C
dt / dv
Input rise and fall time VCC = 3.0, 4.5 or 5.5 (2)
0 to 8
ns / V
Notes:
(1)VCCA must be higher or equal to VCCB (VCCB higher than VCCA is forbidden).
(2)Derates system propagation delays by difference in rise time to switch point for tr or tf > 1 ns/V.
54AC164245
Electrical characteristics
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3 Electrical characteristics
In the table below, Top = -55 °C to 125 °C, VDD1 = 4.5 V to 5.5 V, VDD2 = 2.7 V to 3.6 V,
unless otherwise specified. Each input/output, as applicable, is tested at the specified
temperature, for the specified limits, according to the tests specified in TABLE IA from the
SMD 5962-98580 DLA Agency Spec. Non-designated output terminals are high-level logic,
low-level logic or open, except for all IDD tests, where the output terminals are open. When
performing these tests, the current meter must be placed in the circuit so that all current
flows through the meter.
Table 6: DC specifications
Symbol
Parameter
Port
voltage
Test condition (VDD) (1)
Limits
Unit
Min.
Max.
VT+
Schmitt trigger positive going
threshold port A
3.3 V
VDD1 = 4.5 and 5.5 V
0.7
VDD2
V
VDD2 = 2.7 and 3.6 V
5 V
VDD1 = 4.5 and 5.5 V
VDD2 = 4.5 and 5.5 V
Schmitt trigger positive going
threshold port B
3.3 V
VDD2 = 2.7 and 3.6 V
0.7
VDD1
VDD1 = 2.7 and 3.6 V
5 V
VDD1 = 4.5 and 5.5 V
VDD2 = 2.7 and 3.6 V
VT-
Schmitt trigger positive going
threshold port A
3.3 V
VDD1 = 4.5 and 5.5 V
0.3
VDD2
VDD2 = 2.7 and 3.6 V
5 V
VDD1 = 4.5 and 5.5 V
VDD2 = 4.5 and 5.5 V
Schmitt trigger positive going
threshold port B
3.3 V
VDD2 = 2.7 and 3.6 V
0.3
VDD1
VDD1 = 2.7 and 3.6 V
5 V
VDD1 = 4.5 and 5.5 V
VDD2 = 2.7 and 3.6 V
VH
Schmitt trigger range of hysteresis
port A
3.3 V
VDD1 = 4.5 and 5.5 V
0.4
VDD2 = 2.7 and 3.6 V
5 V
VDD1 = 4.5 and 5.5 V
0.6
VDD2 = 4.5 and 5.5 V
Schmitt trigger range of hysteresis
port B
3.3 V
VDD2 = 2.7 and 3.6 V
0.4
VDD1 = 2.7 and 3.6 V
5 V
VDD1 = 4.5 and 5.5 V
0.6
VDD2 = 2.7 and 3.6 V
Electrical characteristics
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Symbol
Parameter
Port
voltage
Test condition (VDD) (1)
Limits
Unit
Min.
Max.
IIH
Input current high port A
(for input under test VI = VDD2
other inputs, VI = VDD2 or VSS)
3.3 V
VDD1 = 5.5 V
3
µA
VDD2 = 3.6 V
5 V
VDD1 = 5.5 V
VDD2 = 5.5 V
Input current high port B
(for input under test VI = VDD1
other inputs, VI = VDD1 or VSS)
3.3 V
VDD1 = 3.6 V
VDD2 = 3.6 V
5 V
VDD1 = 5.5 V
VDD2 = 3.6 V
IIL
Input current low port A
(for input under test VI = VSS other
inputs, VI = VDD2 or VSS)
3.3 V
VDD1 = 5.5 V
-1
VDD2 = 3.6 V
5 V
VDD1 = 5.5 V
VDD2 = 5.5 V
Input current low port B
(for input under test VI = VSS other
inputs, VI = VDD1 or VSS)
3.3 V
VDD1 = 3.6 V
VDD2 = 3.6 V
5 V
VDD1 = 5.5 V
VDD2 = 3.6 V
ICS
Input current cold spare mode port
A = port B = 5.5 V = VI
DIRn = 5.5 V, OEn = 5.5 V
VDD1 = 0 V
-1
5
Input current cold spare mode port
A = port B = 5.5 V = VI
DIRn = 0V, OEn = 5.5 V
Input current cold spare mode port
A = port B = 5.5 V = VI
DIRn = 5.5 V, OEn = 0 V
Input current cold spare mode port
A = port B = 5.5 V = VI
DIRn = 0 V, OEn = 0 V
VOL1
Low level output voltage port A,
IOL = 8 mA for all inputs affecting
output under test, VI = VDD2 or VSS
3.3 V
VDD1 = 4.5 V
0.5
V
VDD2 = 2.7 V
5 V
VDD1 = 4.5 V
0.4
VDD2 = 4.5 V
Low level output voltage port B,
IOL = 8 mA for all inputs affecting
output under test, VI = VDD1 or VSS
3.3 V
VDD1 = 2.7 V
0.5
VDD2 = 2.7 V
5 V
VDD1 = 4.5 V
0.4
VDD2 = 2.7 V
54AC164245
Electrical characteristics
DocID18093 Rev 7
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Symbol
Parameter
Port
voltage
Test condition (VDD) (1)
Limits
Unit
Min.
Max.
VOL2
Low level output voltage
3.3 V
VDD1 = 4.5 V
0.2
V
VDD2 = 2.7 V
Port A, IOL = 100 µA for all inputs
affecting output under test,
VI = VDD2 or VSS
5 V
VDD1 = 4.5 V
VDD2 = 4.5 V
Low level output voltage
3.3 V
VDD1 = 2.7 V
VDD2 = 2.7 V
Port B, IOL = 100 µA for all inputs
affecting output under test,
VI = VDD1 or VSS
5 V
VDD1 = 4.5 V
VDD2 = 2.7 V
VOH1
High level output voltage port A,
IOH = -8 mA for all inputs affecting
output under test, VI = VDD2 or VSS
3.3 V
VDD1 = 4.5 V
VDD2-
0.9
VDD2 = 2.7 V
5 V
VDD1 = 4.5 V
VDD2-
0.7
VDD2 = 4.5 V
High level output voltage port B,
IOH = -8 mA for all inputs affecting
output under test, VI = VDD1 or VSS
3.3 V
VDD1 = 2.7 V
VDD1-
0.9
VDD2 = 2.7 V
5 V
VDD1 = 4.5 V
VDD1-
0.7
VDD2 = 2.7 V
VOH2
High level output voltage port A,
IOH = - 100 µA for all inputs
affecting output under test,
VI = VDD2 or VSS
3.3 V
VDD1 = 4.5 V
VDD2-
0.2
VDD2 = 2.7 V
5 V
VDD1 = 4.5 V
VDD2 = 4.5 V
High level output voltage port B,
IOH = - 100 µA for all inputs
affecting output under test,
VI = VDD1 or VSS
3.3 V
VDD1 = 2.7 V
VDD1-
0.2
VDD2 = 2.7 V
5 V
VDD1 = 4.5 V
VDD2 = 2.7 V
Electrical characteristics
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Symbol
Parameter
Port
voltage
Test condition (VDD) (1)
Limits
Unit
Min.
Max.
IOL (2)
Output current (sink) port A,
VI = VSS
3.3 V
VDD1 = 4.5 V
8.0
mA
VDD2 = 2.7 V
VOL = 0.5 V
5 V
VDD1 = 4.5 V
VDD2 = 4.5 V
VOL = 0.4 V
Output current (sink) port B,
VI = VSS
3.3 V
VDD1 = 2.7 V
VDD2 = 2.7 V
VOL = 0.5 V
5 V
VDD1 = 4.5 V
VDD2 = 2.7 V
VOL = 0.4 V
IOH (3)
Output current (source) port A,
VI = VDD2 or VSS
3.3 V
VDD1 = 4.5 V
-8.0
VDD2 = 2.7 V
VOH = VDD2-0.9 V
5 V
VDD1 = 4.5 V
VDD2 = 4.5 V
VOH = VDD2-0.7 V
Output current (source) port B,
VI = VDD2 or VSS
3 V
VDD1 = 2.7 V
VDD2 = 2.7 V
VOH = VDD2-0.9 V
5 V
VDD1 = 4.5 V
VDD2 = 2.7 V
VOH = VDD2-0.7 V
IOZH
Three-state output leakage
current high port A, for input under
test, VI = VDD2 other inputs,
VO = VDD2 VI = VDD2 or VSS
3.3 V
VDD1 = 5.5 V
3.0
µA
VDD2 = 3.6 V
VDD1 = 5.5 V
VDD2 = 5.5 V
Three-state output leakage
current high port B, for input under
test, VI = VDD1 other inputs,
VO = VDD1 VI = VDD1 or VSS
3.3 V
VDD1 = 3.6 V
VDD2 = 3.6 V
5 V
VDD1 = 5.5 V
VDD2 = 3.6 V
54AC164245
Electrical characteristics
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Symbol
Parameter
Port
voltage
Test condition (VDD) (1)
Limits
Unit
Min.
Max.
IOZL
Three-state output leakage
current low port A, for input under
test, VI = VSS other inputs,
VO = VSS VI = VDD2 or VSS
3.3 V
VDD1 = 5.5 V
-1.0
µA
VDD2 = 3.6 V
5 V
VDD1 = 5.5 V
VDD2 = 5.5 V
Three-state output leakage
current low port B, for input under
test, VI = VSS other inputs,
VO = VSS VI = VDD1 or VSS
3.3 V
VDD1 = 3.6 V
VDD2 = 3.6 V
5 V
VDD1 = 5.5 V
VDD2 = 3.6 V
IOS (4)
Short circuit output current port A,
VO = VDD2 or VSS
3.3 V
VDD1 = 4.5 to 5.5 V
-100
100
mA
VDD2 = 2.7 to 3.6 V
5 V
VDD1 = 4.5 to 5.5 V
-200
200
VDD2 = 4.5 to 5.5 V
Short circuit output current port B,
VO = VDD1 or VSS
3.3 V
VDD1 = 2.7 to 3.3 V
-100
100
VDD2 = 2.7 to 3.6 V
5 V
VDD1 = 4.5 to 5.5 V
-200
200
VDD2 = 2.7 to 3.6 V
PD (3) (4) (5)
Power dissipation, port A,
CL = 50 pF per switching output
3.3 V
VDD1 = 4.5 to 5.5 V
1.5
mW/
MHz
VDD2 = 2.7 to 3.6 V
5 V
VDD1 = 4.5 to 5.5 V
2.0
VDD2 = 4.5 to 5.5 V
Power dissipation, port B,
CL = 50 pF per switching output
3.3 V
VDD1 = 2.7 to 3.3 V
1.5
VDD2 = 2.7 to 3.6 V
5 V
VDD1 = 4.5 to 5.5 V
2.0
VDD2 = 2.7 to 3.6 V
IDDQ
Quiescent supply current port A,
VI = VDD2 or VSS
5 V
VDD1 = 5.5 V at 25 °C
10
µA
VDD2 = 5.5 V at 25 °C
VDD1 = 5.5 V at -55 to
125 °C
100
VDD2 = 5.5 V at -55 to
125 °C
Quiescent supply current port B,
VI = VDD1 or VSS
5 V
VDD1 = 5.5 V at 25 °C
10
VDD2 = 5.5 V at 25 °C
VDD1 = 5.5 V at -55 to
125 °C
100
VDD2 = 5.5 V at -55 to
125 °C
Electrical characteristics
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Symbol
Parameter
Port
voltage
Test condition (VDD) (1)
Limits
Unit
Min.
Max.
CI
Input capacitance
f = 1 MHz
VDD1 = VDD2 = 0 V
15
pF
CO
Output capacitance
f = 1 MHz
VDD1 = VDD2 = 0 V
(6)
Functional test VIH = 0.7 VDD,
VIL = 0.3 VDD
VDD1 = 4.5 to 5.5 V
L
H
VDD2 = 2.7 to 3.6 V
Notes:
(1)This device requires both VDD1 and VDD2 power supplies for operation. The power supply is indicated and followed by the
voltage to which the power supply is set to the given test
(2)This parameter is supplied as a design limit but not guaranteed or tested
(3)Power does not include power contribution of any CMOS output sink current
(4)No more than one output should be shorted at a time for a maximum duration of one second
(5)Power dissipation specified per switching output
(6)Tests must be performed in sequence and include attribute data only. Functional tests should include the truth table and other
logic patterns used for fault detection. The test vectors used to verify the truth table must, at the minimum, test all the functions of
each input and output. All possible input to output logic patterns per function should be guaranteed, if not tested, to the function
table, Table 2. Functional tests are performed in sequence as approved by the qualifying activity on qualified devices. Functional
tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min + 20%, -0%); VIL =
VIL(max + 0%, -50%), as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices are guaranteed to VIH(min) and
VIL(max).
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Electrical characteristics
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In the table below, data are guaranteed by design but, not tested.
Table 7: AC electrical characteristics
Symbol
Parameter
Port voltage
Test condition
(VDD)
Limits
Unit
Min.
Max.
tPLH
Propagation delay time, data to
bus (active low) CL = 50 pF
Port A = 3.3 V,
Port B = 5 V
VDD1 = 4.5 to 5.5 V
1.0
20
ns
VDD2 = 2.7 to 3.6 V
Port A = Port B = 3.3 V
VDD1 = 2.7 to 3.6 V
VDD2 = 2.7 to 3.6 V
Port A = Port B = 5 V
VDD1 = 4.5 to 5.5 V
15
VDD2 = 4.5 to 5.5 V
tPHL
Propagation delay time, data to
bus (active high) CL = 50 pF
Port A = 3.3 V,
Port B = 5 V
VDD1 = 4.5 to 5.5 V
20
VDD2 = 2.7 to 3.6 V
Port A = Port B = 3.3 V
VDD1 = 2.7 to 3.6 V
VDD2 = 2.7 to 3.6 V
Port A = Port B = 5 V
VDD1 = 4.5 to 5.5 V
15
VDD2 = 4.5 to 5.5 V
tPZL
Propagation delay time, output
enable, OEn to bus (active low),
CL = 50 pF
Port A = 3.3 V,
Port B = 5 V
VDD1 = 4.5 to 5.5 V
18
VDD2 = 2.7 to 3.6 V
Port A = Port B = 3.3 V
VDD1 = 2.7 to 3.6 V
18
VDD2 = 2.7 to 3.6 V
Port A = Port B = 5 V
VDD1 = 4.5 to 5.5 V
12
VDD2 = 4.5 to 5.5 V
tPZH
Propagation delay time, output
enable, OEn to bus (active high),
CL = 50 pF
Port A = 3.3 V,
Port B = 5 V
VDD1 = 4.5 to 5.5 V
18
VDD2 = 2.7 to 3.6 V
Port A = Port B = 3.3 V
VDD1 = 2.7 to 3.6 V
VDD2 = 2.7 to 3.6 V
Port A = Port B = 5 V
VDD1 = 4.5 to 5.5 V
12
VDD2 = 4.5 to 5.5 V
tPLZ
Propagation delay time, output
disable, OEn to bus (low
impedance), CL = 50 pF
Port A = 3.3 V,
Port B = 5 V
VDD1 = 4.5 to 5.5 V
20
VDD2 = 2.7 to 3.6 V
Port A = Port B = 3.3 V
VDD1 = 2.7 to 3.6 V
VDD2 = 2.7 to 3.6 V
Port A = Port B = 5 V
VDD1 = 4.5 to 5.5 V
15
VDD2 = 4.5 to 5.5 V
Electrical characteristics
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Symbol
Parameter
Port voltage
Test condition
(VDD)
Limits
Unit
Min.
Max.
tPHZ
Propagation delay time, output
disable, OEn to bus (high
impedance), CL = 50 pF
Port A = 3.3 V,
Port B = 5 V
VDD1 = 4.5 to 5.5 V
1.0
18
ns
VDD2 = 2.7 to 3.3 V
Port A = Port B = 3.3 V
VDD1 = 2.7 to 3.3 V
VDD2 = 2.7 to 3.3 V
Port A = Port B = 5 V
VDD1 = 4.5 to 5.5 V
12
VDD2 = 4.5 to 5.5 V
tPZL
Propagation delay time, output
enable, DIRn to bus (active low),
CL = 50 pF
Port A = 3.3 V,
Port B = 5 V
VDD1 = 4.5 to 5.5 V
18
VDD2 = 2.7 to 3.3 V
Port A = Port B = 3.3 V
VDD1 = 2.7 to 3.3 V
VDD2 = 2.7 to 3.3 V
Port A = Port B = 5 V
VDD1 = 4.5 to 5.5 V
12
VDD2 = 4.5 to 5.5 V
tPZH
Propagation delay time, output
enable, DIRn to bus (active high),
CL = 50 pF
Port A = 3.3 V,
Port B = 5 V
VDD1 = 4.5 to 5.5 V
18
VDD2 = 2.7 to 3.3 V
Port A = Port B = 3.3 V
VDD1 = 2.7 to 3.3 V
VDD2 = 2.7 to 3.3 V
Port A = Port B = 5 V
VDD1 = 4.5 to 5.5 V
12
VDD2 = 4.5 to 5.5 V
tPLZ
Propagation delay time, output
disable, DIRn to bus (low
impedance), CL =50 pF
Port A = 3.3 V,
Port B = 5 V
VDD1 = 4.5 to 5.5 V
20
VDD2 = 2.7 to 3.3 V
Port A = Port B = 3.3 V
VDD1 = 2.7 to 3.3 V
VDD2 = 2.7 to 3.3 V
Port A = Port B = 5 V
VDD1 = 4.5 to 5.5 V
15
VDD2 = 4.5 to 5.5 V
tPHZ
Propagation delay time, output
disable, DIRn to bus (high
impedance), CL =50 pF
Port A = 3.3 V,
Port B = 5 V
VDD1 = 4.5 to 5.5 V
20
VDD2 = 2.7 to 3.3 V
Port A = Port B = 3.3 V
VDD1 = 2.7 to 3.3 V
VDD2 = 2.7 to 3.3 V
Port A = Port B = 5 V
VDD1 = 4.5 to 5.5 V
15
VDD2 = 4.5 to 5.5 V
54AC164245
Radiations
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4 Radiations
Total dose (Mil1019 dose rate): all parameters are post-irradiation guaranteed by wafer-lot
acceptance (after dose, all guaranteed electrical parameters are tested on a sample of
units of each wafer lot).
All parameters provided in Table 6 and Table 7 apply to both pre- and post-irradiation. The
54AC164245 is a pure CMOS product. Irradiation is performed at high dose rates.
Heavy ions: the behavior of the product when submitted to heavy ions is guaranteed by
qualification and is not tested in production. Heavy-ion trials are performed on qualification
lots only.
Table 8: Radiations
Type
Features
Value
Unit
TID
Total ionizing dose, high-dose rate
(50 - 300 rad/sec) up to:
100
krad
Heavy ions
SEL immune (at 125 °C) up to:
110
MeV.cm²/mg
SEU immune up to:
64
Test circuit
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5 Test circuit
Figure 5: Test circuit
1. CL = 50 pF or equivalent (includes jig and probe capacitance), RT = ZOUT of pulse generator (typically 50 Ω),
VREF = 0.5 VDD. ISRC is set to -1.0 mA and ISNK is set to 1.0 mA for tPHL and tPLH measurements. Input signal
from pulse generator: VI = 0.0 V to VDD; f = 10 MHz; tr = 1.0 V/ns "0.3 V/ns; tf = 1.0 V/ns "0.3 V/ns; tr and tf
are measured from 0.1 VDD to 0.9 VDD and from 0.9 VDD to 0.1 VDD respectively.
Figure 6: Waveform 1: propagation delay
54AC164245
Test circuit
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Figure 7: Waveform 2: enable and disable times (port A = port B, 5 V operation)
Figure 8: Waveform 3: enable and disable times (port A = port B, 3.3 V operation)
Test circuit
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Figure 9: Waveform 4: enable and disable times (port A = 3.3 V, port B = 5 V)
54AC164245
Package information
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6 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Package information
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6.1 Ceramic Flat-48 package information
Figure 10: Ceramic Flat-48 package outline
1. The upper metallic lid is not electrically connected to any pins, nor to the IC die inside the package.
Connecting any unused pins or the metal lid to ground or to the power supply will not affect the electrical
characteristics.
Table 9: Ceramic Flat-48 mechanical data
Ref.
Dimensions
Millimeters
Inches
Min.
Typ.
Max.
Min.
Typ.
Max.
A
2.18
2.47
2.72
0.086
0.097
0.107
b
0.20
0.254
0.30
0.008
0.010
0.012
c
0.12
0.15
0.18
0.005
0.006
0.007
D
15.57
15.75
15.92
0.613
0.620
0.627
E
9.52
9.65
9.78
0.375
0.380
0.385
E2
6.22
6.35
6.48
0.245
0.250
0.255
E3
1.52
1.65
1.78
0.060
0.065
0.070
e
0.635
0.025
f
0.20
0.008
L
6.85
8.38
9.40
0.270
0.330
0.370
Q
0.66
0.79
0.92
0.026
0.031
0.036
S1
0.25
0.43
0.61
0.010
0.017
0.024
(N-2 places)
e
Pin 1 identifier
48
2524
S1
(4 places)
b
(N places)
D
A
Q
L E
E3E2E3
L
f
c
54AC164245
Ordering information
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7 Ordering information
Table 10: Order codes
Order code
Description
Temp. range
Package
Marking
Packing
RHRAC164245K1
Engineering
model
-55 °C to 125 °C
Flat-48
RHRAC164245K1
Conductive
strip pack
RHRAC164245K01V
QML-V flight
5962R9858008VYC
Other information
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8 Other information
8.1 Data code
The date code is structured as shown below:
EM xyywwz
QML-V yywwz
where:
8.2 Documentation
Table 11: Documentation provided for ESCC flight
Quality level
Documentation
Engineering model
—
QML-V flight
Certificate of conformance
QCI (1) (groups A, B, C, D, and E)
Screening electrical data
Precap report
PIND (2) test
SEM (3) inspection report
X-Ray report
Notes:
(1)QCI = quality conformance inspection
(2)PIND = particle impact noise detection
(3)SEM = scanning electron microscope
yx y ww z
Assembly location (EM only) 3:
Rennes (France)
Last two digits of year
Week digits
Lot index in the week
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Revision history
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9 Revision history
Table 12: Document revision history
Date
Revision
Changes
23-Sep-2011
1
Initial release.
06-Apr-2012
2
Added Pin 4 description to Table 3: "pin descriptions".
29-Aug-2013
3
Minor changes to layout
Features: removed “Bus hold”
Table 1: updated order codes, quality level, and EPPL data.
Table 10: "Order codes": updated order codes and description
data.
Added Section 8: "Other information"
28-Apr-2014
4
Table 11: "Documentation provided for ESCC flight": removed
documentation for engineering model (there is none).
Updated disclaimer
27-Jul-2015
5
Table 4: "Absolute maximum ratings": removed Rthja and
updated Rthjc information respectively.
14-Sep-2016
6
Table 1: updated "RHFAC164245K1" with
"RHRAC164245K1" and "RHFAC164245K01V" with
"RHRAC164245K01V".
Table 10: "Order codes": updated "RHFAC164245K1" with
"RHRAC164245K1".
12-Jan-2017
7
Updated Section 1.1: "Cold spare"
Updated Section 1.2: "Power-up"
Table 4: "Absolute maximum ratings": updated VDD1/VDD2
value and updated footnote 1.
Table 5: “Operating conditions”: added footnote 1
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