Winbond
Bus Termination Regulator
W83310DS/DG
W83310DS
Datasheet Revision History
Pages
Dates Version
Version
on Web Main Contents
1 May/03 0.5 N.A. All versions before 0.5 are only for internal use.
2 1 May/03 0.51 N.A. Typo corrected.
3 5 May/03 0.60 N.A. Electrical characteristics update.
4 5 Jul./03 0.61 N.A. Electrical characteristics update.
5 10,11
Feb./04
0.70 N.A. Package dimension outline and Thermal data.
6 11 Mar./04
0.71 N.A. Thermal data update.
7 All Sep./04
0.8 N.A. Add Pb-free part W83310DG.
8 1 May/05 0.9 N.A. Add DDR II support spec
Please note that all data and specifications are subject to change without notice. All the
trademarks of products and companies mentioned in this datasheet belong to their
respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems
where malfunction of these products can reasonably be expected to result in personal
injury. Winbond customers using or selling these products for use in such applications do
so at their own risk and agree to fully indemnify Winbond for any damages resulting from
such improper use or sales.
All Trademark and Brand name belong to their respective owners. Publication Release Date: 2005/May
Revision 0.9
1
W83310DS/DG
PRELIMINARY
1. General Description
The W83310DS/DG is a linear regulator provides a power achieves continuous
2.0Amp bi-directional sinking and driving capability for a high speed bus terminator
application. The chip simply implements a stable power supply which tracks half of
input power dynamically for bus terminator with a single chip; it’s also can be fixed
with the input of V
REF1
and V
REF2
pins following with setting of pin BOOT_SEL. The
W83310DS/DG is promoted with small footprint 8-SOP 150mil power package. With
W83310DS/DG design, a high integration, high performance, and cost-effective
solution is promoted.
2. Features
Regulates a bi-directional power with driving and sinking capability
Provides achieve continuous 2.0Amp driving and sinking current
Power MOSFET integrated
Low external component count
Low output voltage offset
VCNTL Operates with +3.3V & 2.5 V power
8-SOP 150mil small power package
Low cost and easy to use
3. Applications
DDR/DDRII Bus Termination Regulator
Active Termination Bus
Intel® Springdale GMCH-V
TT
Support
SSTL-2
SSTL-3
All Trademark and Brand name belong to their respective owners. Publication Release Date: 2005/May
Revision 0.9
2
W83310DS/DG
PRELIMINARY
4. Pin Configuration and Description
- W83310DS/DG
SYMBOL PIN FUNCTION
V
IN
1 Main power input pin.
GND 2 Power ground.
V
REF1
3
Internal reference voltage source 1.
Reference voltage on the pin will be referred
with the value of pin BOOT_SEL set high.
V
OUT
4 Voltage output pin.
BOOT_SEL 5 A signal for the chip reference voltage source
selection. The function is designed for Intel®
Springdale chipset GMCH_V
TT
application.
V
CNTL
6 Power for internal control logic use
ENABLE 7 Chip function enable pin. 1: Enable; 0: Disable
V
REF2
8
Internal reference voltage source 2.
Reference voltage of the pin will be referred with
the value of pin BOOT_SEL set low.
V
IN
GND
V
REF1
V
OUT
V
REF2
ENABLE
V
CNTL
BOOT_SEL
1
2
3
4
8
7
6
5
W83310DS/DG
All Trademark and Brand name belong to their respective owners. Publication Release Date: 2005/May
Revision 0.9
3
W83310DS/DG
PRELIMINARY
5. Application Circuit
- W83310DS/DG for DDR SDRAM Application
C2
10u
C1
1000u
R1
1K
VRAM
U1
W83310DS
1
2
3
4
5
6
7
8
VIN
GND
VREF1
VOUT
BOOTSEL
VCTRL
ENABLE
VREF2
2.5VREF
C5
0.1U
R2
1K
C4
1500u
ENABLE
3VDUAL
DDRVTT
(0:DISABLE
1:ENABLE)
C3
1u
- W83310DS/DG for Intel® Springdale GMCH_VTT Application
C1
1000u
CPU_VTT
R2
R
C2
10u
BOOTSELECT
C3
1u
GMCHVTT
R1
R
BOOTSELECT=1 GMCHVTT=1.225V for Intel® PRESCOTT CPU
BOOTSELECT=0 GMCHVTT=1.45V for Intel® NORTHWOOD CPU
R3
R
GMCH_VTT
C4
1500u
2.5VREF
PWOK
VCC2.5
C5
0.1U
U1
W83310DS
/DG
1
2
3
4 5
6
7
8
VIN
GND
VREF1
VOUT BOOTSEL
VCTRL
ENABLE
VREF2
R1: R2: R3 = 4.66: 1.00: 5.44
!
Ω
"
#$ %%!
Ω
"
&'#!
Ω
VCC3
All Trademark and Brand name belong to their respective owners. Publication Release Date: 2005/May
Revision 0.9
4
W83310DS/DG
PRELIMINARY
- Dual Layout of W83310DS/DG and W83310S-R2 for DDR V
TT
Application
U1
W83310DS/DG
1
2
3
4
5
6
7
8
VIN
GND
VREF1
VOUT
BOOTSEL
VCTRL
ENABLE
VREF2
C3
1u
C4
1500u
C1
1000u
W83310S-R2, W83310DS/DG
DUAL LAYOUT
3VDUAL
R2
10K
R1
10K
C5
100U
VRAM
DDRVTT
2.5VREF
C2
1u
6. Internal Block Diagram
V
CTRL
V
IN
ENABLE
V
REF2
V
REF1
BOOT_SEL
GND
V
OUT
Control
Logic
Control
Logic
Circuit
All Trademark and Brand name belong to their respective owners. Publication Release Date: 2005/May
Revision 0.9
5
W83310DS/DG
PRELIMINARY
7. Electrical Characteristics
AC CHARACTERISTICS
Cout=1000uF, T
A
= 0
°
°°
°
C to +70
°
°°
°
C
Parameter Symbol Min Typ Max
Units Test Conditions
Output Offset Voltage Vos -5 0 +5 mV Iout=0A
0.8 Loading: 0A2.0A
Load Regulation
0.8 % Loading: 0A-2.0A
VIN 1.62
3.63
Input Voltage Range VCNTL 3.3 3.63
V
Operating Current of VCNTL
ICNTL 0.5 1 mA No Load(Iout=0A)
Short Current Limit ILMT 4.0 A
Note: Load regulation is tested by using a 1ms current pulse and V
OUT
measuring.
Cout=1000uF, T
A
= 0
°
°°
°
C to +70
°
°°
°
C
Parameter Symbol
Min Typ Max
Units Test Conditions
Output Offset Voltage Vos -5 0 +5 mV Iout=0A
0.8 Loading: 0A2.0A
Load Regulation
0.8 % Loading: 0A-2.0A
VIN 1.62
3.63
Input Voltage Range VCNTL
3.3 3.63
V
Operating Current of VCNTL ICNTL 0.5 1 mA No Load(Iout=0A)
0.8 V Output=High
VREF1 Threshold trigger
0.2 V Output=Low
1 V BOOT_SEL=High
BOOT_SEL Threshold Trigger
0.2 V BOOT_SEL=Low
Short Current Limit ILMT 4.0 A
Note: Load regulation is tested by using a 1ms current pulse and V
OUT
measuring.
Cout=1000uF, T
A
= 0
°
°°
°
C to +70
°
°°
°
C
Parameter Symbol
Min Typ Max
Units Test Conditions
Output Offset Voltage Vos -5 0 +5 mV Iout=0A
0.8 Loading: 0A2.0A
Load Regulation
0.8 % Loading: 0A-2.0A
VIN 1.62
3.63
Input Voltage Range VCNTL
3.3 3.63
V
Operating Current of VCNTL ICNTL 0.5 1 mA No Load(Iout=0A)
0.8 V Output=High
VREF2 Threshold trigger
0.2 V Output=Low
1 V BOOT_SEL=High
BOOT_SEL Threshold Trigger
0.2 V BOOT_SEL=Low
Short Current Limit ILMT 4.0 A
Note: Load regulation is tested by using a 1ms current pulse and V
OUT
measuring.
All Trademark and Brand name belong to their respective owners. Publication Release Date: 2005/May
Revision 0.9
6
W83310DS/DG
PRELIMINARY
8. Typical Operating Waveform
Load regulation with test condition - V
CTRL
=3.3V; V
IN
=2.5V; V
OUT
=1.225V; 2.0Amp
pulse driving current.
Load regulation with test condition - V
CTRL
=3.3V; V
IN
=2.5V; V
OUT
=1.225V; 2.0Amp
pulse sinking current.
All Trademark and Brand name belong to their respective owners. Publication Release Date: 2005/May
Revision 0.9
7
W83310DS/DG
PRELIMINARY
Load regulation with test condition - V
CTRL
=3.3V; V
IN
=2.5V; V
OUT
=1.45V; 2.0Amp
pulse driving current.
Load regulation with test condition - V
CTRL
=3.3V; V
IN
=2.5V; V
OUT
=1.45V; 2.0Amp
pulse sinking current.
All Trademark and Brand name belong to their respective owners. Publication Release Date: 2005/May
Revision 0.9
8
W83310DS/DG
PRELIMINARY
Load regulation with test condition - V
CTRL
=3.3V; V
IN
=2.5V; V
OUT
=1.25V; 2.0Amp
pulse driving current.
Load regulation with test condition - V
CTRL
=3.3V; V
IN
=2.5V; V
OUT
=1.25V; 2.0Amp
pulse sinking current.
All Trademark and Brand name belong to their respective owners. Publication Release Date: 2005/May
Revision 0.9
9
W83310DS/DG
PRELIMINARY
Short Current Limit
- V
CTRL
= 3.3V
- V
CTRL
= 3.6V
All Trademark and Brand name belong to their respective owners. Publication Release Date: 2005/May
Revision 0.90
10
W83310DS
PRELIMINARY
9. Package Dimension
8L Power SOP 150mil
All Trademark and Brand name belong to their respective owners. Publication Release Date: 2005/May
Revision 0.90
11
W83310DS/DG
PRELIMINARY
10. Thermal Performance
Test on Four-Layer (2S2P) JEDEC Test Board
Component Temp. (
o
C)
Package Power (W)
Package Die
Downset Lead Ambient
jc
(
o
C /W)
PSOP-8 3.05 100 145
79 78 25 14.7
An area of 190mil*150mil on the top layer is use as a thermal pad for W83310DS and this is con-
nected to the bottom layer by vias. The ja of the W83310DS mounted on this demo board is ab-
out 39
o
C /W.Assuming the T
A
=25
o
C and T
J
=160
o
C,the maximum power dissipation is calculated
as: P
D(max)
=(160-25)/39=3.46W
11. Ordering Information
Part Number Package Type Production Flow
W83310DS
Power SOP-8
12. How to Read the Top Marking
Left line: Winbond logo
1
st
& 2
nd
line: W83310DS/DG – the part number
3rd line: Tracking code 318 G A
318
: packages assembled in Year 03’, week 18
G
: assembly house ID; O means OSE, G means GR, etc.
A
: the IC version
W83
310DS
249GA
W83
310DG
249GA
All Trademark and Brand name belong to their respective owners. Publication Release Date: 2005/May
Revision 0.90
12
W83310DS/DG
PRELIMINARY
Headquarters
No. 4, Creation Rd. III
Science
-
Based Industrial Park
Hsinchu, Taiwan
TEL: 886
-
35
-
770066
FAX: 886
-
35
-
789467
www: http://www.winbond.com.tw/
Taipei Office
9F, No. 480, Rueiguang Road, Neihu District,
Taipei, 114, Taiwa
n
TEL:
886
-
2
-
81777168
FAX: 886-2-87153579
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II
123 Hoi Bun Rd., Kwun Tong
Kowloon, Hong Kong
TEL: 852-27516023-7
FAX: 852-27552064
Winbond Electronics
(North America) Corp.
2727 North First Street
San Jose, California 95134
TEL: 1-408-9436666
FAX: 1-408-9436668
Please note that all data and specifications are subject to change without notice. All the trade
marks of products and companies mentioned in this data sheet belong to their respective owners.
These products are not designed for use in life support appliances, devices, or systems where
malfunction of these products can reasonably be expected to result in personal injury. Winbond
customers using or selling these products for use in such applications do so at their own risk and
agree to fully indemnify Winbond for any damages resulting from such improper use or sale.
