BTS4130QGA
Smart High-Side Power Switch
Data Sheet, Rev. 1.0, March 2008
Automotive Power
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Datasheet 2 1.0, 2008-27-02
BTS 4130QGA
1Overview 3
2Block Diagram 5
3 Pin Configuration 6
3.1 Pin Assignment 6
3.2 Pin Definitions and Functions 6
3.3 Voltage and Current Definition 7
4 General Product Characteristics 8
4.1 Absolute Maximum Ratings 8
4.2 Functional Range 9
4.3 Thermal Resistance 9
5 Power Stage 10
5.1 Output ON-State Resistance 10
5.2 Turn ON / OFF Characteristics 10
5.3 Inductive Output Clamp 11
5.3.1 Maximum Load Inductance 12
5.4 Electrical Characteristics Power Stage 13
6 Protection Mechanisms 14
6.1 Loss of Ground Protection 14
6.2 Undervoltage Protection 14
6.3 Overvoltage Protection 14
6.4 Reverse Polarity Protection 15
6.5 Overload Protection 15
6.5.1 Current Limitation 16
6.6 Electrical Characteristics Protection Functions 17
7 Diagnostic Mechanism 18
7.1 ST 0/1/2/3 Pin 18
7.2 ST0/1/2/3 Signal in Case of Failures 18
7.2.1 Diagnostic in Open Load, Channel OFF 19
7.2.2 ST 0/1 Signal in case of Over Temperature 20
7.3 Electrical Characteristics Diagnostic Functions 21
8 Input Pins 22
8.1 Input Circuitry 22
8.2 Electrical Characteristics 22
9 Application Information 23
9.1 Further Application Information 23
10 Package Outlines 24
11 Revision History 25
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PG-DSO-20-32
Type Package Marking
BTS4130QGA PG-DSO-20-32 BTS4130QGA
Data Sheet 3 Rev. 1.0, 2008-03-18
Smart High-Side Power Switch
Four Channel Device
BTS4130QGA
1 Overview
Basic Features
• Withstand low Cranking Voltage
• Fit for 12V Application
• Four Channel device
• Very low Stand-by Current
• CMOS Compatible Inputs
• Electrostatic Discharge Protection (ESD)
• Optimized Electromagnetic Compatibility
• Logic ground independent from load ground
• Very low Leakage Current from OUT to the load in OFF State
• Green Product (RoHS compliant)
•AEC Qualified
Description
The BTS4130QGA is a quad channel Smart High-Side Power Switch. It is embedded in a PG-DSO-20-32
package, providing protective functions and diagnostics. The power transistor is built by a N-channel power
MOSFET with charge pump. The device is monolithically integrated in Smart technology. It is specially designed
to drive relays as well as resistive loads in the harsh automotive environment.
Table 1 Electrical Parameters (short form)
Parameter Symbol Value
Operating voltage range VSOP 5.5V .... 20V
Undervoltage switch OFF at Tj = -40°C Vs (USO) 3.2V
Maximum load per channel PBULB 2 * R5W, relays or LED
Over voltage protection VS (AZ) 43V
Max ON State resistance at Tj = 150°C per channel RDS(ON) 260mΩ
Nominal load current (one channel active) IL (nom) 1.8A
Minimum current limitation IL_SCR 5A
Standby current for the whole device with load IS(off) 16µA
Maximum reverse battery voltage -Vs(REV) 32V
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Data Sheet 4 Rev. 1.0, 2008-03-18
BTS4130QGA
Overview
Diagnostic Feature
• Open load detection in OFF state
• Feedback of the thermal shutdown in ON state
• Diagnostic feedback with open drain output
Protection Functions
• Short circuit protection
• Overload protection
• Current limitation
• Thermal shutdown
• Overvoltage protection (including load dump) with external resistor
• Reverse battery protection with external resistor
• Loss of ground and loss of VS protection
• Electrostatic discharge protection (ESD)
Application
• All types of resistiv, inductive and capacitive loads
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Data Sheet 5 Rev. 1.0, 2008-03-18
BTS4130QGA
Block Diagram
2 Block Diagram
Figure 1 Block diagram for the BTS4130QGA
Block diagram . emf
Channel 0 V
S
OUT 0
IN0
T
driver
logic
gate control
&
charge pump
open load detection
over
temperature clamp for
inductive load
over current
switch off
voltage sensor
ESD
protection
ST 0/1
internal
power
supply
Channel 1
IN1
Control and protection circuit equivalent to channel 0
T
V
S
OUT 1
Channel 2 V
S
OUT 2
IN2
T
driver
logic
gate control
&
charge pump
open load detection
over
temperature clamp for
inductive load
over current
switch off
voltage sensor
GND
ESD
protection
ST 2/3
internal
power
supply
Channel 3
IN3
Control and protection circuit equivalent to channel 0
T
V
S
OUT 3
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Data Sheet 6 Rev. 1.0, 2008-03-18
BTS4130QGA
Pin Configuration
3 Pin Configuration
3.1 Pin Assignment
Figure 2 Pin Configuration
3.2 Pin Definitions and Functions
Pin Symbol Function
1, 10, 11,
12, 15, 16,
19, 20
VSBattery voltage; Design the wiring for the simultaneous maximum short circuit
currents from channel 0 and 1 and also for low thermal resistance
2GND0/1 Ground; Ground connection for channel 0 and 1
3 IN0 Input channel 0; Input signal for channel 0. Activate the channel in case of logic
high level
4ST 0/1 Diagnostic feedback; of channel 0/1. Open drain.
5 IN1 Input channel 1; Input signal for channel 1. Activate the channel in case of logic
high level
6GND2/3 Ground; Ground connection for channel 2 and 3
7 IN2 Input channel 2; Input signal for channel 2. Activate the channel in case of logic
high level
8ST 2/3 Diagnostic feedback; of channel 2/3. Open drain.
9 IN3 Input channel 3; Input signal for channel 3. Activate the channel in case of logic
high level
1
2
3
4
14
13
12
11
ST 0/1
GND0/1
IN0
Vs
5
6
7
IN1
17
16
15
OUT0
OUT1
Vs
GND2/3
Pinout SO20 shared diag.vsd
10
9
8
20
19
18
Vs Vs
Vs
OUT3
OUT2
Vs
Vs
Vs
IN2
ST2/3
IN3
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Data Sheet 7 Rev. 1.0, 2008-03-18
BTS4130QGA
Pin Configuration
3.3 Voltage and Current Definition
Figure 3 shows all terms used in this data sheet, with associated convention for positive values.
Figure 3 Voltage and current definition
13 OUT3 Output 3; Protected High side power output channel 3
14 OUT2 Output 2; Protected High side power output channel 2
17 OUT1 Output 1; Protected High side power output channel 1
18 OUT0 Output 0; Protected High side power output channel 0
Pin Symbol Function
V
S
IN0
IN1
ST 0/ 1
GND
OUT0
OUT1
I
IN0
I
IN1
I
ST0 /1
V
S
V
IN0
V
IN1
V
ST0 /1
I
S
I
GND
V
DS0
V
DS1
V
OUT0
V
OUT1
Voltage and current convention quad
shared diag.vsd
IN2
IN3
ST 2/ 3
I
IN2
I
IN3
I
ST2 /3
OUT2
OUT3
V
OUT3
V
DS2
V
DS3
V
OUT2
I
OUT3
I
OUT0
I
OUT1
I
OUT2
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Data Sheet 8 Rev. 1.0, 2008-03-18
BTS4130QGA
General Product Characteristics
4 General Product Characteristics
4.1 Absolute Maximum Ratings
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings 1)
TJ = 25°C; (unless otherwise specified)
1) Not subject to production test, specified by design
Pos. Parameter Symbol Limit values Unit Conditions
Min. Max.
Voltages
4.1.1 Supply voltage VS-0.3 43 V –
4.1.2 Reverse polarity Voltage - VS(REV) –32 V –
4.1.3 Supply voltage for short circuit protection Vbat(SC) 020 VRECU = 20mΩ,
RCable = 16mΩ/m,
LCable = 1µH/m,
l = 0 or 5m 2)
see Chapter 6
2) Set up in accordance to AEC Q100-012 and AEC Q101-006
Input pins
4.1.4 Voltage at INPUT pins VIN -10 16 V –
4.1.5 Current through INPUT pins IIN -0.3 0.3 mA –
4.1.6 Current through INPUT pins pulsed IIN -5 5mA Only for testing
Status pin
4.1.7 Current through ST 0/1 pin IST0/1 -5 5mA –
4.1.8 Current through ST 2/3 pin IST2/3 -5 5mA –
Power stage
4.1.9 Load current | IL | – IL(LIM) A –
4.1.10 Power dissipation (DC), all channel
active
PTOT –1.4 WTA = 85°C,
Tj <150°C
4.1.11 Maximum Switchable energy, single
pulse
EAS –76 mJ IL = 2.3A,
VS = 12V
Temperatures
4.1.12 Junction Temperature Tj-40 150 °C –
4.1.13 Dynamic temperature increase while
switching
∆Tj–60 K –
4.1.14 Storage Temperature Tstg -55 150 °C –
ESD Susceptibility
4.1.15 ESD Resistivity IN pin VESD -1 1kV HBM3)
3) ESD susceptibility HBM according to EIA/JESD 22-A 114B
4.1.16 ESD Resistivity ST 0/1, 2/3 pins VESD -4 4kV HBM3)
4.1.17 ESD Resistivity OUT to all other pins
shorted
VESD -5 5kV HBM3)
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Data Sheet 9 Rev. 1.0, 2008-03-18
BTS4130QGA
General Product Characteristics
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
4.2 Functional Range
Tj = -40 °C to +150 °C; (unless otherwise specified)
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3 Thermal Resistance
Pos. Parameter Symbol Limit values Unit Conditions
Min. Max.
4.2.1 Operating Voltage VSOP 5.5 20 VVIN = 4.5V,
RL = 12Ω,
VDS < 0.5V
4.2.2 Undervoltage switch OFF VSUV –3.2 V -1),
Tj = -40°C,
VDS < 0.5V
1) Battery voltage is decreasing
4.2.3 Operating current
One channel active
Four channels active
IGND
–
–
0.9
3.3
mA VIN = 5V
4.2.4 Standby current for whole device
with load
IS(OFF) –
–
–
16
16
24
µA Tj = 25°C
Tj = 85°C2)
Tj = 150°C,
Vs = 12V,
RL = 12Ω,
VIN = 0V
2) Not subject to production test. Specified by design
Pos. Parameter Symbol Limit values Unit Conditions
Min. Typ. Max.
4.3.1 Junction to Soldering Point each
channel
RthJSP ––15 K/W –1)
1) Not subject to production test, specified by design
4.3.2 Junction to Ambient RthJA –45 –K/W with 6cm² cooling
area1)
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Data Sheet 10 Rev. 1.0, 2008-03-18
BTS4130QGA
Power Stage
5 Power Stage
The power stages are built by an N-channel vertical power MOSFET (DMOS) with charge pump.
5.1 Output ON-State Resistance
The ON-state resistance RDS(ON) depends on the supply voltage as well as the junction temperature Tj. Figure 4
shows the dependencies for the typical ON-state resistance. The behavior in reverse polarity is described in
Chapter 6.4.
Figure 4 Typical ON-state resistance
A high signal (See Chapter 8) at the input pin causes the power DMOS to switch ON with a dedicated slope, which
is optimized in terms of EMC emission.
5.2 Turn ON / OFF Characteristics
Figure 5 shows the typical timing when switching a resistive load.
Figure 5 Turn ON/OFF (resistive) timing
0
50
100
150
200
250
300
5 7 9 11 13 15 17 19
VS (V)
Rdson ( mOhm)
Rdson (mOhm) @ -40°C
Rdson (mOhm) @ +25°C
Rdson (mOhm) @ +150°C
ron.vsd
IN
t
V
OUT
t
ON
t
OFF
90% V
S
10% V
S
V
IN_H_min
V
IN_L_max
t
Switching times.vs
d
30% V
S
70% V
S
dV/dt
ON
dV/dt
OFF
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Data Sheet 11 Rev. 1.0, 2008-03-18
BTS4130QGA
Power Stage
5.3 Inductive Output Clamp
When switching OFF inductive loads with high side switches, the voltage VOUT drops below ground potential,
because the inductance intends to continue driving the current. To prevent the destruction of the device due to
high voltages, there is a voltage clamp mechanism implemented that keeps the negative output voltage at a certain
level (VS-VDS(AZ)). Please refers to Figure 6 and Figure 7 for details. Nevertheless, the maximum allowed load
inductance is limited.
Figure 6 Output clamp (OUT0 and OUT1)
Figure 7 Switching an inductance
VBAT
VOUT
IL
L, RL
V
S
OUT
VDS
LOGIC
IN
VIN
Output clamp.vsd
GND
IN
V
OUT
I
L
V
S
V
S-
V
DS(AZ)
t
t
t
Switching an inductance.vs
d
t
peak
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Data Sheet 12 Rev. 1.0, 2008-03-18
BTS4130QGA
Power Stage
5.3.1 Maximum Load Inductance
During demagnetization of inductive loads, energy has to be dissipated in the BTS4130QGA. This energy can be
calculated with following equation:
Following equation simplifies under the assumption of RL = 0Ω.
The energy, which is converted into heat, is limited by the thermal design of the component. See Figure 8 for the
maximum allowed inductivity.
Figure 8 Maximum energy dissipation single pulse, Tj,Start = 150 °C
EV
DS AZ()L
RL
-------
×VSVDS AZ()
–
RL
---------------------------------- 1
RLIL
×
VSVDS AZ()
–
----------------------------------–
ln IL
+××=
E1
2
---LI
21
VS
VSVDS AZ()
–
----------------------------------–
×××=
max eas.vsd
1
10
100
1000
123456
IL (A)
ZL (mH)
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Data Sheet 13 Rev. 1.0, 2008-03-18
BTS4130QGA
Power Stage
5.4 Electrical Characteristics Power Stage
Electrical Characteristics: Power stage
VS = 12 V, Tj = -40 °C to +150 °C. Typical values are given at Tj = 25°C
Pos. Parameter Symbol Limit values Unit Conditions
Min. Typ. Max.
5.4.1 ON-state resistance per channel RDS(ON) –130 – mΩTj = 25°C,1)
IL = 2A,
VIN = 5V,
See Figure 4
1) Not subject to production test, specified by design
–210 260 Tj = 150°C
5.4.2 Nominal load current per channel
One channel active
Two channel active
Four channel active
IL(nom)
2.1
1.5
1.1
–
–
–
–
–
–
ATA = 85°C1),
Tj <150°C
5.4.3 Drain to source clamping voltage
VDS(AZ) = VS-VOUT
VDS(AZ) 41 47 52 VIDS = 40mA2)
2) Voltage is measured by forcing IDS.
5.4.4 Output leakage current per channel IL(OFF) –15µA VIN = 0V
5.4.5 Slew rate ON
10% to 30% VOUT
dV/dtON 0.2 –1V/µs RL=12Ω,
VS=12V
See Figure 5
5.4.6 Slew rate OFF
70% to 40% VOUT
-dV/dtOFF 0.2 –1.1 V/µs
5.4.7 Turn-ON time to 90% VS
Includes propagation delay
tON –100 250 µs
5.4.8 Turn-OFF time to 10% VS
Includes propagation delay
tOFF –100 270 µs
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Data Sheet 14 Rev. 1.0, 2008-03-18
BTS4130QGA
Protection Mechanisms
6 Protection Mechanisms
The device provides embedded protective functions. Integrated protection functions are designed to prevent the
destruction of the IC from fault conditions described in the data sheet. Fault conditions are considered as “outside”
normal operating range. Protection functions are designed for neither continuous nor repetitive operation.
6.1 Loss of Ground Protection
In case of loss of the module ground, where the load remains connected to ground, the device protects itself by
automatically turning OFF (when it was previously ON) or remains OFF, regardless of the voltage applied on IN
pins. In that case, a maximum I(OUTGND) can flow out of the output.
6.2 Undervoltage Protection
Below VSUV_max, the under voltage mechanism is met. If the supply voltage is below the under voltage mechanism,
the device is OFF (turns OFF). As soon as the supply voltage is above the under voltage mechanism, then the
device can be switched ON and the protection functions are operational.
6.3 Overvoltage Protection
There is a clamp mechanism for over voltage protection. To guarantee this mechanism operates properly in the
application, the current in the zener diode ZDAZ has to be limited by a ground resistor. Figure 9 shows a typical
application to withstand overvoltage issues. In case of supply greater than VS(AZ), the power transistor switches
ON and the voltage across logic section is clamped. As a result, the internal ground potential rises to VS - VS(AZ).
Due to the ESD zener diodes, the potential at pins IN and ST 0/1/2/3 rises almost to that potential, depending on
the impedance of the connected circuitry. Integrated resistors are provided at the IN pins to protect the input
circuitry from excessive current flow during this condition but an external resistor must be provided at the ST0/1/2/3
pins.
Figure 9 Over voltage protection with external components
IN1
R
IN0
IN0
R
IN1
ZD
ESD
GND
OUT
V
S
V
BAT
R
GND
ZD
AZ
Overvoltage protection quad diag
shared.vsd
V
ccµ C
R
L
R
ST 0/1
ST 0/1
R
PU_ST 0/1
IN3
R
IN2
IN2
R
IN3
ZD
ESD
V
ccµC
R
ST 2/3
ST 2/3
R
PU_ST 3
LOGIC
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Data Sheet 15 Rev. 1.0, 2008-03-18
BTS4130QGA
Protection Mechanisms
In the case the supply voltage is in between of VS(SC) max and VDS(AZ), the output transistor is still operational and
follow the input. If at least one channel is in ON state, parameters are no longer warranted and lifetime is reduced
compared to normal mode. This specially impacts the short circuit robustness, as well as the maximum energy
EAS the device can handle.
6.4 Reverse Polarity Protection
In case of reverse polarity, the intrinsic body diode causes power dissipation. The current in this intrinsic body
diode is limited by the load itself. Additionally, the current into the ground path and the logical pins has to be limited
to the maximum current described in Chapter 4.1, sometimes with an external resistor. Figure 10 shows a typical
application. The RGND resistor is used to limit the current in the zener protection of the device. Resistors RIN and
RST are used to limit the current in the logic of the device and in the ESD protection stage. The recommended value
for RGND is 150Ω, for RST 0/1 = 15kΩ. In case the over voltage is not considered in the application, RGND can be
replaced by a Shottky diode.
Figure 10 Reverse polarity protection with external components
6.5 Overload Protection
In case of overload, or short circuit to ground, the BTS4130QGA offers several protections mechanisms.
Micro controller
protection diodes
GND
OUT0, 1, 2, 3
IN1
V
S
V
BAT
R
IN0
IN0
ST 0/1
R
IN 1
R
ST /1
R
GND
ZD
body
Rever se Polarity quad shar ed
diag .vs d
-V
DS(REV)
I
L(nom)
R
L
R
PU ST 0/1
VccµC
ZD
ESD
IN1
R
IN0
IN0
ST 2/3
R
IN 1
R
ST 2/3
R
PU ST 2/3
VccµC
ZD
ESD
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Data Sheet 16 Rev. 1.0, 2008-03-18
BTS4130QGA
Protection Mechanisms
6.5.1 Current Limitation
At first step, the instantaneous power in the switch is maintained to a safe level by limiting the current to the
maximum current allowed in the switch IL(LIM). During this time, the DMOS temperature is increasing, which affects
the current flowing in the DMOS. At thermal shutdown, the device turns OFF and cools down. A restart mechanism
is used, after cooling down, the device restarts and limits the current to IL(SCR). Figure 11 shows the behavior of
the current limitation as a function of time.
Figure 11 Current limitation function of the time
t
I
L
I
L(LIM)
I
L(SCr)
current limitation with diag shared.vs
d
t
IN
ST 0/1
t
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Data Sheet 17 Rev. 1.0, 2008-03-18
BTS4130QGA
Protection Mechanisms
6.6 Electrical Characteristics Protection Functions
Electrical Characteristics: Protection
VS = 12 V, Tj = -40 °C to +150 °C. Typical values are given at Tj = 25°C
Pos. Parameter Symbol Limit values Unit Conditions
Min. Typ. Max.
Loss of ground
6.6.1 Output leakage current while GND
disconnected
IOUT(GND) ––2mA VS = 32V
VIN = 0V
Reverse polarity
6.6.2 Drain source diode voltage during
reverse polarity
-VDS(REV) –600 –mV IL= - 2A,
Tj = 150°C
VIN = 0V
Overvoltage
6.6.3 Over voltage protection VS(AZ) 41 47 52 VIs = 40mA
Overload condition
6.6.4 Load current limitation IL(LIM) –
–
5
–
9
–
14
–
–
ATj = -40°C,
Tj = 25°C,
Tj = 150°C
6.6.5 Repetitive short circuit current limit IL(SCR) –
–
6.5
6.5
–
–
AOne channel1)
Two channel1)
parallel
6.6.6 Thermal shutdown temperature TjSC 150 – – °C –
6.6.7 Thermal shutdown hysteresis ∆TJT –10 – K – 1)
1) Not subject to production test, but specified by design
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Data Sheet 18 Rev. 1.0, 2008-03-18
BTS4130QGA
Diagnostic Mechanism
7 Diagnostic Mechanism
For diagnosis purpose, the BTS4130QGA provides status pin.
7.1 ST 0/1/2/3 Pin
BTS4130QGA status pins are an open drain, active low circuit. Figure 12 shows the equivalent circuitry. As long
as no “hard” failure mode occurs (Short circuit to GND / Over temperature or open load in OFF), the signal is
permanently high, and due to a required external pull-up to the logic voltage will exhibit a logic high in the
application. A suggested value for the RPU ST01 is 15 kΩ.
.
Figure 12 Status output circuitry
7.2 ST0/1/2/3 Signal in Case of Failures
Table 2 gives a quick reference for the logical state of the ST 0/1/2/3 pins during device operation.
Table 2 ST 0/1 2/3 truth table
Device operation IN0/2 IN1/3 OUT0/2 OUT1/3 ST 0/1
ST2/3
Normal operation LLLLH
L H L H
H L H L
HHHH
Open Load channel 0/2 L X > V(OL) X L1)
1) L if potential at the output exceeds the Openload detection voltage
H X H X H
Open Load channel 1/3 XLX> V(OL) L1)
X H X H H
Over temperature both channel LLLLH
X H X L L
H X L X L
Over temp channel 0/2 L X L X H
H X L X L
Over temp channel 1/3 X L X L H
X H X L L
ST pin quad shared
diag.v sd
GND
ST 0/1
or
ST 2/3
R
ST 0/1
R
ST 2/3
ZD
ESD
R
PU ST 0/1
R
PU ST 2/3
V
ccµC
OR
Channel 0 or 2
Diagnostic
Logic
Channel 1 or 3
Diagnostic
Logic
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Data Sheet 19 Rev. 1.0, 2008-03-18
BTS4130QGA
Diagnostic Mechanism
7.2.1 Diagnostic in Open Load, Channel OFF
For open load diagnosis in OFF-state, an external output pull-up resistor (ROL) is recommended. For calculation
of the pull-up resistor value, the leakage currents and the open load threshold voltage VOL(OFF) has to be taken into
account. Figure 13 gives a sketch of the situation and Figure 14 shows the typical timing diagram.
Ileakage defines the leakage current in the complete system, including IL(OFF) (see Chapter 5.4) and external
leakages e.g. due to humidity, corrosion, etc... in the application.
To reduce the stand-by current of the system, an open load resistor switch SOL is recommended.
If the channel is OFF, the output is no longer pulled down by the load and VOUT voltage rises to nearly VS. This is
recognized by the device as open load. The voltage threshold is given by VOL(OFF). In that case, the ST 0/1 signal
is switched to a logical low VST01(L).
Figure 13 Open load detection in OFF electrical equivalent circuit
Figure 14 ST 0/1 in open load condition
OUT
V
S
R
leakage
R
OL
S
OL
V
bat
V
OL(OFF)
I
leak age
I
LOFF
OL
comp.
Open Load in OFF.vsd
GND
R
GND
IN
V
OUT
ST 0/1 or ST 2/3
I
L
Diagnostic In Open load quad shared diag.vs
d
t
t
t
t
V
ST(HIGH)
V
(OL)
V
ST(LOW)
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Data Sheet 20 Rev. 1.0, 2008-03-18
BTS4130QGA
Diagnostic Mechanism
7.2.2 ST 0/1 Signal in case of Over Temperature
In case of over temperature, the junction temperature reaches the thermal shutdown temperature TjSC.
In that case, the ST 0/1 signal is toggling between VST01(L) and VST01(H). Figure 15 gives a sketch of the situation.
Figure 15 Sense signal in overtemperature condition
.
IN
V
OUT
ST 0/1
T
J
Diagnostic In Overload shared toggling.vs
d
t
t
t
t
T
JSC
∆T
JSC
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Data Sheet 21 Rev. 1.0, 2008-03-18
BTS4130QGA
Diagnostic Mechanism
7.3 Electrical Characteristics Diagnostic Functions
Electrical Characteristics: Diagnostics
VS = 12 V, Tj = -40 °C to +150 °C. Typical values are given at Tj = 25°C
Pos. Parameter Symbol Limit values Unit Conditions
Min. Typ. Max.
Load condition threshold for diagnostic
7.3.1 Open Load detection voltage VOL(OFF) 1.7 2.8 4.0 V –
ST 0/1 or ST 2/3 pin
7.3.2 Status output (open drain)
High level; Zener limit voltage
VST (HIGH) 5.4 ––VIST= +1.6mA1),
Zener Limit voltage
7.3.3 Status output (open drain)
Low level
VST (LOW) ––0.6 VIST= +1.6mA1)
1) If ground resistor RGND is used, the voltage drop across this resistor has to be added
Diagnostic timing
7.3.4 Status change after positive
input slope with open load
tdST(ON_OL) –10 20 µs –2)
2) Not subject to production test, specified by design
7.3.5 Status change after positive
input slope with overload
tdST(ON_OvL) 30 ––µs –2)
7.3.6 Status change after negative
input slope with open load
tdST(OFF_OL) ––500 µs –
7.3.7 Status change after negative
input slope with overtemperature
tdST(OFF) ––20 µs –2)
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Data Sheet 22 Rev. 1.0, 2008-03-18
BTS4130QGA
Input Pins
8 Input Pins
8.1 Input Circuitry
The input circuitry is CMOS compatible. The concept of the Input pin is to react to voltage transition and not to
voltage threshold. With the Schmidt trigger, it is impossible to have the device in an un-defined state, if the voltage
on the input pin is slowly increasing or decreasing. The output is either OFF or ON but cannot be in an linear or
undefined state. The input circuitry is compatible with PWM applications. Figure 16 shows the electrical equivalent
input circuitry. The pull down current source ensures the channel is OFF with a floating input.
Figure 16 Input pin circuitry
8.2 Electrical Characteristics
Electrical Characteristics: Diagnostics
VS = 12 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified) Typical values are given at Tj = 25°C
Pos. Parameter Symbol Limit values Unit Conditions
Min. Typ. Max.
INput pins characteristics
8.2.1 Low level input voltage VIN(L) ––1V–1)
1) If ground resistor RGND is used, the voltage drop across this resistor has to be added
8.2.2 High level input voltage VIN(H) 2.5 – – V –1)
8.2.3 Input voltage hysteresis VIN(HYS) –0.2 – V –2)
2) Not subject to production test, specified by design
8.2.4 Low level input current IIN(L) 5–20 µA VIN = 0.4V
8.2.5 High level input current IIN(H) 10 35 60 µA VIN = 5V
8.2.6 Input resistance RI2.5 46kΩSee Figure 16
IN
ESD
To driver’s logic
Input circuitry.vsd
R
I
I
I
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Data Sheet 23 Rev. 1.0, 2008-03-18
BTS4130QGA
Application Information
9 Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
Figure 17 Application diagram with BTS4130QGA
Note: This is a very simplified example of an application circuit. The function must be verified in the real application.
9.1 Further Application Information
• For further information you may visit http://www.infineon.com/
OUT
OUT
IN
GND
Vdd
Microcontroller
(e.g. XC22xx)
IN0
IN1
ST0/1
GND
OUT0
OUT1
V
s
V
BAT
V
DD
V
DD
OUT
OUT
IN
IN2
IN3
ST2/3
OUT2
OUT3
V
DD
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Data Sheet 24 Rev. 1.0, 2008-03-18
BTS4130QGA
Package Outlines
10 Package Outlines
Figure 18 PG-DSO-20-32 (Plastic Dual Small Outline Package)
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-
free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
110
1120
Index Marking
1) Does not include plastic or metal protrusions of 0.15 max per side
2) Does not include dambar protrusion of 0.05 max per side
GPS05094
2.65 max
0.1
0.2
-0.1
2.45
-0.2
+0.15
0.35
1.27
2) 0.2 24x
-0.2
7.6 1)
0.35 x 45˚
0.23
8˚ max
+0.09
+0.8
±0.3
10.3
0.4
12.8-0.21)
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Data Sheet 25 Rev. 1.0, 2008-03-18
BTS4130QGA
Revision History
11 Revision History
Version Date Changes
1.0 2008-03-18 Creation of the data sheet
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Edition 2008-03-18
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2008 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
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