PCA9517AD,118 - NXP Semiconductors

1. General description

The PCA9517A is a CMOS integrated circuit that provides level shifting between low

voltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I2C-bus or SMBus

applications. While retaining all the operating modes and features of the I2C-bus system

during the level shifts, it also permits extension of the I2C-bus by providing bidirectional

buffering for both the data (SDA) and the clock (SCL) lines, thus enabling two buses of

400 pF. Using the PCA9517A enables the system designer to isolate two halves of a bus

for both volt age and cap acitance. The SDA and SCL pins are o vervoltage tolerant and are

high-impedance when the PCA9517A is unpowered.

The 2.7 V to 5.5 V bus port B drivers behave much like the drivers on the PCA9515A

device, while the ad jus table voltage bus port A drivers drive more current and eliminate

the static offset voltage. This results in a LOW on the port B translating into a nearly 0 V

LOW on the port A which accommodates smaller voltage swings of lower voltage logic.

The static offset design of the port B PCA9517A I/O drivers prevent them from being

connected to another device that has rise time accelerator including the PCA9510,

PCA9511, PCA9512, PCA9513, PCA9514, PCA9515A, PCA9516A, PCA9517A (port B),

or PCA9518. Port A of two or more PCA9517As can be connected together, however, to

allow a star topography with port A on the common bus, and port A can be connected

directly to any other buffer with static or dynamic offset voltage. Multiple PCA9517As can

be connected in serie s, port A to port B, with no build-up in offset volt age with only time of

flight delays to consider.

The PCA9517A drive rs ar e no t en ab le d un les s V CC(A) is above 0.8 V and VCC(B) is above

2.5 V. The EN pin can also be used to turn the drivers on and off under system control.

Caution should be observed to only change the state of the enable pin when the bus is

idle.

The output pull-down on the port B internal buffer LOW is set for approximately 0.5 V,

while the input threshold o f the internal buf fer is set about 70 mV lower (0.43 V). When the

port B I/O is driven LOW internally, the LOW is not recognized as a LOW by the input.

This prevents a lock-up condition from occurring. The output pull-down on port A drives a

hard LOW and the input level is set at 0.3VCC(A) to accommodate the need for a lower

LOW level in systems where the low voltage side supply voltage is as low as 0.9 V.

[1] PCA9517 will be discontinued in several years, so move to the PCA9517A for all new designs and system

updates.

[2] The PCA9517A is an improved hot swap and ESD version of the PCA9517, but otherwise operates

identically and should be used for all new designs and system updates.

PCA9517A

Level translating I2C-bus repeater

Rev. 4 — 9 May 2012 Product data sheet

Table 1. PCA9517 and PCA9517A comparison

Parameter PCA9517[1] PCA9517A[2]

electrostatic discharge, HBM > 2 kV > 5.5 kV

Product data sheet Rev. 4 — 9 May 2012 2 of 22

NXP Semiconductors PCA9517A

Level translating I2C-bus repeater

2. Features and benefits

2 channel, bidirectional buffer isolates capacitance and allows 40 0 pF on either side of

the device

Voltage level translation from 0.9 V to 5.5 V and from 2.7 V to 5.5 V

Footprint and fu nc tion a l repl ac em e nt fo r PCA9 51 5/ 15 A

I2C-bus and SMBus compatible

Active HIGH repeater enable input

Open-drain input/outputs

Lock-up free operation

Supports arbitration an d cloc k stre tching across th e re pe a ter

Accommodates Standard-mode and Fast-mode I2C-bus de vices and multiple masters

Powered-off high-impedance I2C-bus pins

Port A operating supply voltage range of 0.9 V to 5.5 V

Port B operating supply voltage range of 2.7 V to 5.5 V

5V tolerant I

2C-bus and enable pins

0 Hz to 400 kHz clock frequency (the maximum system operating frequency may be

less than 400 kHz because of the delays added by the repeater)

ESD protection exceeds 5500 V HBM per JESD22-A114 and 1000 V CDM per

JESD22-C101

Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

Packages offered: SO8, TSSOP8 and HWSON8

3. Ordering information

[1] Also known as MSOP8.

[2] PCA9517ADP/DG is functionally the same (electrically and mechanically) as the PCA9517ADP, but was initially produced (e.g., “born”)

with Dark Green (lead-free and halogen/antimony-free) package material and is a temporary unique orderable part number for

customers who desire to order and only receive Dark Green package material. The standard part PCA9517ADP will transition to Dark

Green package material in 2Q’12 and then the PCA9517ADP and PCA9517ADP/DG devices will be identical. The PCA9517ADP/DG

part number will be EOL after several years as customers who used this temporary part number update their BOM to the normal part

number.

Table 2. Ordering information

Tamb =

−

C to +85

Type number Topside

mark Package

Name Description Version

PCA9517AD PA9517A SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1

PCA9517ADP 9517A TSSOP8[1] plastic thin shrink small outline package; 8 leads;

body width 3 mm SOT505-1

PCA9517ADP/DG 9517A TSSOP8[1][2] plastic thin shrink small outline package; 8 leads;

body width 3 mm SOT505-1

PCA9517ATP 17A HWSON8 plastic thermal enhanced very very thin small outline

package; no leads; 8 terminals; body 2 ×3×0.8 mm SOT1069-2

Product data sheet Rev. 4 — 9 May 2012 3 of 22

NXP Semiconductors PCA9517A

Level translating I2C-bus repeater

4. Functional diagram

5. Pinning information

5.1 Pinning

Fig 1. Functional diagram of PCA9517A

002aad465

PCA9517A

SDAA

SCLA

SDAB

SCLB

CC(A)

CC(B)

GND

CC(B)

pull-up

resistor

Fig 2. Pin configuration for SO8 Fig 3. Pin configuration for TSSOP8

(MSOP8)

Fig 4. Pin configuration for HWSON8

VCC(A) VCC(B)

SCLA SCLB

SDAA SDAB

GND EN

002aad466

PCA9517AD

PCA9517ADP

PCA9517ADP/DG

VCC(A) VCC(B)

SCLA SCLB

SDAA SDAB

GND EN

002aad467

SDAA

GND

SDAB

SCLA

VCC(A)

VCC(B)

SCLB

002aag100

terminal 1

index area 1

PCA9517ATP

Transparent top view

Product data sheet Rev. 4 — 9 May 2012 4 of 22

NXP Semiconductors PCA9517A

Level translating I2C-bus repeater

5.2 Pin description

[1] HWSON8 package die supply ground is connected to both GND pin and exposed center pad. GND pin

must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and

board level performance, the exposed pad needs to be soldered to the board using a corresponding

thermal pad on the board and for proper head conduction through the board, thermal vias need to be

incorporated in the printed-circuit board in the thermal pad region.

6. Functional description

Refer to Figure 1 “Functional diagram of PCA95 17A”.

The PCA9517A enables I2C-bus or SMBus translation down to VCC(A) as low as 0.9 V

without degradation of system performance. The PCA9517A contains two bidirectional

open-drain buffers specifically designed to support up-translation/down-translation

between the low voltage (as low as 0.9 V) and a 3.3 V or 5 V I2C-bus or SMBus. All inputs

and I/Os are overvoltage tolerant to 5.5 V even when the device is unpowered (VCC(B)

and/or VCC(A) = 0 V). The PCA9517A includes a power-up circuit that keeps the output

drivers turned off until VCC(B) is above 2.5 V and the VCC(A) is above 0.8 V. VCC(B) and

VCC(A) can be applied in any sequence at power-up. After power-up and with the enable

(EN) HIGH, a LOW level on port A (below 0.3VCC(A)) turns the corresponding p ort B driver

(either SDA or SCL) on and drives port B down to about 0.5 V. When port A rises above

0.3VCC(A), the port B pull-down driver is turned off and the external pull-up resistor pulls

the pin HIGH. When port B falls first and goes below 0.3VCC(B) the port A driver is turned

on and port A pulls down to 0 V. The port B pull-down is not enabled unless the port B

voltage goes below 0.4 V. If the port B low voltage does not go below 0.5 V, the port A

driver will turn off when port B voltage is above 0.7VCC(B). If the port B low voltage goes

below 0.4 V, the port B pull-down driver is enabled and port B will only be able to rise to

0.5 V until port A rises above 0.3VCC(A), then port B will continue to rise being pulled up by

the external pu ll-u p re sist or. The VCC(A) is only used to provide the 0.3VCC(A) reference to

the port A input comparators and for the power good detect circuit. The PCA9517A logic

and all I/Os are powered by the VCC(B) pin.

Table 3. Pin descripti on

Symbol Pin Description

SO8,

TSSOP8 HWSON8

VCC(A) 1 7 port A supply voltage (0.9 V to 5.5 V)

SCLA 2 8 serial clock port A bus

SDAA 3 1 serial dat a port A bus

GND 4 2[1] supply ground (0 V)

EN 5 3 active HIGH repeater enable input

SDAB 6 4 serial dat a port B bus

SCLB 7 5 serial clock port B bus

VCC(B) 8 6 port B supply voltage (2.7 V to 5.5 V)

Product data sheet Rev. 4 — 9 May 2012 5 of 22

NXP Semiconductors PCA9517A

Level translating I2C-bus repeater

6.1 Enable

The EN pin is active HIGH with an internal pull-up to VCC(B) and allows the user to select

when the repeater is active. This can be used to isolate a badly behaved slave on

power-up until after the system power-up reset. It should never change state during an

I2C-bus operation because disabling during a bus operation will hang the bus and

enabling part way through a bus cycle could confuse the I2C-bus parts being enabled.

The enable pin sh ould o nly change state when th e globa l bus and the repe ater port a re in

an idle state to prevent system failures.

6.2 I2C-bus systems

As with the standard I2C-bus system, pu ll-u p re sistors are required to provide the logic

HIGH levels on the buffered bus (standard open-collector configuration of the I2C-bus).

The size of these pull-up resistors depends on the system, but each side of the repeater

must have a pull-up resistor. This part designed to work with Standard mode and Fast

mode I2C-bus device s in addition to SMBus devices. Standard m ode I2C-bus devices only

specify 3 mA output drive; this limits the termination current to 3 mA in a generic I2C-bus

system where Standard-mode devic es an d mult iple mas te rs are po ssible. Under certain

conditions higher termination currents can be used.

Please see Application Note AN255, I2C/SMBus Repeaters, Hubs and Expanders for

additional information on sizing resistors and precautions when using more than one

PCA9517A in a system or using the PCA9517A in conjunction with other bus buffers.

7. Application design-in information

A typical application is shown in Figure 5. In this example, the system master is running

on a 3.3 V I2C-bus while the slave is connected to a 1.2 V bus. Both buses run at 400 kHz.

Master devices can be placed on either bus.

The PCA9517A is 5 V tolerant, so it does not require any additional circuitry to translate

between 0.9 V to 5.5 V bus voltages and 2.7 V to 5.5 V bus voltages.

Fig 5. Typical application

002aad468

VCC(A)

VCC(B)

PCA9517A

SDAB SDAA

SCLB SCLA

10 kΩ10 kΩ

SDA

SCL

BUS

MASTER

400 kHz SLAVE

400 kHz

SDA

SCL

bus B bus A

1.2 V

3.3 V

10 kΩ10 kΩ

Product data sheet Rev. 4 — 9 May 2012 6 of 22

NXP Semiconductors PCA9517A

Level translating I2C-bus repeater

When port A of the PCA9517A is pulled LOW by a driver on the I2C-bus, a comparator

detects the falling edge when it goes below 0.3VCC(A) and caus es the int er na l driv er on

port B to turn on, causing port B to pull down to about 0.5 V. When port B of the

PCA9517A falls, first a CMOS hysteresis type input detects the falling edge and causes

the internal driver on port A to turn on and pull the port A pin down to ground. In order to

illustrate what would be seen in a typical application, refer to Figure 9 and Figure 10. I f the

bus master in Figure 5 were to write to the slave through the PCA9517A, waveforms

shown in Figure 9 would be observed on the A bus. This looks like a normal I2C-bus

transmission except that the HIGH level may be as low as 0.9 V, and the turn on and turn

off of the acknowledge signals are slightly delayed.

On the B bus side of the PCA9517A, the clock and dat a lines wou ld have a p ositive of fse t

from ground equal to the VOL of the PCA9517 A. After the eigh th clock pulse, the dat a line

will be pulled to the VOL of the slave device which is very close to ground in this example.

At the end of the acknowledge, the level rises only to the LOW level set by the driver in the

PCA9517A for a short de lay while th e A bus side rises above 0.3VCC(A) then it continues

HIGH. It is import ant to note that any arbitrat ion or clock stretch ing event s require th at the

LOW level on the B bus side at the input of the PCA9517A (VIL) be at or below 0.4 V to be

recognized by the PCA9517A and then transmitted to the A bus side.

Multiple PCA9517A port A sides can be connected in a star configuration (Figure 6),

allowing all nodes to communicate with each other.

Multiple PCA9517As can be connected in series (Figure 7) as long as port A is connected

to port B. I2C-bus slave devices can be connected to any of the bus segment s. The

number of devices that can be connected in series is limited by repeater

delay/time-of-flight considerations on the maximum bus speed requirements.

Product data sheet Rev. 4 — 9 May 2012 7 of 22

NXP Semiconductors PCA9517A

Level translating I2C-bus repeater

Fig 6. Ty pical star application

VCC(B)

VCC(A)

PCA9517A

SDAA SDAB

SCLA SCLB

10 kΩ10 kΩ

SDA

SCL

BUS

MASTER SLAVE

400 kHz

SDA

SCL

VCC(B)

VCC(A)

10 kΩ10 kΩ

VCC(B)

VCC(A)

PCA9517A

SDAA SDAB

SCLA SCLB

10 kΩ10 kΩ

SLAVE

400 kHz

SDA

SCL

002aad469

VCC(B)

VCC(A)

PCA9517A

SDAA SDAB

SCLA SCLB

10 kΩ10 kΩ

SLAVE

400 kHz

SDA

SCL

Fig 7. Typical series application

002aad470

PCA9517A

SDAA SDAB

SCLA SCLB

SDA

SCL

BUS

MASTER SLAVE

400 kHz

SDA

SCL

10 kΩ10 kΩ

PCA9517A

SDAA SDAB

SCLA SCLB

VCC

PCA9517A

SDAA SDAB

SCLA SCLB

10 kΩ10 kΩ10 kΩ10 kΩ10 kΩ10 kΩ

Product data sheet Rev. 4 — 9 May 2012 8 of 22

NXP Semiconductors PCA9517A

Level translating I2C-bus repeater

Remark: Figure 9 and Figure 10 reference Figure 8 and assume master on Bus B side and slave

on Bus A side.

Fig 8. Typical application of PCA9517A driving a short cable

Fig 9. Bus A (0.9 V to 5.5 V bus) waveform

Fig 10. Bus B (2.7 V to 5.5 V) waveform

002aad644

VCC(B)

VCC(A)

SDAA SDAB

SCLA SCLB

10 kΩ10 kΩ

VCC(B)

VCC(A)

RPU

GND

75 Ω

RPU 10 kΩ

(optional)

MASTER

SLAVE

CARD 1

CARD 2

002aac775

9th clock pulse

acknowledge

SCL

SDA

002aad471

9th clock pulse

acknowledge

SCL

SDA

of slave

of PCA9517A

Product data sheet Rev. 4 — 9 May 2012 9 of 22

NXP Semiconductors PCA9517A

Level translating I2C-bus repeater

8. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VCC(B) supply voltage port B 2.7 V to 5.5 V −0.5 +7 V

VCC(A) supply voltage port A adjustable −0.5 +7 V

VI/O voltage on an input/output pin port A and port B ; enable pin (EN) −0.5 +7 V

II/O input/output current port A; port B - 50 mA

IIinput cur r en t EN, VCC(A), VCC(B), GND - 50 mA

Ptot total power dissipation - 100 mW

Tstg storage temperature −55 +125 °C

Tamb ambient temperature operating in free air −40 +85 °C

Tjjunction temperature - +125 °C

Product data sheet Rev. 4 — 9 May 2012 10 of 22

NXP Semiconductors PCA9517A

Level translating I2C-bus repeater

9. Static characteristics

Table 5. Static characteristics

VCC = 2.7 V to 5.5 V; GND = 0 V; Tamb =

−

Cto+85

C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Supplies

VCC(B) supply voltage port B 2.7 - 5.5 V

VCC(A) supply voltage port A [1] 0.9 - 5.5 V

ICC(VCC(A)) supply current on pin VCC(A) --1mA

ICCH HIGH-level supply current both channels HIGH;

VCC =5.5V;

SDAn = SCLn = VCC

-1.55mA

ICCL LOW-level supply current both channels LOW;

VCC =5.5V;

one SDA and one SCL = GND;

other SDA and SCL open

-1.55mA

ICC(A)c contention port A supply current VCC =5.5V;

SDAn = SCLn = VCC

-1.55mA

Input and output SDAB and SCLB

VIH HIGH-level input voltage 0.7VCC(B) -5.5 V

VIL LOW-level input voltage [2] −0.5 - +0.3VCC(B) V

VILc contention LOW-level input

voltage −0.5 0.4 - V

VIK input clamping voltage II=−18 mA - - −1.2 V

ILI input leakage current VI=3.6V - - ±1μA

IIL LOW-level input current SDA, SCL; VI=0.2V - - 10 μA

VOL LOW-level output voltage IOL =100μA or 6 mA 0.47 0.52 0.6 V

VOL−VILc dif ference between LOW-level

output and LOW-level input

voltage contention

guaranteed by design - - 70 mV

ILOH HIGH-level output leakage

current VO=3.6V - - 10 μA

Cio input/output capacitance VI= 3 V or 0 V; VCC =3.3V - 6 7 pF

VI= 3 V or 0 V; VCC =0V - 6 7 pF

Input and output SDAA and SCLA

VIH HIGH-level input voltage 0.7VCC(A) -5.5 V

VIL LOW-level input voltage [3] −0.5 - +0.3VCC(A) V

VIK input clamping voltage II=−18 mA - - −1.2 V

ILI input leakage current VI=3.6V - - ±1μA

IIL LOW-level input current SDA, SCL; VI=0.2V - - 10 μA

VOL LOW-level output voltage IOL =6mA - 0.1 0.2 V

ILOH HIGH-level output leakage

current VO=3.6V - - 10 μA

Cio input/output capacitance VI= 3 V or 0 V; VCC =3.3V - 6 7 pF

VI= 3 V or 0 V; VCC =0V - 6 7 pF

Product data sheet Rev. 4 — 9 May 2012 11 of 22

NXP Semiconductors PCA9517A

Level translating I2C-bus repeater

[1] LOW-level supply voltage.

[2] VIL specification is for the first LOW level seen by the SDAB/SCLB lines. VILc is for the second and subsequent LOW levels seen by the

SDAB/SCLB lines.

[3] VIL for port A with envelope noise must be below 0.3VCC(A) for stable performance.

10. Dynamic characteristics

[1] Times are specified with loads of 1.3 5 kΩ pull-up resistance and 57 pF load capacitance on port B, and 167 Ω pull-up resistance and

57 pF load capacitance on port A. Different load resistance and capacitance will alter the RC time constant, thereby changing the

propagation delay and transition times.

[2] Pull-up voltages are VCC(A) on port A and VCC(B) on port B.

[3] Typical values were measured with VCC(A) = 3.3 V at Tamb =25°C, unless otherwise noted.

[4] The tPLH delay data from port B to port A is measured at 0.5 V on port B to 0.5VCC(A) on port A when VCC(A) is less than 2 V, and 1.5 V

on port A if VCC(A) is greater than 2 V.

[5] Typical value measured with VCC(A) =2.7V at T

amb =25°C.

[6] The proportional delay data from port A to port B is measured at 0.3VCC(A) on port A to 1.5 V on port B.

[7] The enable pin, EN, should only change state when the global bus and the repeater port are in an idle state.

Enable

VIL LOW-level input voltage −0.5 - +0.3VCC(B) V

VIH HIGH-level input voltage 0.7VCC(B) -5.5 V

IIL(EN) LOW-level input current on

pin EN VI= 0.2 V, EN; VCC =3.6V - −10 −30 μA

ILI input leakage current −1-+1 μA

Ciinput capacitance VI=3.0V or 0V - 6 7 pF

Table 5. Static characteristics …continued

VCC = 2.7 V to 5.5 V; GND = 0 V; Tamb =

−

Cto+85

C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Table 6. Dynamic characteristics

VCC = 2.7 V to 5.5 V; GND = 0 V; Tamb =

−

Cto+85

C; unless otherwise specified.[1][2]

Symbol Parameter Conditions Min Typ[3] Max Unit

tPLH LOW to HIGH propagation delay port B to port A; Figure 13 [4] 100 170 250 ns

tPHL HIGH to LOW propagation delay port B to port A; Figure 11

VCC(A) ≤2.7 V [5] 30 80 110 ns

VCC(A) ≥3V 10 66 300 ns

tTLH LOW to HIGH output transition time port A; Figure 11 10 20 30 ns

tTHL HIGH to LOW output transition time port A; Figure 11

VCC(A) ≤2.7 V [5] 177105ns

VCC(A) ≥3V 20 70 175 ns

tPLH LOW to HIGH propagation delay port A to port B; Figure 12 [6] 25 53 110 ns

tPHL HIGH to LOW propagation delay port A to port B; Figure 12 [6] 60 79 230 ns

tTLH LOW to HIGH output transition time port B; Figure 12 120 140 170 ns

tTHL HIGH to LOW output transition time port B; Figure 12 30 48 90 ns

tsu set-up time EN HIGH before START condition [7] 100 - - ns

thhold time EN HIGH after STOP condition [7] 100 - - ns

Product data sheet Rev. 4 — 9 May 2012 12 of 22

NXP Semiconductors PCA9517A

Level translating I2C-bus repeater

10.1 AC waveforms

11. Test information

Fig 11. Propagation dela y a nd tran s ition times;

port B to port A Fig 12. Propag a t ion de lay and transi tio n tim e s;

port A to port B

Fig 13. Propa ga tio n de la y

002aad642

3.0 V

1.2 V

PLH

THL

1.5 V 1.5 Vinput

output 20 %

0.6 V 0.6 V 80 %

20 %

80 %

PHL

TLH

0.1 V

002aad643

CC(A)

3.0 V

PLH

THL

0.3V

CC(A)

0.3V

CC(A)

input

output 20 %

1.5 V 1.5 V 80 %

20 %

80 %

PHL

TLH

0.5 V

input

SDAB, SCLB

output

SCLA, SDAA

tPLH

50 % if VCC(A) is less than 2 V

1.5 V if VCC(A) is greater than 2 V

002aad641

RL= load resistor; 1.35 kΩ on port B; 167 Ω on port A (0.9 V to 2.7 V) and 450 Ω on port A (3.0 V

to 5.5 V).

CL= load capacitance includes jig and probe capacitance; 57 pF

RT= termination resistance should be equal to Zo of pulse generators

Fig 14. Test circuit for open-dra in outputs

PULSE

GENERATOR

002aab649

VCC(B)

DUT

VCC(A)

Product data sheet Rev. 4 — 9 May 2012 13 of 22

NXP Semiconductors PCA9517A

Level translating I2C-bus repeater

12. Package outline

Fig 15. Package outline SOT96-1 (SO8)

UNIT A

max. A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 5.0

4.8 4.0

3.8 1.27 6.2

5.8 1.05 0.7

0.6 0.7

0.3 8

0.25 0.10.25

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

1.0

0.4

SOT96-1

detail X

vMA

(A )

pin 1 index

076E03 MS-012

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.20

0.19 0.16

0.15 0.05 0.244

0.228 0.028

0.024 0.028

0.012

0.010.010.041 0.004

0.039

0.016

0 2.5 5 mm

scale

SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1

99-12-27

03-02-18

Product data sheet Rev. 4 — 9 May 2012 14 of 22

NXP Semiconductors PCA9517A

Level translating I2C-bus repeater

Fig 16. Package outline SOT505-1 (TSSOP8)

UNIT A1

max. A2A3bpLHELpwyv

ceD(1) E(2) Z(1) θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.45

0.25 0.28

0.15 3.1

2.9 3.1

2.9 0.65 5.1

4.7 0.70

0.35 6°

0°

0.1 0.10.10.94

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.7

0.4

SOT505-1 99-04-09

03-02-18

0.25

A2A1

(A3)

detail X

vMA

2.5 5 mm0

scale

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1

1.1

pin 1 index

Product data sheet Rev. 4 — 9 May 2012 15 of 22

NXP Semiconductors PCA9517A

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Fig 17. Package outline SOT1069-2 (HWSON8)

References

Outline

version European

projection Issue date

IEC JEDEC JEITA

SOT1069-2 - - -

MO-229

- - -

sot1069-2_po

09-11-18

12-04-18

Unit

mm max

nom

min

0.80

0.75

0.70

0.05

0.02

0.00

2.1

2.0

1.9

1.6

1.5

1.4

3.1

3.0

2.9 0.5 1.5 0.45

0.40

0.35 0.05

A(1)

Dimensions

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

HWSON8: plastic thermal enhanced very very thin small outline package; no leads;

8 terminals; body 2 x 3 x 0.75 mm SOT1069-2

0.65

0.55

0.45

0.2

A3b

0.30

0.25

0.18

D(1) D2E(1) E2

1.6

1.5

1.4

0.40

0.35

0.30

0.1

0.05

0 1 2 mm

scale

terminal 1

index area

B A

detail X

terminal 1

index area b

eAC B

vCw

1 4

Product data sheet Rev. 4 — 9 May 2012 16 of 22

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13. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

13.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole an d

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

13.2 Wave and reflow soldering

W ave soldering is a joinin g technology in which the joint s are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circu it board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

13.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

Product data sheet Rev. 4 — 9 May 2012 17 of 22

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13.4 Reflow soldering

Key characteristics in reflow soldering are:

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 18) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enoug h for the solder to make reliable solder joint s (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 7 and 8

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 18.

Table 7. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm3)

< 350 ≥ 350

< 2.5 235 220

≥ 2.5 220 220

Table 8. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 4 — 9 May 2012 18 of 22

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For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

14. Abbreviations

MSL: Moisture Sensitivity Level

Fig 18. Temperature profiles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Table 9. Abbreviations

Acronym Description

BOM Bill Of Materials

CDM Charged-Device Model

CMOS Complementary Metal-Oxide Semiconductor

EOL End Of Life

ESD ElectroStatic Discharge

HBM Human Body Model

I2C-bus Inter Integrated Circuit bus

I/O Input/Output

RC Resistor-Capacitor network

SMBus System Management Bus

Product data sheet Rev. 4 — 9 May 2012 19 of 22

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15. Revision history

Table 10. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PCA9517A v.4 20120509 Product data sheet - PCA9517A v.3

Modifications: •Tabl e 1 “ PCA9517 and PCA9517A comparison”:

–Table note [1] is rewritten

–Table note [2] is rewritten

•Tabl e 2 “ Ordering information”

–Added type number PCA9517ADP/DG

–Added Table note [2]

•Figure 3 “Pin configuration for TSSOP8 (MSOP8)”: added type number PCA9517ADP/DG

PCA9517A v.3 20120229 Product data sheet - PCA9517A v.2

PCA9517A v.2 20080505 Product data sheet - PCA9517A v.1

PCA9517A v.1 20080222 Product data sheet - -

Product data sheet Rev. 4 — 9 May 2012 20 of 22

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16. Legal information

16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

16.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short dat a sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full dat a

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conf lict with the short data sheet, the

full data sheet shall pre vail.

Product specificat io n — The information and data provided in a Product

data sheet shall define the specification of the product as agr eed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

16.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an inf ormation

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental ,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulat ive liability t owards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors pro duct can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications and ther efore such inclu sion and/or use is at the cu stomer’s own

risk.

Applications — Applications that are described herein for any of these

products are for il lustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liabili ty related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessa ry

testing for th e customer’s applications and pro ducts using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by cust omer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Not hing in this document may be interpret ed or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyri ghts, paten ts or

other industrial or intellectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contain s data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specif ication.

Product [short] dat a sheet Production This document contain s the product specification.

Product data sheet Rev. 4 — 9 May 2012 21 of 22

NXP Semiconductors PCA9517A

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Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for aut omo tive use. It i s neit her qua lif ied nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever cust omer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y

liability, damages or failed product claims resulting f rom customer design an d

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specif ications.

Translations — A non-English (translated) versio n of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

16.4 Trademarks

Notice: All refe renced brands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

I2C-bus — logo is a trademark of NXP B.V.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors PCA9517A

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For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 9 May 2012

Document identifier : PCA9517A

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Functional description . . . . . . . . . . . . . . . . . . . 4

6.1 Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

6.2 I2C-bus systems . . . . . . . . . . . . . . . . . . . . . . . . 5

7 Application design-in information . . . . . . . . . . 5

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 9

9 Static characteristics. . . . . . . . . . . . . . . . . . . . 10

10 Dynamic characteristics . . . . . . . . . . . . . . . . . 11

10.1 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . 12

11 Test information. . . . . . . . . . . . . . . . . . . . . . . . 12

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13

13 Soldering of SMD packages . . . . . . . . . . . . . . 16

13.1 Introduction to soldering . . . . . . . . . . . . . . . . . 16

13.2 Wave and reflow soldering . . . . . . . . . . . . . . . 16

13.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 16

13.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 17

14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 18

15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 19

16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 20

16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20

16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 20

16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21

17 Contact information. . . . . . . . . . . . . . . . . . . . . 21

18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22