Rev 2.0, October 11, 2010 Page 1 of 16
400 West C esar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com
SL15300
Key Features
• Low power dissipation
- 7.9mA-typ at 66MHz and VDD=3.3V
- 7.0mA-typ at 66MHz and VDD=2.5V
• Wide 2.5V to 3.3V +/-10% power supply range
• Programmable 4 outputs from 3 to 200MHz
• Low Jitter
- TBDps at 66MHz
• Programmable Center or Down Spread Modulation
from 0.25 to 5.0%
• 8 to 48 MHz external crystal range
• 8 to 166 MHz external clock range
• Integrated internal voltage regulator
• Programmable PD#/OE/SSON#/FS functions
• Programmable CL at XIN and XOUT pins
• Programmable output rise and fall times
• SSC modulation frequency is 32kHz -typ
Applications
• Printers, MFPs
• Digital Copiers
• NBPCs and LCD Monitors
• Routers, Servers and Switchers
• HDTV and DVD-R/W
Description
The SL15300 a programmable low power Spread
Spectrum Clock Generator (SSCG) used for reducing
Electroma gnet ic Interference (EMI). The product is
designed using SpectraLinear proprietary programmable
EProClock™ phase-locked loop (PLL) and Spread
Spectrum Clock (SSC) technology to synthesize and
modulate the input clo ck. The modu late d clo ck can
significantly reduce the measured EMI levels, and leading
to the compliance with regulatory agency requirements.
Up to 4 output clock frequencies, Spread %, output rise
and fall times, crystal load, modulation frequ en cy and
PD#/OE/SSON#/FS
functions can be programmed to meet
the needs of wide range of applications. The SL15300
operates from 2.5V to 3.3V power supply voltage range.
The product is offered in 8-pin T S SO P package with
commercial and industrial grades.
Refer to SL15L300 Programmable SSCG product for 1.8V
power supply operation.
Benefits
• Peak EMI reduction of 8 to 16 dB
• Fast time-to-market
• Cost Reduction
• Reduction of PCB layers
• Eleminates the need for higher order crystals (Xtals)
and crystal oscil lato rs (X O s)
Block Diagram
3PLL with
Modulation Control 7
Programmable
Configuration Register
2
300K
CLKOUT
XIN/CLKIN
XOUT
VSS
VDD
Output
Buffers,
Dividers
and
Switch
Matrix
PCin
PCout
6REFOUT
1
5
V-Reg
To
Core
To I/O
4 8
PD# SSON#
Programmable Spread Spectrum Clock Generator (SSCG)
Rev 2.0, October 11, 2010 Page 2 of 16
SL15300
Pin Configuration
8
SL15300
-XXX
7
6
54
1
2
3
SSON#
CLKOUT
REFOUT
VSS
PD#
XIN/CLKIN
XOUT
VDD
8-Pin TSSOP
Pin Description
Pin
Number
Pin Name Pin Type
Pin Description
1 VDD Power Positive power supply.
2 XOUT Output Crystal or ceramic resonator output pin. Leave this pin unconnected
(floating) if external clock is used at Pin-3.
3 XIN/CLKIN Input Crystal, ceramic resonator or external clock input pin.
4 PD# Input Power Down (PD#-Active Low): If PD#=0(Low) and Output Enable (OE-
Active High). This pin is weakly pulled high to VDD (200KΩ-typ).
5 VSS Power Power supply ground.
6 REFOUT Output Reference clock output. Frequency at this pin is same as input crystal or
clock.
7 CLKOUT Output This pin can be programmed as SSCLK2 or REFCLK2.
8 SSON# Input Spread Spectrum Clock Control pin. SSON#. If SSON#=0 spread is ON.
If SSON#=1 spread is OFF. This pin is weakly pulled high to VDD
(200KΩ-typ).
Rev 2.0, October 11, 2010 Page 3 of 16
SL15300
General Description
The primary source of EMI from digital circuits is the
system clock and all the other synchronous clocks and
control signals derived from the system clock. The well
know techniques of filtering (suppression) and shielding
(containment), while
effective, can cost money, board
space and longer development time.
A more effective and efficient technique to reduce EMI is
Spread Spectrum Clock Generator (SSCG) technique.
Instead of using constant clock frequency, the SSCG
technique modulates (spreads) the system clock with a
much smaller frequency, to reduce EMI emissions at its
source: The System Clock.
The SL15300 is designed using SpectraLinear
proprietary programmable EProClock™ phase-locked
loop (PLL) and Spread Spectrum Technologies (SST) to
synthesize and modulate (spread) the system clock such
that the energy is spread out over a wider bandwidth.
This reduces the peak value of the radiated emissions at
the fundamental and the harmonics. This reduction in
radiated energy can significantly re
duce the cost of
complying with regulatory agency requirements and
improve time-to-market without degrading system perfor-
mance.
The SL15300 operates from 3.3V to 2.5V power supply
range. Refer to SL15L101 f
or 1.8V power supply
operation.
The SL15300 is available in 8-pin TSSOP package with
Commercial Temperature range of 0 to 70°
C and
Industrial Temperature range of –40 to 85°C.
Input Frequency Range
The input frequency range is from 8.0 to 48.0 MHz f or
crystals and ceramic resonators. If an external clock is
used, the input frequency range is from 8 to 166 MHz.
Output Frequency Range and Outputs
Up to four (4) outputs can be programmed as SSCLK or
REFCLK. SSCLK output can be synthesized to any value
from 3
to 200 MHz with spread based on valid input
frequency. The spread at SSCLK pins can be stopped by
SSON# input control pin, If SSON# pin is HIGH (VDD),
the frequency at this pin is the synthesized
to the
nominal value of the input frequency and there is no
spread.
REFOUT is the buffered output of the oscillator and is
the same frequency as the input frequency without
spread. However, REFOUT value can also be divided by
using the output dividers from 2 to 32. The SS CLK is the
programmed and synthesized value of the input clock.
The remaining SSCLKs cou
ld be the same value
providing fanout of up to 4 or the f
requency can be
divided from also 2 to 32. In this case, the spread %
value is the same as the original programmed spread %
value. By using only first order crystals, SL15300 can
synthesize output frequency up to 200 MHz, eliminating
the need for higher
order Crystals (Xtals) and Crystal
Oscillators (XOs). This reduces the cost while improving
the system clock accuracy, performance and reliability.
Programmable CL (Crystal Load)
The SL15300 provides programma ble on-chip capacitors
at XIN/CLKIN (Pin-3) and XOUT (Pin-2). The resolution of
this program mab le capacit or is 6-bits with LSB value of
0.5pF. When all bits are off the pin capacit ance is
CXIN=CXOUT =8.5pF (minimum value). When all bits are
on the pin capacitance is CXIN=CXOUT=40pF (maximum
value). The values of CXIN and CXOUT based on the CL
(Crystal Load Capacitor) can be calculated as:
CXIN=CXOUT=2CL-CPCB. Refer to the Page-13 for
additional information on crystal load (CL).
In addition, if an external clock is used, the capacitance at
Pin-3 (CLKIN) can programmed to control the edge rate of
this input clock, providing additional EMI control.
Programmable Modulation Frequency
The Spread Spectrum Clock (SSC) modulation default
value is 31.5 kHz. The higher values of up to 120 kHz can
also be programmed. Les s than 30 kHz modulation
frequency is not recommended to stay out of the range
audio frequency bandwidth sin ce this frequ ency cou ld be
detected as a noise by the audio receivers within the
vicinity.
Programmable Spread Percent (%)
The spread percent (%) value is programmable from +/-
0.25% to +/-2.5% (center spread) or -0.5% to -5.0%
(down spread) for all SSCLK frequencies. It is possible to
program smaller or larger non-standard values of spread
percent. Contact SLI if these non-standard spread percent
values are requir ed in the application.
SSON# or Frequency Select (FS)
The SL15300 Pin-8 can also be programmed as either
SSON# to enable or disable the programmed spread
percent value or as Frequency Select (FS). If SSON# is
used, when this pin is pulled high (VDD), the spread is
stopped and the frequency is the nominal value without
spread. If low (GND), the frequency is the nominal value
with the spread.
If FS function is used, the output pins can be programmed
for different set of frequencies as selected by FS. SSCLK
value can be any frequency from 3 to 200MHz, but the
spread % is the same percent v alue. REFOUT is the
same frequency as the input reference clock or divide by
from 2 to 32 without spread. The set of frequencies in
Table 1 is given as en example, using 48MHz crystal.
The SL15300 also allow s a fan-out of up to 4, meaning
that Pins 4, 6, 7 and 8 can be programmed to the same
frequencies with or without spread.
FS
(Pin-8)
SSCLK1/2
(Pins-6/7)
REFCLK4
(Pin-4)
0
66MHz, +/-2%
48MHz
1
33MHz, +/-2%
24MHz
Table 1. Frequency Selection (FS)
Power Down (PD#) or Output Enable (OE)
The SL15300 Pin-4 can be programmed as either PD# or
OE. PD# powers down the entire chip whereas OE only
disables the output buffers to Hi-Z.
Rev 2.0, October 11, 2010 Page 4 of 16
SL15300
Absolute Maximum Ratings
Description
Condition
Unit
Supply voltage, VDD
V
All Inputs and Outputs
V
Ambient Operating Temperature
In operation, C-Grade
°C
Ambient Operating Temperature In operation, I-Grade -40 85 °C
Storage Temperature No power is applied -65 150 °C
Junction Temperature
In operation, power is applied
°C
Soldering Temperature
°C
ESD Rating (Human Body Model) JEDEC22-A114D -4,000 4,000 V
ESD Rating (Charge Device Model) JEDEC22-C101C -1,500 1,500 V
ESD Rating (Machine Model) JEDEC22-A115D -250 250 V
Latch-up 125°C -200 200 mA
DC Electrical Characteristics (C-Grade)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70 Deg C
Description Symbol Condition Min Typ Max Unit
Operating Voltage VDD VDD+/-10% 2.97 3.3 3.63 V
Input Low Voltage VIL CMOS Level, if Pins 4 and 8
programmed as PD#, OE,
SSON# or FS 0 - 0.3VDD V
Input High Voltage VIH CMOS Level, if Pins 4 and 8
programmed as PD#, OE,
SSON# or FS. 0.7VDD - VDD V
Output High Voltage VOH1 IOH=10mA , If Pins 4, 6, 7 and
8 are programmed as
SSCLK/REFCLK VDD-0.5 - - V
Output Low Voltage VOL1 IOL=10mA, If Pins 4, 6, 7 and 8
are programmed as
SSCLK/REFCLK - - 0.5 V
Input High Current IIH
VIN=VDD, Pins 4 and 8. If
outputs are programmed as
PD#, OE, SSON# or FS and no
pull-up/down resister used
-10 - 10 μA
Input Low Current IIL
VIN=GND, Pins 4 and 8. If
outputs are programmed as
PD#, OE, SSON# or FS and no
pull-up/down resister used
-10 - 10 μA
Pull-up or Down Resistors RPU/D CMOS Level, if Pins 4 and 8
programmed as PD#, OE,
SSON# or FS 90 160 230 kΩ
Rev 2.0, October 11, 2010 Page 5 of 16
SL15300
Operating Supply Current IDD FIN=30MHz and all 4 clocks are
at 66MHz and +/-2.0% Spread
and CL=0 - 7.9 9.4 mA
Standby Current ISBC PD#=GND - 70 90 μA
Output Leakage Current IOL Pins 4, 6, 7 and 8 if
programmed as SSCLK or
REFOUT -10 - 10 μA
Programmable
Input Capacitance at
Pins 2 and 3
PCin
PCout
Minimum setting value - 8 - pF
Maximum setting value - 40 - pF
Resolutio n (progr am mi ng step s) - 0.5 - pF
Input Capacitance CIN2 Pins 4 and 8 if programmed as
PD#, OE, SSON or FS - 4 6 pF
Load Capacitance CL Pins 4, 6, 7 and 8 If
programmed as SSCLK or
REFCLK - - 15 pF
AC Electrical Characteristics (C-Grade)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70 Deg C
Parameter Symbol
Condition Min Typ Max Unit
Input Frequency Range FIN1 Crystal or Ceramic Resonator 8 - 48 MHz
Input Frequency Range FIN2 External Clock 8 - 166 MHz
Output Frequency Range
FOUT1 SSCLK 3 - 200 MHz
Output Frequency Range
FOUT2 REFCLK, crystal or resonator input 0.25 - 48 MHz
O
utput Frequency Range
FOUT3 REFCLK, clock input 0.25 - 166 MHz
Output Duty Cycle DC1 SSCLK 45 50 55 %
Output Duty Cycle DC2 REFCLK , Xtal input 45 50 55 %
Output Duty Cycle DC3 REFCLK, clock input 40 50 60 %
Input Duty Cycle DCIN Clock Input, Pin 3 40 50 60 %
Output Rise/Fall Time tr/f1 Programmable, VDD=3.3V,
CL=15pF, 20 to 80% of VDD - 4.00 4.80 ns
Output Rise/Fall Time tr/f2 Programmable, VDD=3.3V,
CL=15pF, 20 to 80% of VDD - 2.00 2.40 ns
Output Rise/Fall Time tr/f3 Programmable, VDD=3.3V,
CL=15pF, 20 to 80% of VDD - 1.40 1.70 ns
Output Rise/Fall Time tr/f4 Programmable, VDD=3.3V,
CL=15pF, 20 to 80% of VDD - 1.10 1.35 ns
Output Rise/Fall Time tr/f5 Programmable, VDD=3.3V,
CL=15pF, 20 to 80% of VDD - 0.85 1.00 ns
Output Rise/Fall Time tr/f6 Programmable, VDD=3.3V,
CL=15pF, 20 to 80% of VDD - 0.70 0.85 ns
Output Rise/Fall Time tr/f7 Programmable, VDD=3.3V,
CL=15pF, 20 to 80% of VDD - 0.55 0.67 ns
Rev 2.0, October 11, 2010 Page 6 of 16
SL15300
Cycle-to-Cycle Jitter
(SSCLK – Pins 4/6/7/8) CCJ1 FIN=30MHz, all 4 clocks are at
33MHz, +/-2.0% Spread. CL=15pF - TBD TBD ps
Cycle-to-Cycle Jitter
(SSCLK – Pins 4/6/7/8) CCJ2 FIN=30MHz, all 4 clocks are at
33MHz, +/-2.0% Spread. CL=15pF - TBD TBD ps
Power-down Time tPD Time from PD# falling edge to Hi-Z
at outputs (Asynchronous) - 150 350 ns
Power-up Time
(Crystal or Resonator)
tPU1 Time from PD# rising edge to valid
frequency at outp uts
(Asynchronous)
- 3.5 5.0 ms
Power-up Time
(Clock)
tPU2 Time from PD# rising edge to valid
frequency at outp uts
(Asynchronous)
- 2.0 3.0 ms
Output Enable Time tOE Time from OE falling edge to Hi-Z at
outputs (Asynchronous) - 180 350 ns
Output Disable Time tOD Time from OE falling edge to Hi-Z at
outputs (Asynchronous) - 180 350 ns
Spread Percent Range SPR-1 Center Spread, SSCLK-1/2/3/4 +/-0.125 - +/-2.5 %
Spread Percent Range SPR-2 Down Spread, SSCLK-1/2/3/4 -5.0 - -0.25 %
Spread Percent Variation
ΔSS% Variation of programmed Spread % -15 - 15 %
Modulation Frequency FMOD Programmable, 31.5 kHz standard 30 31.5 120 kHz
DC Electrical Characteristics (C-Grade)
Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range 0 to +85 Deg C
Description Symbol Condition Min Typ Max Unit
Operating Voltage VDD VDD+/-10% 2.25 2.5 2.75 V
Input Low Voltage VIL CMOS Level, if Pins 4 and 8
programmed as PD#, OE,
SSON# or FS 0 - 0.3VDD V
Input High Voltage VIH CMOS Level, if Pins 4 and 8
programmed as PD#, OE,
SSON# or FS. 0.7VDD - VDD V
Output High Voltage VOH1 IOH=10mA , If Pins 4, 6, 7 and
8 are programmed as
SSCLK/REFCLK VDD-0.4 - - V
Output Low Voltage VOL1 IOL=10mA, If Pins 4, 6, 7 and 8
are programmed as
SSCLK/REFCLK - - 0.4 V
Input High Current IIH
VIN=VDD, Pins 4 and 8. If
outputs are programmed as
PD#, OE, SSON# or FS and no
pull-up/down resister used
-10 - 10 μA
Input Low Current IIL
VIN=GND, Pins 4 and 8. If
outputs are programmed as
PD#, OE, SSON# or FS and no
pull-up/down resister used
-10 - 10 μA
Rev 2.0, October 11, 2010 Page 7 of 16
SL15300
Pull-up or Down Resistors RPU/D CMOS Level, if Pins 4 and 8
programmed as PD#, OE,
SSON# or FS 90 160 230 kΩ
Operating Supply Current IDD FIN=30MHz and all 4 clocks are
at 66MHz and +/-2.0% Spread
and CL=0 - 7.0 8.3 mA
Standby Current ISBC PD#=GND - 70 90 μA
Output Leakage Current IOL Pins 4, 6, 7 and 8. If
programmed as SSCLK or
REFCLK -10 - 10 μA
Programmable
Input Capacitance at
Pins 2 and 3
PCin
PCout
Minimum setting value - 8 - pF
Maximum setting value - 40 - pF
Resolutio n (progr am mi ng step s) - 0.5 - pF
Input Capacitance CIN2 Pins 4 and 8
If programmed as PD#, OE,
SSON or FS - 4 6 pF
Load Capacitance CL Pins 4, 6, 7 and 8. If
programmed as SSCLK or
REFCLK - - 15 pF
AC Electrical Characteristics (C-Grade)
Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range 0 to +85 Deg C
Parameter Symbol
Condition Min Typ Max Unit
Input Frequency Range FIN1 Crystal or Ceramic Resonator 8 - 48 MHz
Input Frequency Range FIN2 External Clock 8 - 166 MHz
Output Frequency Range
FOUT1 SSCLK 3 - 200 MHz
Output Frequency Range
FOUT2 REFCLK, crystal or resonator input 0.25 - 48 MHz
Output Frequency Range
FOUT3 REFCLK, clock input 0.25 - 166 MHz
Output Duty Cycle DC1 SSCLK 45 50 55 %
Output Duty Cycle DC2 REFCLK, Xtal input 45 50 55 %
Output Duty Cycle DC3 REFCLK, clock input 40 50 60 %
Input Duty Cycle DCIN Clock Input, Pin 3 40 50 60 %
Output Rise/Fall Time tr/f1 Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD - 4.80 5.80 ns
Output Rise/Fall Time tr/f2 Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD - 2.60 3.10 ns
Output Rise/Fall Time tr/f3 Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD - 1.80 2.20 ns
Output Rise/Fall Time tr/f4 Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD - 1.40 1.70 ns
Rev 2.0, October 11, 2010 Page 8 of 16
SL15300
Output Rise/Fall Time tr/f5 Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD - 1.10 1.35 ns
Output Rise/Fall Time tr/f6 Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD - 0.90 1.10 ns
Output Rise/Fall Time tr/f7 Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD - 0.70 0.85 ns
Cycle-to-Cycle Jitter
(SSCLK – Pins 4/6/7/8 ) CCJ1 FIN=30MHz, all 4 clocks are at
33MHz, +/-2.0% Spread. CL=15pF - TBD TBD ps
Cycle-to-Cycle Jitter
(SSCLK – Pins 4/6/7/8) CCJ2 FIN=30MHz, all 4 clocks are at
33MHz, +/-2.0% Spread. CL=15pF - TBD TBD ps
Power-down Time tPD Time from PD# falling edge to Hi-Z
at outputs (Asynchronous) - 150 350 ns
Power-up Time
(Crystal or Resonator)
tPU1 Time from PD# rising edge to valid
frequency at outp uts
(Asynchronous)
- 3.5 5.0 ms
Power-up Time
(Clock)
tPU2 Time from PD# rising edge to valid
frequency at outp uts
(Asynchronous)
- 2.0 3.0 ms
Output Enable Time tOE Time from OE falling edge to Hi-Z at
outputs (Asynchronous) - 180 350 ns
Output Disable Time tOD Time from OE falling edge to Hi-Z at
outputs (Asynchronous) - 180 350 ns
Spread Percent Range SPR-1 Center Spread, SSCLK-1/2/3/4 +/-0.125 - +/-2.5 %
Spread Percent Range SPR-2 Down Spread, SSCLK-1/2/3/4 -5.0 - -0.25 %
Spread Percent Variation
ΔSS% Variation of programmed Spread % -15 - 15 %
Modulation Frequency FMOD Programmable, 31.5 kHz standard 30 31.5 120 kHz
DC Electrical Characteristics (I-Grade)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85 Deg C
Description Symbol Condition Min Typ Max Unit
Operating Voltage VDD VDD+/-10% 2.97 3.3 3.63 V
Input Low Voltage VIL CMOS Level, if Pins 4 and 8
programmed as PD#, OE,
SSON# or FS 0 - 0.3VDD V
Input High Voltage VIH CMOS Level, if Pins 4 and 8
programmed as PD#, OE,
SSON# or FS. 0.7VDD - VDD V
Output High Voltage VOH1 IOH=10mA , If Pins 4, 6, 7 and
8 are programmed as
SSCLK/REFCLK VDD-0.5 - - V
Output Low Voltage VOL1 IOL=10mA, If Pins 4, 6, 7 and 8
are programmed as
SSCLK/REFCLK - - 0.5 V
Rev 2.0, October 11, 2010 Page 9 of 16
SL15300
Input High Current IIH
VIN=VDD, Pins 4 and 8. If
outputs are programmed as
PD#, OE, SSON# or FS and no
pull-up/down resister used
-15 - 15 μA
Input Low Current IIL
VIN=GND, Pins 4 and 8. If
outputs are programmed as
PD#, OE, SSON# or FS and no
pull-up/down resister used
-15 - 15 μA
Pull-up or Down Resistors RPU/D CMOS Level, if Pins 4 and 8
programmed as PD#, OE,
SSON# or FS 100 160 220 kΩ
Operating Supply Current IDD FIN=30MHz and all 4 clocks are
at 66MHz and +/-2.0% Spread
and CL=0 - 8.2 9.8 mA
Standby Current ISBC PD#=GND - 80 100 μA
Output Leakage Current IOL Pins 4, 6, 7 and 8. If
programmed as SSCLK or
REFCLK -10 - 10 μA
Programmable
Input Capacitance at
Pins 2 and 3
PCin
PCout
Minimum setting value - 8 - pF
Maximum setting value - 40 - pF
Resolutio n (progr am mi ng step s) - 0.5 - pF
Input Capacitance CIN2 Pins 4 and 8
If programmed as PD#, OE,
SSON or FS - 4 6 pF
Load Capacitance CL Pins 4, 6, 7 and 8. If
programmed as SSCLK or
REFCLK - - 15 pF
AC Electrical Characteristics (I-Grade)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85 Deg C
Parameter Symbol
Condition Min Typ Max Unit
Input Frequency Range FIN1 Crystal or Ceramic Resonator 8 - 48 MHz
Input Frequency Range FIN2 External Clock 8 - 166 MHz
Output Frequency Range
FOUT1 SSCLK 3 - 200 MHz
Output Frequency Range
FOUT2 REFCLK, crystal or resonator input 0.25 - 48 MHz
Output Frequency Range
FOUT3 REFCLK, clock input 0.25 - 166 MHz
Output Dut y Cycle DC1 SSCLK 45 50 55 %
Output Duty Cycle DC2 REFCLK, Xtal input 45 50 55 %
Output Duty Cycle DC3 REFCLK, clock input 40 50 60 %
Input Duty Cycle DCIN Clock Input, Pin 3 40 50 60 %
Output Rise/Fall Time tr/f1 Programmable, VDD=3.3V,
CL=15pF, 20 to 80% of VDD - 4.00 4.80 ns
Rev 2.0, October 11, 2010 Page 10 of 16
SL15300
Output Rise/Fall Time tr/f2 Programmable, VDD=3.3V,
CL=15pF, 20 to 80% of VDD - 2.00 2.40 ns
Output Rise/Fall Time tr/f3 Programmable, VDD=3.3V,
CL=15pF, 20 to 80% of VDD - 1.40 1.70 ns
Output Rise/Fall Time tr/f4 Programmable, VDD=3.3V,
CL=15pF, 20 to 80% of VDD - 1.10 1.35 ns
Output Rise/Fall Time tr/f5 Programmable, VDD=3.3V,
CL=15pF, 20 to 80% of VDD - 0.85 1.00 ns
Output Rise/Fall Time tr/f6 Programmable, VDD=3.3V,
CL=15pF, 20 to 80% of VDD - 0.70 0.85 ns
Output Rise/Fall Time tr/f7 Programmable, VDD=3.3V,
CL=15pF, 20 to 80% of VDD - 0.55 0.67 ns
Cycle-to-Cycle Jitter
(SSCLK – Pins 4/6/7/8) CCJ1 FIN=30MHz, all 4 clocks are at
33MHz, +/-2.0% Spread. CL=15pF - TBD TBD ps
Cycle-to-Cycle Jitter
(SSCLK – Pins4/6/7/8) CCJ2 FIN=30MHz, all 4 clocks are at
66MHz, +/-2.0% Spread. CL=15pF - TBD TBD ps
Power-down Time tPD Time from PD# falling edge to Hi-Z
at outputs (Asynchronous) - 150 350 ns
Power-up Time
(Crystal or Resonator)
tPU1 Time from PD# rising edge to valid
frequency at outp uts
(Asynchronous)
- 3.5 5.0 ms
Power-up Time
(Clock)
tPU2 Time from PD# rising edge to valid
frequency at outp uts
(Asynchronous)
- 2.0 3.0 ms
Output Enable Time tOE Time from OE falling edge to Hi-Z at
outputs (Asynchronous) - 180 350 ns
Output Disable Time tOD Time from OE falling edge to Hi-Z at
outputs (Asynchronous) - 180 350 ns
Spread Percent Range SPR-1 Center Spread, SSCLK-1/2/3/4 +/-0.125 - +/-2.5 %
Spread Percent Range SPR-2 Down Spread, SSCLK-1/2/3/4 -5.0 - -0.25 %
Spread Percent Variation
ΔSS% Variation of programmed Spread % -20 - 20 %
Modulation Frequency FMOD Programmable, 31.5 kHz standard 30 31.5 120 kHz
DC Electrical Characteristics (I-Grade)
Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85 Deg C
Description Symbol Condition Min Typ Max Unit
Operating Voltage VDD VDD+/-10% 2.25 2.5 2.75 V
Input Low Voltage VIL CMOS Level, if Pins 4 and 8
programmed as PD#, OE,
SSON# or FS 0 - 0.3VDD V
Input High Voltage VIH CMOS Level, if Pins 4 and 8
programmed as PD#, OE,
SSON# or FS. 0.7VDD - VDD V
Rev 2.0, October 11, 2010 Page 11 of 16
SL15300
Output High Voltage VOH1 IOH=10mA , If Pins 4, 6, 7 and
8 are programmed as
SSCLK/REFCLK VDD-0.4 - - V
Output Low Voltage VOL1 IOL=10mA, If Pins 4, 6, 7 and 8
are programmed as
SSCLK/REFCLK - - 0.4 V
Input High Current IIH
VIN=VDD, Pins 4 and 8. If
outputs are programmed as
PD#, OE, SSON# or FS and no
pull-up/down resister used
-15 - 15 μA
Input Low Current IIL
VIN=GND, Pins 4 and 8. If
outputs are programmed as
PD#, OE, SSON# or FS and no
pull-up/down resister used
-15 - 15 μA
Pull-up or Down Resistors RPU/D CMOS Level, if Pins 4 and 8
programmed as PD#, OE,
SSON# or FS 90 160 230 kΩ
Operating Supply Current IDD FIN=30MHz and all 4 clocks are
at 66MHz and +/-2.0% Spread
and CL=0 - 7.2 8.6 mA
Standby Current ISBC PD#=GND - 80 100 μA
Output Leakage Current IOL Pins 4, 6, 7 and 8. If
programmed as SSCLK or
REFCLK -10 - 10 μA
Programmable
Input Capacitance at
Pins 2 and 3
PCin
PCout
Minimum setting value - 8 - pF
Maximum setting value - 40 - pF
Resolutio n (progr am mi ng step s) - 0.5 - pF
Input Capacitance CIN2 Pins 4 and 8
If programmed as PD#, OE,
SSON or FS - 4 6 pF
Load Capacitance CL Pins 4, 6, 7 and 8. If
programmed as SSCLK or
REFCLK - - 15 pF
AC Electrical Characteristics (I-Grade)
Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85 Deg C
Parameter Symbol
Condition Min Typ Max Unit
Input Frequency Range FIN1 Crystal or Ceramic Resonator 8 - 48 MHz
Input Frequency Range FIN2 External Clock 8 - 166 MHz
Output Frequency Range
FOUT1 SSCLK 3 - 200 MHz
Output Frequency Range
FOUT2 REFCLK, crystal or resonator input 0.25 - 48 MHz
Output Frequency Range
FOUT3 REFCLK, clock input 0.25 - 166 MHz
Output Duty Cycle DC1 SSCLK 45 50 55 %
Rev 2.0, October 11, 2010 Page 12 of 16
SL15300
Output Dut y Cycle DC2 REFCLK, Xtal input 45 50 55 %
Output Duty Cycle DC3 REFCLK, clock input 40 50 60 %
Input Duty Cycle DCIN Clock Input, Pin 3 40 50 60 %
Output Rise/Fall Time tr/f1 Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD - 4.80 5.80 ns
Output Rise/Fall Time tr/f2 Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD - 2.60 3.10 ns
Output Rise/Fall Time tr/f3 Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD - 1.80 2.20 ns
Output Rise/Fall Time tr/f4 Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD - 1.40 1.70 ns
Output Rise/Fall Time tr/f5 Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD - 1.10 1.35 ns
Output Rise/Fall Time tr/f6 Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD - 0.90 1.10 ns
Output Rise/Fall Time tr/f7 Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD - 0.70 0.85 ns
Cycle-to-Cycle Jitter
(SSCLK – Pins 4/6/7/8) CCJ1 FIN=30MHz, all 4 clocks are at
33MHz, +/-2.0% Spread. CL=15pF - TBD TBD ps
Cycle-to-Cycle Jitter
(SSCLK – Pins 4/6/7/8) CCJ2 FIN=30MHz, all 4 clocks are at
33MHz, +/-2.0% Spread. CL=15pF - TBD TBD ps
Power-down Time tPD Time from PD# falling edge to Hi-Z
at outputs (Asynchronous) - 180 350 ns
Power-up Time
(Crystal or Resonator)
tPU1 Time from PD# rising edge to valid
frequency at outp uts
(Asynchronous)
- 3.5 5.0 ms
Power-up Time
(Clock)
tPU2 Time from PD# rising edge to valid
frequency at outp uts
(Asynchronous)
- 2.0 3.0 ms
Output Enable Time tOE Time from OE falling edge to Hi-Z at
outputs (Asynchronous) - 180 350 ns
Output Disable Time tOD Time from OE falling edge to Hi-Z at
outputs (Asynchronous) - 180 350 ns
Spread Percent Range SPR-1 Center Spread, SSCLK-1/2/3/4 +/-0.125 - +/-2.5 %
Spread Percent Range SPR-2 Down Spread, SSCLK-1/2/3/4 -5.0 - -0.25 %
Spread Percent Variation
ΔSS% Variation of programmed Spread % -20 - 20 %
Modulation Frequency FMOD Programmable, 31.5 kHz standard 30 31.5 120 kHz
Rev 2.0, October 11, 2010 Page 13 of 16
SL15300
External Components & De sign Considerations
Typical Application Schematic
SL15300
XIN(3) VDD(1)
XOUT(2)
SSCLK1(7)
SSCLK3(4)
66 MHz, +/-1.5% Spread
27MHz
0.1μF
VSS(5)
SSCLK2(8)
27 MHz, No Spread
VDD
REFCLK(6)
66 MHz, +/-1.5% Spread
33 MHz, +/-1.5% Spread
Comments an d Recommendations
Decoupling Capacitor: A decoupling capacitor of 0.1μF must be used between VDD and VSS on the pins 1 and 5.
Place the capacitor on the component side of the PCB as close to the VDD pin as possible. The PCB trace to the
VDD pin and to the GND via should be kept as short as possible Do not use vias between the decoupling capacitor
and the VDD pin.
Series Termination Resistor: A series termination resistor is recommended if the distance between the outputs
(SSCLK or REFCLK pins) and the load is over 1 ½ inch. The nominal impedance of the SSCLK output is about 30 Ω.
Use 20 Ω resistor in series with the output to terminate 50Ω trace impedance and place 20 Ω resistor as close to the
SSCLK output as possible.
Crystal and Crystal Load: Use only parallel resonant fundamental crystals. DO NOT USE higher over to ne cry stal s.
To meet the crystal initial accuracy specification (in ppm); the internal on-chip programmable capacitors PCin and
PCout must be programmed to match the crystal load requirement. These values are given by the formula below:
PCin(pF) =PCout(pF)= [(CL(pF) – Cp(pF)/2)] x 2
Where CL is crystal load capacitor as given by the crystal datasheet and Cp(pF) is the compensation factor for the
total parasitic capacitance at XIN or XOUT pin including PCB related parasitic capacitance.
As an example; if a crystal with CL=18pF is used and Cp=4pF, by using the above formula, PCin=PCout=[(18-(4/2)] x
2 = 32pF. Programming PCin and PCout to 32pF assures that this crystal sees an equivalent load of 18pF and no
other external crystal load capacitor is needed. Deviating from the crystal load specification could cause an increase
in frequency accuracy in ppm. Refer to the Table 5 for the recommended crystal specifications.
Rev 2.0, October 11, 2010 Page 14 of 16
SL15300
Recommended External Crystal Specifications
Parameter
Description
Min
Typ
Max
Unit
Comments
FNOM Nominal Crystal
Frequency Range
8 - 48 MHz Fundamental Mode – AT Cut
CL
Nominal Crystal Load
6
12
18
pF
Load for +/-0 ppm Fo resonance
value
R1,1
Equivalent Series
Resistance
20
40
100
Ohm
F-Range: 8.0 to 12.999 MHz
R1,2
Equivalent Series
Resistance
12.5
25
60
Ohm
F-Range: 13.0 to 19.999 MHz
R1,3 Equivalent Series
Resistance
10 20 50 Ohm F-Range: 20.0 to 48.000 MHz
DL1,1
Crystal Drive Level
-
-
200
µW
F-Range: 8.0 to 19.999 MHz
DL1,2
Crystal Drive Level
-
-
150
µW
F-Range: 20.0 to 48.000 MHz
Co1
Shunt Capacitance
-
4
5.4
pF
S MD Xta l s
Co2
Shunt Capacitance
-
5
7.2
pF
Through Hole (Leaded) Xtals
Table 5. Recommended Crystal Specifications
Rev 2.0, October 11, 2010 Page 15 of 16
SL15300
Package Ou t lin e and Pack ag e Dim en sio ns
8-Pin TSSOP Package (173 Mil)
1 4
8 5
6.250(0.246)
6.500(0.256)
4.300(0.169)
4.500(0.177)
2.900(0.114)
3.100(0.122)
0.850(0.033)
0.950(0.037)
0.190(0.007)
0.300(0.012) 0.650(0.025)
BSC
0.050(0.002)
0.150(0.006)
1.100(0.043) MAX
0.076(0.003)
0 to 8°
0.500(0.020)
0.700(0.027)
0.650(0.025)
BSC Gauge
Plane
0.090(0.003)
0.200(0.008)
Dimensions are in milimeters(inches).
Top line: (MIN) and Bottom line: (Max)
Pin-1 ID
Seating Plane
Thermal Characteristics
Parameter Symbol Condition Min Typ Max Unit
Ther mal R esistance
Junctio n to Ambient
θ JA Still air - 110 - °C/W
θ JA 1m/s air flow - 100 - °C/W
θ JA 3m/s air flow - 80 - °C/W
Ther mal R esistance
Junction to Case
θ JC Independent of air flow - 35 - °C/W
Rev 2.0, October 11, 2010 Page 16 of 16
SL15300
Ordering Information
[1]
Ordering Number [2] Marking Shipping Package Package Temperature
SL15300EZC-XXX
SL15300EZC-XXX
Tube
8-pin TSSOP
0 to 70°C
SL15300EZCT-XXX
SL15300EZC-XXX
Tape and Reel
8-pin TSSOP
0 to 70°C
SL15300EZI-XXX
SL15300EZI-XXX
Tube
8-pin TSSOP
-40 to 85°C
SL15300EZIT-XXX
SL15300EZI-XXX
Tape and Reel
8-pin TSSOP
-40 to 85°C
Notes:
1. All SLI products are RoHS compliant.
2. “XXX” is “Dash” number and will be assigned by SLI for final programmed samples or production
units based on the each customer programming requirements.
The information i n this document is beli eved to be accurate in all respects at the time of public ation but is subject to change without
notice. Si licon Laboratories assumes no responsibility for errors and om issions, and disclaims responsibil ity for any cons equences
resulting from the us e of information included herein. Additionall y, Silicon Laboratories assumes no responsi bility for the functioning
of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon
Laboratories mak es no warranty, representat ion or guarantee regarding the s uitability of its products for any particular purpos e, nor
does Silic on Laborat ori es assume any liability arisi ng out of the application or us e of any product or circuit, and speci fically disclaims
any and all liability, includi ng without limit ation consequential or incidental damages. Silic on Laboratories products are not desi gned,
intended, or aut horized for use in appli cations intended to s upport or sustain life, or for any other applicat ion in which the failure of
the Silicon Laboratories product could create a situation where personal injury or death m ay occur. Should Buyer purchase or use
Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon
Laboratories harml ess against all claims and damages.
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Silicon Laboratories:
SL15300ZC SL15300ZCT SL15300ZI SL15300ZIT