Semiconductor Components Industries, LLC, 2004
October, 2004 − Rev. 5 1Publication Order Number:
NTHS5443T1/D
NTHS5443
Power MOSFET
−20 V, −4.9 A, P−Channel ChipFET
Features
•Low RDS(on) for Higher Efficiency
•Logic Level Gate Drive
•Miniature ChipFET Surface Mount Package Saves Board Space
•Pb−Free Package is Available
Applications
•Power Management in Portable and Battery−Powered Products; i.e.,
Cellular and Cordless Telephones and PCMCIA Cards
MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Rating Symbol 5 secs Steady
State Unit
Drain−Source Voltage VDS −20 V
Gate−Source Voltage VGS 12 V
Continuous Drain Current
(TJ = 150°C) (Note 1)
TA = 25°C
TA = 85°C
ID
−4.9
−3.5 −3.6
−2.6
A
Pulsed Drain Current IDM 15 A
Continuous Source Current (Note 1) IAS −2.1 −1.1 A
Maximum Power Dissipation (Note 1)
TA = 25°C
TA = 85°C
PD2.5
1.3 1.3
0.7
W
Operating Junction and Storage
Temperature Range TJ, Tstg −55 to +150 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq
[1 oz] including traces).
Device Package Shipping†
ORDERING INFORMATION
NTHS5443T1 ChipFET 3000/Tape & Reel
G
S
D
P−Channel MOSFET
http://onsemi.com
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
−20 V 56 m @ −4.5
RDS(on) TYP
−4.9 A
ID MAXV(BR)DSS
NTHS5443T1G ChipFET
(Pb−Free) 3000/Tape & Reel
ChipFET
CASE 1206A
STYLE 2
MARKING
DIAGRAM
1
2
3
4
D
D
D
G
D
S
PIN
CONNECTIONS
8
7
6
5
5
6
7
81
2
3
4
A4 M
A4 = Specific Device Code
M = Month Code
D
D
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2
THERMAL CHARACTERISTICS
Characteristic Symbol Typ Max Unit
Maximum Junction−to−Ambient (Note 2)
t 5 s
Steady State
RJA 40
80 50
95
°C/W
Maximum Junction−to−Foot (Drain)
Steady State RJF 15 20 °C/W
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic Symbol Test Condition Min Typ Max Unit
Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID = −250 A −0.6 V
Gate−Body Leakage IGSS VDS = 0 V, VGS = 12 V 100 nA
Zero Gate Voltage Drain Current IDSS VDS = −16 V, VGS = 0 V −1.0 A
VDS = −16 V, VGS = 0 V,
TJ = 85°C−5.0
On−State Drain Current (Note 3) ID(on) VDS −5.0 V, VGS = −4.5 V −15 A
Drain−Source On−State Resistance
(Note 3) rDS(on) VGS = −4.5 V, ID = −3.6 A
VGS = −3.6 V, ID = −3.3 A 0.056
0.065 0.065
0.074
VGS = −2.5 V, ID = −2.7 A 0.095 0.110
Forward Transconductance (Note 3) gfs VDS = −10 V, ID = −3.6 A 10 S
Diode Forward Voltage (Note 3) VSD IS = −1.1 A, VGS = 0 V −0.8 −1.2 V
Dynamic (Note 4)
Total Gate Charge QG7.5 12 nC
Gate−Source Charge QGS VDS = −10 V, VGS = −4.5 V,
I
D
= −3.6 A 0.9 2.8
Gate−Drain Charge QGD
ID
=
−
3
.
6
A
2.2 −
T urn−On Delay Time td(on) 8.5 13 s
Rise Time trVDD = −10 V, RL = 10
ID10A V
GEN = 45V
14 21
Turn−Off Delay Time td(off) ID −1.0 A, VGEN = −4.5 V,
RG = 6 38 57
Fall Time tf
G
30 45
Source−Drain Reverse Recovery Time trr IF = −1.1 A, di/dt = 100 A/s 30 60 ns
2. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq [1 oz] including traces).
3. Pulse Test: Pulse Width 300 s, Duty Cycle 2%.
4. Guaranteed by design, not subject to production testing.
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3
TYPICAL ELECTRICAL CHARACTERISTICS
−6 V
125°C
−1.6 V
0
10
2.5
8
6
31.51
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
−ID, DRAIN CURRENT (AMPS)
4
2
00.5
Figure 1. On−Region Characteristics
0.5
10
8
21.5 2.5
6
4
2
1
03
Figure 2. Transfer Characteristics
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0.05
24
0.15
0.1
06
Figure 3. On−Resistance versus
Gate−to−Source Voltage
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
−ID, DRAIN CURRENT (AMPS)
191085
0.06
4
0.04
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
−ID, DRAIN CURRENT (AMPS)
−50 0−25 25
1.4
1.2
1
0.8
0.6 50 125100
Figure 5. On−Resistance Variation with
Temperature
TJ, JUNCTION TEMPERATURE (°C)
TJ = 25°C
VGS = −1.4 V
0.2
13
TJ = −55°C
ID = −3.6 A
TJ = 25°C
0.08
0.02
75 150
TJ = 25°C
ID = −3.6 A
VGS = −4.5 V
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
2
25°C
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
1.6
VGS = −4.5 V
VGS = −6 V
−1.8 V
−2 V
−2.2 V
−2.4 V
−3.4 V
−5 V
−4 V
−2.8 V
−2.6 V
VDS ≥ −10 V
05 7623
04 8
1000
100
10 2016
Figure 6. Drain−to−Source Leakage Current
versus Voltage
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
12
VGS = 0 V
−IDSS , LEAKAGE (nA)
10,000
TJ = 150°C
TJ = 100°C
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4
TYPICAL ELECTRICAL CHARACTERISTICS
VDS = 0 V VGS = 0 V
10510 15
1800
900
600
300
020
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
C, CAPACITANCE (pF)
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
TJ = 25°C
Coss
Ciss
Crss
1500
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
101
10
1100
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
t, TIME (ns)
VDD = −10 V
ID = −1.0 V
VGS = −4.5 V
1000
50
1200
td(off)
td(on)
tf
tr
−VGS −VDS
100
QG, TOTAL GATE CHARGE (nC)
0
1
2
3
4
5
012345678
0
1
2
3
4
5
6
7
8
9
10
11
ID = −3.6 A
TJ = 25°C
QGD/QGS = 3.1
QG
QGD
QGS
0.0001 1
0.01 100.10.01
SQUARE WAVE PULSE DURATION (sec)
0.1
1
0.001
Figure 10. Normalized Thermal Transient Impedance, Junction−to−Ambient
Duty Cycle = 0.5
100 1000
NORMALIZED EFFECTIVE TRANSIENT
THERMAL IMPEDANCE
0.2
Single Pulse
0.1
0.05
0.02
PER UNIT BASE = RJA =
80°C/W
TJM − TA = PDMZJA(t)
SURFACE MOUNTED
PDM
t1
t2
DUTY CYCLE, D = t1/t2
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5
PACKAGE DIMENSIONS
ChipFET
CASE 1206A−03
ISSUE E
STYLE 1:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. GATE
5. SOURCE
6. DRAIN
7. DRAIN
8. DRAIN
BS
C
D
G
L
A
1234
8765
M
J
K
1234
8765
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A2.95 3.10 0.116 0.122
B1.55 1.70 0.061 0.067
C1.00 1.10 0.039 0.043
D0.25 0.35 0.010 0.014
G0.65 BSC 0.025 BSC
J0.10 0.20 0.004 0.008
K0.28 0.42 0.011 0.017
L0.55 BSC 0.022 BSC
M°5 NOM
S1.80
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM
PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET IN
HORIZONTAL AND VERTICAL SHALL NOT EXCEED
0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE
BURRS.
6. NO MOLD FLASH ALLOWED ON THE TOP AND
BOTTOM LEAD SURFACE.
7. 1206A−01 AND 1206A−02 OBSOLETE. NEW
STANDARD IS 1206A−03.
0.05 (0.002)
°5 NOM
2.00 0.072 0.080
Basic Style 1 mm
inches
0.178
0.007
2.032
0.08
1.727
0.068
0.66
0.026
0.711
0.028
0.457
0.018
0.457
0.018
2.032
0.08
0.635
0.025
0.66
0.026
0.711
0.028 mm
inches
SCALE 20:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINTS*
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to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NTHS5443T1/D
ChipFET is a trademark of Vishay Siliconix.
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