SY89853U
Precision Low-Power Dual 2:1 LVPECL MUX
with Inter nal Termination
Precision Edge is a registered tradem ark of Micrel, Inc
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
August 2007
M9999-082907-C
hbwhelp@micrel.com or (408) 955-1690
General Description
The SY89853U features two, low jitter 2:1 differential
multiplexers with 100K LVPECL (800mV) compatible
outputs, capable of handling clocks up to 2.5GHz and
data streams up to 2.5Gbps.
The SY89853U differential inputs include Micrel’s
unique, 3-input termination architecture that allows
users to interface to any differential signal (AC- or DC-
Coupled) as small as 100mV without any level shifting
or term ination resistors networks in the signal path. The
result is a clean, stub-free, low jitter interface solution.
The differential 800mV LVPECL outputs have fast
rise/fall times guaranteed to be less than 180ps.
The SY89853U operates from a 2.5V ±5% or a 3.3V
±10% supply, and is guaranteed over the full industrial
temperature range (–40°C to +85°C). For applications
that require higher performance, consider the
SY58026U. The SY89853U is part of Micrel's Precision
Edge® product family.
All support doc umentat ion can be found on Mic rel’s web
site at www.micrel.com.
Precision Edge®
Features
• Dual 2:1 MUX, each channel selects from inputs
• Unique, patent -pending input isolation design
minimizes crosstalk
• Low power 210mW (VCC = 2.5V)
• Guaranteed AC performance over temperature and
voltage:
- DC-to->2.5Gbps data rate throughput
- <360ps IN-to-Q tpd
- <180ps tr/tf times
• Ultra-low jitter design:
- <1psRMS random jitter
- <10psPP deterministic jitter
- <10psPP total jitter (clock)
- <0.7psRMS crosstalk-induced jitter
• Unique, patent -pe nd ing 50Ω input termination and
VT pin accepts DC- and AC-coupled inputs (CML,
LVDS, PECL)
• 800mV LVPECL output swing
• Power supply 2.5V ±5% or 3.3V ±10%
• –40°C to +85°C temperature range
• Available in 32-pin (5mm x 5mm) QFN package
Applications
• Data communication systems
• All SONET OC-3 to OC-48 app licat ions
• All Fibre Channel applications
• All GigE applications
Markets
• LAN/WAN communication
• Enterprise servers
• ATE
• Test and measurement
Micrel, Inc.
SY89853U
August 2007 3 M9999-082907-C
hbwhelp@micrel.com or (408) 955-1690
Ordering Information(1)
Part Number Package
Type Operating
Range Package Marking Lead Finish
SY89853UMG QFN-32 Industrial SY89853U with Pb-Free bar-line indicator NiPdAu Pb-Free
SY89853UMGTR(2) QFN-32 Industrial SY89853U with Pb-F ree bar-line indicator NiPdAu Pb-Free
Notes:
1. Contact f act ory for die availabi lit y. Dice are guaranteed at TA = 2 5ºC, DC Electricals on l y.
2. Tape and Reel.
Pin Configuration
32-Pin QFN
Pin Description
Pin Number Pin Name Pin Function
25, 28,
29, 32
1, 4
5, 8
INA0, /INA0,
INA1, /INA1,
INB0, /INB0,
INB1, /INB1
Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs
accept AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally
terminates to a VT pin through 50Ω. Note that these inputs will default to an indeterminate
state if left open. Connecting one input to VCC and the complementary input-to-GND
through 1kΩ resistor can terminate unused differential input pairs. The VT pin is to be left
open in this configuration. Please refer to the “Input Interface Applications” section for more
details.
10, 13, 16, 17,
20, 23 VCC Positive power supply. Bypass with 0.1µF//0.01µF low ESR capacitors. The 0.01µF
capacitor should be as close to VCC pin as possible.
14, 19 NC Not connected.
18
15 SELA,
SELB Bank A and Bank B Input Channel Select (TTL/CMOS): These TTL/CMOS-compatible
inputs select the inputs to the multiplexers. These inputs are internally connected to a
25kΩ pull-up resistor and will default to logic HIGH state if left open.
22, 21
12, 11 QA, /QA,
QB, /QB Differential Outputs: These LVPECL output pairs are the outputs of the device. They are a
logic function of the INA0, INA1, INB0, INB1 and SELA and SELB inputs. Please refer to
the “Truth Table” below for details.
26, 30
2, 6 VTA0, VTA1
VTB0, VTB1 Input Termination Center-Tap: Each side of the differential input pair terminates to a VT
pin. The VTA0, VTA1, VTB0, VTB1 pins provide a center-tap to a termination network for
maximum interf ac e flex ibil ity . S ee “Input Interface Applic ations” section for details.
27
31
3
7
VREF-ACA0,
VREF-ACA1,
VREF-ACB0,
VREF-ACB1
Reference Voltages: These reference voltage outputs are equivalent to VCC-1.2V. They are
used for AC-coupled inputs. Connect VREF-AC directly to the VT pin and bypass with
0.01µF low ESR capacitor to VCC. See “Input Interfac e App li cati ons ” section. Maximum
sink/source current is ±1.5mA.
9, 24 GND,
Exposed Pad Ground: Ground pins and exposed pad must be connected to the same ground plane.
Micrel, Inc.
SY89853U
August 2007 4 M9999-082907-C
hbwhelp@micrel.com or (408) 955-1690
Absolute Maximum Ratings(1)
Supply Voltage (VCC) ............................ –0.5V to +4.0V
Input Voltage (VIN) .................................... –0.5V to VCC
LVPECL Output Current (IOUT)
Continuous ................................................. ±50mA
Surge ....................................................... ±100mA
Termination Current
Source or Sink Current on VT .................... ±50mA
Input Current
Source or Sink Current on IN, /IN .............. ±50mA
Current (VREF-AC)
Source or Sink Current on VREF-AC ............... ±2mA
Lead Temperature (soldering, 20sec.) ............... 260°C
Storage Temperature (Ts) .................–65°C to +150°C
Operating Ratings(2)
Supply Voltage (VCC) ..................... +2.375V to +2.625V
..................................................... +3.0V to +3.6V
Ambient Temperature (TA) .................... –40°C to +85°C
Package Thermal Resistance(3)
QFN (θJA)
Still-Air ...................................................... 35°C/W
500lfpm .................................................... 28°C/W
QFN (ψJB)
Junction-to-Board ..................................... 16°C/W
DC Electrical Characteristics(4)
TA = –40°C to +85°C, unless otherwise noted.
Symbol Parameter Condition Min Typ Max Units
VCC Power Supply VCC = 2.5V
VCC = 3.3V 2.375
3.0 2.5
3.3 2.625
3.6 V
V
ICC Power Supply Current No load, max. VCC. 65 85 mA
RIN Input Resistance
(IN-to-VT) 45 50 55 Ω
RDIFF_IN Differential Input Resistance
(IN-to-/IN) 90 100 110 Ω
VIH Input High Voltage
(IN, /IN) Note 5 VCC– 1.6 VCC V
VIL Input Low Voltage
(IN, /IN) 0 VIH– 0.1 V
VIN Input Voltage Swing
(IN-to-/IN) See Figure 1a. 0.1 1.7 V
VDIFF_IN Differential Input Voltage Swing
|IN - /IN| See Figure 1b. 0.2 V
VT_IN Maximum Input Voltage
(IN-to-VT) 1.28 V
VREF-AC Output Reference Vol tage VCC– 1.3 VCC– 1.2 VCC– 1.1 V
Notes:
1. Permanent device dam age may occur if absolute maximum ratings are exceeded. This is a stress rating only and functi onal operation is not
implied at conditions other than those detailed i n the operational sect i ons of this data sheet. Exposure to absol ut e maximum ratings condit i ons
for extended periods may affect device reliabil ity.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. θJA and ψJB
values are determined for a 4-layer board in still-air, unl ess ot herwise stated.
4. The ci rcuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been establis hed.
5. VIH (min) not lower than 1.2V.
Micrel, Inc.
SY89853U
August 2007 5 M9999-082907-C
hbwhelp@micrel.com or (408) 955-1690
LVPECL Outputs DC Electrical Characteristics(5)
VCC = 2.5V ±5% or 3.3V ±10%; RL = 50Ω to VCC–2V; TA = –40°C to +85°C, unless otherwise noted.
Symbol Parameter Condition Min Typ Max Units
VOH Output High Voltage
(Q, /Q) VCC–1.145 VCC–0.895 V
VOL Output Low Voltage
(Q, /Q) VCC–1.945 VCC–1.695 V
VOUT Output Voltage Swing
(Q, /Q) See Figure 1a. 400 800 mV
VDIFF-OUT Differential Output Voltage Swing
(Q, /Q) See Figure 1b. 800 1600 mV
LVTTL/CMOS DC Electrical Characteristics(5)
VCC = 2.5V ±5% or 3.3V ±10%; TA = –40°C to +85 °C, unl es s other wis e noted.
Symbol Parameter Condition Min Typ Max Units
VIH Input High Voltage 2.0 V
VIL Input Low Voltage 0.8 V
IIH Input High Current VIN = VCC 75 µA
IIL Input Low Current VIN = 0.5V –300 µA
Notes:
5. The ci rcuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been establis hed.
Micrel, Inc.
SY89853U
August 2007 6 M9999-082907-C
hbwhelp@micrel.com or (408) 955-1690
AC Electrical Characteristics(6)
VCC = 2.5V ±5% or 3.3V ±10%; TA = –40°C to + 85°C, RL = 5 0Ω to VCC–2V, unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
fMAX Maximum Operating Frequency NRZ Data 2.5 Gbps
Clo ck, VOUT > 400mV 2.5 GHz
tpd Propagation Delay
IN-to-Q
SEL-to-Q
160 250 360 ps
100 260 400 ps
tpd
Tempco Differential Propagation Del ay
Temperature Coefficient 143 fs/ ºC
tSKEW Input-to-Input Skew (Within-bank)
Bank-to-Bank Skew Note 7 10 20 ps
Note 8 12 25 ps
tJITTER Data
Random Jitter (RJ) Note 9 1 psRMS
Determini sti c Jitt er (DJ) Note 10 10 psPP
Clo ck
Cycle-to-Cyc le Jitter Note 11 1 psRMS
Total Jitter (TJ) Note 12 10 psPP
Crosstalk-Induced Jitter
Channel-to-Channel (Within-bank)
Note 13, within-bank
0.7
psRMS
tr, tf Output Rise/Fall Time (20% to 80%) At full output swing. 50 100 180 ps
Notes:
6. High-speed AC parameters are guaranteed by design and characterization. VIN swing ≥ 100mV, unless otherwise stated.
7. Input-to-input skew is the difference in time between two inputs to the output within a bank.
8. Bank-to-bank skew is the difference in time from input to the output between banks.
9. Random jitt er is measured with a K28.7 character pattern, measured at <fMAX.
10. Determini st ic jitter is m easured at 2.5Gbps with both K28.5 and 223-1 PRBS pattern.
11. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn – Tn-1 where T is the t ime between rising edges of the
output signal.
12. Total jitter definition: with an ideal clock input of frequency <fMAX, no more than one output edge in 1012 output edges will deviate by more than
the specified peak-to-peak jitter value.
13. Crosst alk is measured at the output while applying two similar differential cl ock frequencies that are asynchronous with respect to each other
at the inputs.
Micrel, Inc.
SY89853U
August 2007
10 M9999-082907-
C
hbwhelp@micrel.com or (408) 955-1690
Input and Output Stages
Figure 2a. Simplified Differential Input Stage
Figure 2b. Simplified LVPECL Output Stage
Input Interface Applications
Figure 3a. LVPECL Interface
(DC-Coupled)
Figure 3b. LVPECL Interface
(AC-Coupled)
Figure 3c. LVDS Interface
option: may connect VT to VCC.
Figure 3d. CML Interface
(DC-Coupled)
Figure 3e. CML Interface
(AC-Coupled)
Micrel, Inc.
SY89853U
August 2007
11 M9999-082907-
C
hbwhelp@micrel.com or (408) 955-1690
Output Interface Applications
LVPECL has high input impedance, very low output
(open emitter) impedance, and small signal swing,
which result in low EMI. LVPECL is ideal for driving
50Ω and 100Ω controlled impedance transmission
lines. There are different techniques for terminating
LVPECL outputs: Parallel Termination Thevenin-
Equivalent, Parallel Term ination (3-r esistor), an d AC-
coupled term ination. Un used outp ut pairs m ay be left
floating; however, single-ended outputs must be
terminated or balanced.
Note:
1. For a 2.5V system, R1 = 250Ω, R2 = 62.5 Ω.
2. For a 3.3V system, R1 = 130Ω, R2 = 82Ω.
Figure 4a. Parallel Thevenin-Equivalent
Termination
Note:
1. For a 2.5V system, Rb = 19Ω.
2. For a 3.3V system, Rb = 50 Ω.
Figure 4b. Parallel Termination
(3-Resistor)
Note:
For a 2.5V system, R = 50Ω.
Figure 4c. AC-Coupled Termination
Note:
For a 2.5V system, R1 = 250Ω, R2 = 62.5 Ω.
Figure 4d. Parallel Thevenin-Equivalent
Termination
Related Product and Support Documentation
Part Number Function Data Sheet Link
SY58026U 5Gbps Dual 2 :1 400mV LVPECL MUX
with Internal Term i nation www.micrel.com/product-info/products/sy58026u.shtml.
HBW Sol utions New Products and Applications www.micrel.com/product-info/products/solutions.shtml
Micrel, Inc.
SY89853U
August 2007 12 M9999-082907-C
hbwhelp@micrel.com or (408) 955-1690
Package Information
32-Pin QFN
PCB Thermal Consideration for 32-Pin QFN Package
(Always solder, or equivalent, the exposed pad to the PCB)
Packages Notes:
1. Package m eets Level 2 Moisture Sensiti vity Classification.
2. All parts are dry-packed before shipment.
3. Exposed pads must be soldered to a ground for proper thermal management.
Micrel, Inc.
SY89853U
August 2007 13 M9999-082907-C
hbwhelp@micrel.com or (408) 955-1690
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http: /ww w .micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for
its use. Micrel reserves the right to change circuit ry and specificati ons at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support applianc es, devices or systems where malfunction of a
product can reasonably be expected to result in personal i nj ury. Lif e support devices or systems are devices or systems that (a) are intended for
surgical implant int o the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant
injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk
and Purchaser agrees to fully indem nify Micrel f or any damages resulting from such use or sale.
© 2005 Micrel, Incorporated.
