x
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________________General Description
The MAX1661/MAX1662/MAX1663 serial-to-parallel/
parallel-to-serial converters are intended to control external
power MOSFETs in power-plane switching applications.
These small, low-cost devices can be used on a system
motherboard to control point-of-load switching from a 2-
wire SMBus™ serial interface. Each device has three high-
voltage open-drain outputs that double as TTL-level logic
inputs, giving them bidirectional capabilities. The I/O pins
can withstand +28V, so they can control battery voltage-
distribution switches in notebook computers.
The MAX1661 is intended for driving N-channel MOSFETs
and its outputs are low upon power-up. The MAX1662/
MAX1663 are intended for P-channel MOSFETs, and their
outputs are high-impedance upon power-up. This ensures
that the MOSFETs are off at power-up, so the system can
enforce power-plane sequencing.
The SMBSUS control input selects control data between
two separate data registers. This feature allows the system
to select between two different power-plane configurations
asynchronously, eliminating latencies introduced by the
serial bus. Other features include thermal-overload and
overcurrent protection, ultra-low supply current, and both
hardware and software interrupt capabilities. These
devices are available in the space-saving 10-pin µMAX
package.
________________________Applications
Power-Plane Switching
Point-of-Load Power-Bus Switching
Notebook and Subnotebook Computers
Desktop Computers
Smart Batteries
____________________________Features
♦Performs Serial-to-Parallel and Parallel-to-Serial
Conversions
♦Three General-Purpose Digital Input/Output Pins
(withstand +28V)
♦SMBus 2-Wire Serial Interface
♦Supports SMBSUS Asynchronous Suspend Mode
♦3µA Supply Current
♦+2.7V to +5.5V Supply Range
♦Space-Saving, Low-Cost 10-Pin µMAX Package
MAX1661/MAX1662/MAX1663
________________________________________________________________
Maxim Integrated Products
1
1
2
3
4
5
10
9
8
7
6
ALERT
SMBCLK
SMBDATA
SMBSUSI/O3
I/O2
I/O1
VCC
MAX1661
MAX1662
MAX1663
µMAX
TOP VIEW
ADDGND
__________________Pin Configuration
19-1306; Rev 0; 10/97
PART
MAX1661EUB
MAX1662EUB
MAX1663EUB -40°C to +85°C
-40°C to +85°C
-40°C to +85°C
TEMP. RANGE PIN-PACKAGE
10 µMAX
10 µMAX
10 µMAX
EVALUATION KIT
AVAILABLE
______________Ordering Information
Typical Operating Circuits appear at end of data sheet.
SMBus is a trademark of Intel Corp.
PART POWER-ON-
RESET STATE INTENDED
APPLICATION SMBus ADDRESS
ADDRESS PIN ADDRESS
MAX1661 Outputs Low N-Channel MOSFETs GND
High-Z
VCC
0100000
0111100
1001000
MAX1662 Outputs High
(high-Z state) P-Channel MOSFETs GND
High-Z
VCC
0100001
0111101
1001001
MAX1663 Outputs High
(high-Z state) P-Channel MOSFETs GND
High-Z
VCC
0100010
0111110
1001010
______________________________________________________________Selector Guide
Serial-to-Parallel/Parallel-to-Serial Converters and
Load-Switch Contr ollers with SMBus Interface
MAX1661/MAX1662/MAX1663
Serial-to-Parallel/Parallel-to-Serial Converters and
Load-Switch Contr ollers with SMBus Interface
2_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA= TMIN to TMAX, unless otherwise noted. Typical values are for TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC to GND..............................................................-0.3V to +6V
I/O to GND (I/O1, I/O2, I/O3)..................................-0.3V to +30V
I/O Sink Current (I/O1, I/O2, I/O3),
Internally Limited.............................................-1mA to +50mA
Digital Inputs to GND (SMBCLK, SMBDATA,
SMBSUS, ALERT).................................................-0.3V to +6V
ADD to GND...............................................-0.3V to (VCC + 0.3V)
SMBDATA Current, ALERT Current....................-1mA to +50mA
Continuous Power Dissipation (TA= +70°C)
10-pin µMAX (derate 5.6mW/°C above +70°C)...........444mW
Operating Temperature Range
MAX166_EUB ..................................................-40°C to +85°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10sec).............................+300°C
VCC falling
Measured between the 10% level of the falling
edge and the 10% level of the rising edge
Static condition; SMBDATA, SMBCLK, ADD,
ALERT = VCC or GND (Note 2)
Measured between the 90% level of the rising
edge and the 90% level of the falling edge
(Notes 3, 4)
SMBCLK, SMBDATA
VALERT = 5.5V, high-Z state
VCC = 2.7V to 5.5V;
SMBDATA, SMBCLK, SMBSUS
VSMBDATA, VSMBCLK, VSMBSUS,
VADD = 0V, VCC
VALERT = 0.4V
VSMBDATA = 0.6V
VI/O_ = 0V, VCC; high-impedance state
VI/O_ = 28V, high-impedance state
VI/O_ = 0.4V, VCC = 2.7V or 5.5V
VI/O_ = 1.0V, VCC = 4.5V
I/O1, I/O2, or I/O3; VCC = 4.5V
Typical hysteresis of 10°C
I/O_, SMBSUS, SMBCLK, SMBDATA
CONDITIONS
µs4.7tLOW
SMBCLK Low Time
µs4tHIGH
SMBCLK High Time
kHz100SMBus Clock Frequency pF5SMBus Input Capacitance µA1
ALERT Output Leakage Current mA1
ALERT Output Low Sink Current
mA6
SMBDATA Output Low Sink
Current
VLogic Input Low Voltage V2.4Logic Input High Voltage
V1.2 1.6 2.5
Undervoltage Lockout/
Power-On Reset Threshold
µA3 10
V2.7 5.5Input Voltage Range
Supply Current
V0 5.5
SMBus Logic Input
Voltage Range
µA-1 1Digital Input Current
-1 0.5 1 µA
0.5 5
I/O Leakage Current
mA
2
I/O Sink Current 813 mA15 20 50I/O Current Limit °C140Thermal Shutdown
UNITSMIN TYP MAXSYMBOLPARAMETER
0.8
I/O_, SMBSUS, SMBCLK, SMBDATA
MAX1661/MAX1662/MAX1663
Serial-to-Parallel/Parallel-to-Serial Converters and
Load-Switch Contr ollers with SMBus Interface
_______________________________________________________________________________________ 3
Note 1: Specifications from 0°C to -40°C are guaranteed by design, not production tested.
Note 2: Supply current is specified for static state only.
Note 3: The SMBus logic block is a static design that works with clock frequencies down to DC. While slow operation is possible, it
violates the 10kHz minimum clock frequency of the SMBus specifications, and may monopolize the bus.
Note 4: Refer to Figures 2a and 2b for SMBus timing parameter definitions (write and read diagrams).
Note 5: A transition must internally provide a hold time of 300ns to accommodate for the undefined region of the falling edge.
Note 6: Refer to Figure 3 for the acknowledge timing diagram and tDV parameter definition.
Note 7: Refer to Figure 5 for START-STOP interrupt timing diagrams and parameter definitions.
Note 8: Refer to Figure 4 for I/O setup and hold timing parameter definitions.
10% or 90% of SMBDATA
to 10% of the rising edge
of SMBCLK
Measured from 90% of the rising edge
of SMBCLK to 10% of the rising edge of
SMBDATA
Measured from 10% of the falling edge
of SMBDATA to 90% of the falling edge of
SMBCLK
Measured from 90% of the SMBCLK rising
edge to 90% of the SMBDATA falling edge
CONDITIONS
ns
500
tSU:DAT
µs4tSU:STO
SMBus Stop-Condition Setup
Time
µs4tHD:STA
Start-Condition Hold Time
µs4.7tSU:STA
Start-Condition Setup Time
UNITSMIN TYP MAXSYMBOLPARAMETER
Measured from 10% or 90% of VI/O to 10% of
the rising edge of SMBCLK (Note 8)
Measured from SMBCLK rising edge to 10%
or 90% of I/O (Note 4)
Between stop and start conditions (Note 7)
Tested with a 10kΩpull-up resistor on
SMBDATA (Note 6)
(Notes 4, 5)
µs15tSU:I/O
I/O Data Valid to SMBCLK
Rising-Edge Setup Time
ns100tP:I/O
SMBus Write to I/O_
Propagation Delay
µs4.7tBUF
SMBus Bus-Free Time
µs1tDV
SMBCLK Falling Edge to
SMBus Data Valid Time
µs0tHD:DAT
SMBCLK Falling Edge to
SMBDATA Transition Hold Time
Measured from the 10% point of the falling
edge of SMBDATA to the 10% point of the
rising edge of SMBDATA (Note 7)
(Note 8)
µs10 15 30tLOW:SS
START-STOP Software-Interrupt
Pulse Width
µs0tHD:I/O
I/O Data Hold Time
1000
SMBDATA Valid to SMBCLK
Rising Edge Time, Slave
Clocking in Data
VCC = 4.5V
to 5.5V
VCC = 2.7V
to 4.5V
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.7V to +5.5V, TA= TMIN to TMAX, unless otherwise noted. Typical values are for TA= +25°C.) (Note 1)
MAX1661/MAX1662/MAX1663
Serial-to-Parallel/Parallel-to-Serial Converters and
Load-Switch Contr ollers with SMBus Interface
4_______________________________________________________________________________________
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__________________________________________Typical Operating Characteristics
(VCC = +5.0V, TA= +25°C, unless otherwise noted.)
0
3.0
1.5
7.5
9.0
6.0
4.5
10.5
15.0
13.5
12.0
0 1.2 1.80.6 2.4 3.0 3.6 4.2 4.8 5.4 6.0
I/O_ SINK CURRENT
vs. SUPPLY VOLTAGE
MAX1661toc01
SUPPLY VOLTAGE (V)
SINK CURRENT (mA)
VI/O_ = 1.0V
VI/O_ = 0.4V
0
1.0
0.5
2.5
2.0
1.5
4.0
3.5
3.0
4.5
2.0 3.0 3.52.5 4.0 4.5 5.0 5.5
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1661toc02
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (µA)
0
1.5
1.0
0.5
2.5
2.0
4.5
4.0
3.5
3.0
5.0
-40 -20 0 20 40 60 80 100
SUPPLY CURRENT
vs. TEMPERATURE
MAX1661toc03
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
VCC = 5.5V
VCC = 2.7V
ALL I/Os OFF
10
12
14
16
18
20
22
24
26
-40 40200-20 60 80 100
I/O_ CURRENT LIMIT
vs. TEMPERATURE
MAX1661toc04
TEMPERATURE (°C)
CURRENT LIMIT (mA)
VI/O_ FORCED TO 15V
VCC = 5.5V
0
10
5
20
15
30
25
35
3.0 4.0 4.53.5 5.0 5.5
POR DELAY vs. SUPPLY VOLTAGE
MAX1661toc07
SUPPLY VOLTAGE (V)
POR DELAY (µs)
0
5.0
2.5
12.5
10.0
7.5
15.0
17.5
25.0
22.5
20.0
0 6 93 12 15 18 21 24 27 30
I/O_ CURRENT LIMIT vs. I/O_ VOLTAGE
MAX1661toc05
VI/O_ (V)
CURRENT LIMIT (mA)
VCC = 2.7V
VCC = 5.5V
0
5
10
15
20
25
30
35
40
-40 40200-20 60 80 100
POR DELAY vs. TEMPERATURE
MAX1661toc06
TEMPERATURE (°C)
POR DELAY (µs)
0
0.3
0.2
0.1
0.5
0.4
0.9
0.8
0.7
0.6
1.0
-40 -20 0 20 40 60 80 100
I/O_ INPUT BIAS CURRENT
vs. TEMPERATURE
MAX1661toc08
TEMPERATURE (°C)
INPUT BIAS CURRENT (µA)
VCC = 5.5V
VI/O_ = 15V
0
0.2
0.1
0.5
0.4
0.3
0.6
0.7
1.0
0.9
0.8
0 6 93 12 15 18 21 24 27 30
I/O_INPUT BIAS CURRENT
vs. OUTPUT VOLTAGE
MAX1661toc09
OUTPUT VOLTAGE (V)
INPUT BIAS CURRENT (µA)
MAX1661/MAX1662/MAX1663
Serial-to-Parallel/Parallel-to-Serial Converters and
Load-Switch Contr ollers with SMBus Interface
_______________________________________________________________________________________ 5
______________________________________________________________Pin Description
NAME FUNCTION
1 VCC Supply Voltage Input, 2.7V to 5.5V.
2 I/O1 Input 1 or Output 1 (open drain). This pin can tolerate up to 28V.
PIN
3 I/O2 Input 2 or Output 2 (open drain). This pin can tolerate up to 28V.
4 I/O3 Input 3 or Output 3 (open drain). This pin can tolerate up to 28V.
8 SMBDATA SMBus Serial-Data Input/Output (open drain)
7SMBSUS SMBus Suspend-Mode Control Input. Drive low to select the suspend-mode register. Drive high to select
the normal-mode register. (See
Detailed Description.
)
6 ADD SMBus Address Select Pin (see Table 1 for details).
5 GND Ground
10 ALERT Interrupt Output, active low, open drain
9 SMBCLK SMBus Serial Clock Input
INPUT
REGISTER
TRANSITION
DETECTORS
SMBSUS
NORMAL
DATA
REGISTER
NORMAL
I/01
I/02
I/03
SUSPEND
O1
CONTROL
NORMAL
SUSPEND
CONTROL
NORMAL
SUSPEND
CONTROL
SUSPEND-
MODE
DATA
REGISTER
ALERT
RESPONSE
REGISTER
ADDRESS
DECODER
SMB
THERMAL
SHUTDOWN
8
7
ALERT
FAULT
LATCH S
R
ADD
SMBDATA
SMBCLK
MAX1661/
MAX1662/
MAX1663
O2
O3
MUX
MUX
MUX
Figure 1. Functional Diagram
_______________Detailed Description
The MAX1661/MAX1662/MAX1663 convert 2-wire
SMBus serial data into three latched parallel outputs
(I/O1, I/O2, I/O3). These devices are intended to drive N-
channel and P-channel, high-side MOSFET switches in
load power-management systems. Readback capabili-
ties allow them to function as parallel-to-serial devices.
The MAX1661/MAX1662/MAX1663 operate from a single
supply with a typical quiescent current of 3µA, making
them ideal for portable applications (Figure 1).
SMBus Interface Operation
The SMBus serial interface is a 2-wire interface with
multi-mastering capability. From a software perspec-
tive, the MAX1661/MAX1662/MAX1663 appears as a
set of byte-wide registers that contain information con-
trolling the I/O_ pins, masking capabilities, and a con-
trol bit that determines which register is being
addressed. The 2-wire slave interface employs stan-
dard SMBus send-byte and receive-byte protocols.
SMBDATA and SMBCLK are Schmitt-triggered inputs
that can accommodate slower edges; however, the ris-
ing and falling edges should still be faster than 1µs and
300ns, respectively. Except for the stop and start con-
ditions, the SMBDATA input never transitions while
SMBCLK is high. A third interface line (SMBSUS) is
used to execute commands asynchronously from previ-
ously stored registers (see the section
SMBSUS
(Suspend-Mode) Input)
. This reduces the inherent
delay in a standard 2-wire serial interface. In the
receive-byte operation, the SMBus interface reads
back I/O states and thermal-shutdown status.
SMBus Addressing
Each slave device only responds to two addresses: its
own unique address and the alert response address. The
device’s unique address is determined at power-up
(Table 1). The three-level state of the address-select pin
(ADD) is only sampled upon power-on reset (POR) caus-
ing momentary input bias current of 100µA. The address
will not change until the part is power cycled. Stray
capacitance in excess of 50pF on the ADD pin when
floating may cause address recognition problems.
The normal start condition consists of a high-to-low
transition on SMBDATA while SMBCLK is high. After the
start condition, the master transmits a 7-bit address fol-
lowed by a single bit to determine whether the device is
sending or receiving (high = READ, low = WRITE). If
the address is correct, the MAX1661/MAX1662/
MAX1663 sends an acknowledgment pulse by pulling
SMBDATA low. Otherwise, the address is not recog-
nized and the device stays off the bus and waits until
another start condition occurs.
SMBus Send-Byte Commands
If the MAX1661/MAX1662/MAX1663 receives its correct
slave address (Table 1) followed by R/Wlow, it expects
to receive a byte of information. If the device detects a
start or stop condition prior to clocking in the byte of
data, it considers this an error condition and disregards
all of the data.
The MAX1661/MAX1662/MAX1663 generates a first
acknowledge after the write bit and another acknowledge
after the data. It executes the data byte at the rising edge
of SMBCLK following the second acknowledge, just prior
to the stop condition (Figure 2a). See Table 2 for send-
byte operations.
SMBSUS (Suspend-Mode) Input
The SMBus can write to either of the normal-data and
suspend-mode registers via the MSB (bit 7) of the
send-byte word (Table 2). The state of the SMBSUS
input selects which register contents (normal data or
suspend mode) are applied to the I/O_ pins. Driving
SMBSUS low selects the suspend-mode register, while
driving SMBSUS high selects the normal-data register.
This feature allows the system to select between two
different power-plane configurations asynchronously,
eliminating latencies introduced by the serial bus.
SMBSUS typically connects to the SUSTAT# signal in a
notebook computer.
SMBus Receive-Byte Operation
If the MAX1661/MAX1662/MAX1663 receives its correct
slave address, followed by R/Whigh, the device
becomes a slave transmitter (Figure 2b). After receiving
the address data, the device generates an acknowl-
edge during the acknowledge clock pulse and drives
SMBDATA in sync with SMBCLK. The SMB protocol
requires that the master terminate the read transmis-
sion by not acknowledging during the acknowledge bit
of SMBCLK. See Table 3 for receive-byte data format.
Figure 4 shows the complete receive-byte operation
timing diagram.
The logic states of the three I/O pins can be read over
the serial interface (Table 3). The state of the I/O pins is
sampled at the falling edge of the SMBCLK pulse that
follows the R/Wbit and acknowledge bit (Figure 4). The
states of the I/O bits in the status register reflect the
Table 1. SMBus Addresses
MAX1661/MAX1662/MAX1663
Serial-to-Parallel/Parallel-to-Serial Converters and
Load-Switch Contr ollers with SMBus Interface
6_______________________________________________________________________________________
ADD MAX1661 MAX1662 MAX1663
GND 0100000 0100001 0100010
High-Z
(floating) 0111100 0111101 0111110
VCC 1001000 1001001 1001010
Table 2. Format for Send-Byte Data
Send-Byte Format
MAX1661/MAX1662/MAX1663
Serial-to-Parallel/Parallel-to-Serial Converters and
Load-Switch Contr ollers with SMBus Interface
_______________________________________________________________________________________ 7
ADDRESS WRITE ACK DATA ACK
START
CONDITION 7 bits 1 bit
(low) 1 bit
(low) 8 bits 1 bit
(low) STOP
CONDITION
Shaded = Slave Transmission
SMBCLK
I/O
A B C D EF G H IJK
SMBDATA
tSU:STA tHD:STA
tLOW tHIGH
tSU:DAT tHD:DAT tSU:STO tBUF
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
E = SLAVE PULLS SMBDATA LINE LOW
LM
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO SLAVE (OP/SUS BIT)
H = LSB OF DATA CLOCKED INTO SLAVE
I = SLAVE PULLS SMBDATA LINE LOW
J = ACKNOWLEDGE CLOCKED INTO MASTER
K = ACKNOWLEDGE CLOCK PULSE
L = STOP CONDITION, DATA EXECUTED BY SLAVE
M = NEW START CONDITION
tP: I/O
Figure 2a. SMBus Send-Byte Timing Diagram and Format
BIT NAME POR STATE*
(MAX1661) POR STATE*
(MAX1662/MAX1663) FUNCTION
7 (MSB) SELECT N/A N/A Writes data to normal register when high; writes data to suspend
register when low.
6 Mask SS 1 1 Masks START-STOP software interrupts when high.
5 Mask 3 1 1 Masks I/O3 interrupts when high.
4 Mask 2 1 1 Masks I/O2 interrupts when high.
3 Mask 1 1 1 Masks I/O1 interrupts when high.
2 I/O3 0 1 I/O output enable bit. I/O3 is on when this bit is low (low state).
1 I/O2 0 1 I/O output enable bit. I/O2 is on when this bit is low (low state).
0 I/O1 0 1 I/O output enable bit. I/O1 is on when this bit is low (low state).
*
Note: POR states apply to both suspend- and normal-mode registers.
current I/O pin states (i.e., they are not latched). There
is a 15µs data-setup time requirement, due to the slow
level translators needed for high-voltage (28V) opera-
tion. Data-hold time is zero.
Interrupts
The MAX1661/MAX1662/MAX1663 generate interrupts
(hardware and software) whenever the logic states of
the I/O pins change or when thermal shutdown occurs.
Interrupts are signaled with the hardware ALERT pin
MAX1661/MAX1662/MAX1663
Serial-to-Parallel/Parallel-to-Serial Converters and
Load-Switch Contr ollers with SMBus Interface
8_______________________________________________________________________________________
and with the software START-STOP method (software
interrupts are discussed in the
START-STOP Software
Interrupt
section). The I/O interrupts can be masked
individually. In addition, the software START-STOP
interrupt can be masked independently. The power-on-
reset state masks the START-STOP interrupt, as well as
the individual I/O interrupts to the ALERT pin (Table 1).
The thermal-shutdown interrupt cannot be masked.
Note that excessive noise on the supply can cause
false interrupts (see
Applications Information
).
The MAX1661/MAX1662/MAX1663 are slave-only
devices that never initiate communications, except
when asserting an interrupt by forcing ALERT low, or
via the software START-STOP interrupt.
Alert Response Address (0001100)
The Alert Response (interrupt pointer) address pro-
vides quick fault identification for simple slave devices
that lack the complex, expensive logic needed to be a
bus master. When a slave device generates an inter-
Receive-Byte Format
ADDRESS READ ACK DATA ACK
START
CONDITION 7 bits 1 bit
(high) 1 bit
(low) 8 bits 1 bit
(high-Z) STOP
CONDITION
ACK = SMBDATA High
Shaded = Slave Transmission
SMBCLK
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
A B C D EF G H IJ
SMBDATA
tSU:STA tHD:STA
tLOW tHIGH
tSU:DAT tSU:STO tBUF
K
E = SLAVE PULLS SMBDATA LINE LOW
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO MASTER
H = LSB OF DATA CLOCKED INTO MASTER
I = ACKNOWLEDGE CLOCK PULSE
J = STOP CONDITION
K = NEW START CONDITION
Figure 2b. SMBus Receive-Byte Timing Diagram and Format
Table 3. Format for Receive-Byte Data
BIT NAME POR STATE FUNCTION LATCHED
7 (MSB) — 0 Not used —
6 — 0 Not used —
5 — 0 Not used —
4 — 0 Not used —
3 THSD N/A This bit indicates a thermal shutdown. Yes
2 Data 3 N/A This bit indicates the state of I/O3 (high or low). No
1Data 2 N/A This bit indicates the state of I/O2 (high or low). No
0Data 1 N/A This bit indicates the state of I/O1 (high or low). No
rupt, the host (Bus Master) interrogates the bus slave
devices via a special receive-byte operation that
includes the alert response address. The data returned
by this receive-byte operation is the address of the
offending slave device. The interrupt pointer address
can activate several different slave devices simultane-
ously. If more than one slave attempts to respond, bus
arbitration rules apply, with the lowest address code
going first. The other device(s) will not generate an
acknowledge and will continue to hold the ALERT line
low or repeat the START-STOP interrupt until serviced.
Clearing Interrupts via Alert Response
When a fault occurs, ALERT asserts and latches low. If
the fault is momentary and disappears before the
device is serviced, ALERT remains asserted. Normally,
the master sends out the Alert Response address fol-
lowed by a read bit (00011001). ALERT clears when
the device responds by successfully putting its
address on the bus. Reading the Alert Response
address is the
only
method for clearing hardware
and software interrupt latches. Clearing the interrupt
has no effect on the state of the status registers.
MAX1661/MAX1662/MAX1663
Serial-to-Parallel/Parallel-to-Serial Converters and
Load-Switch Contr ollers with SMBus Interface
_______________________________________________________________________________________ 9
tDV
tDV
SMBCLK
R/W BIT
CLOCKED
INTO SLAVE
ACKNOWLEDGE BIT
CLOCKED
INTO MASTER
MOST SIGNIFICANT
BIT OF DATA
CLOCKED INTO MASTER
SLAVE PULLING
SMBDATA LOW
SMBDATA • • •
• • •
Figure 3. SMB Serial-Interface Timing—Acknowledge and Data Valid
START
ADDRESS
MSB ADDRESS
LSB
SLAVE PULLS
SMBDATA LOW 4 ZEROS (NOT USED)
THSD DATA3 DATA2 DATA1
SLAVE
ACKNOWLEDGE
I/O
LATCHED
DATA
MSB DATA LSB
SMBCLK
SMBDATA
R/W BIT
tSU:I/O
(NOTE 1)
NOTE 1: THE SETUP AND HOLD TIMING LIMITS ARE ABSOLUTE LIMITS
(15µs MIN AND 0µs MIN, RESPECTIVELY) AND DO NOT NECESSARILY
CORRESPOND TO A PARTICULAR CLOCK EDGE.
(NOTE 1)
tHD:I/O
SLAVE
ACKNOWLEDGE
(ACK)
Figure 4. I/O Read Timing Diagram
MAX1661/MAX1662/MAX1663
START-STOP Software Interrupt
The START-STOP interrupt is a method for the slave
device to initiate a signal over the 2-wire interface with-
out the need for a third (interrupt) wire. A START-STOP
interrupt is a start condition followed by a stop condi-
tion; in other words, SMBDATA goes low and then high
with SMBCLK high (Figure 5 shows the START-STOP
interrupt and a subsequent Alert Response transmis-
sion used to clear the interrupt). The START-STOP
function can be disabled (masked) by setting the data
register mask SS (bit 6) high.
In order to avoid bus collisions, the START-STOP inter-
rupt will not occur when the bus is busy. If the device
begins a start condition simultaneously with another
transmitter on the bus, it recognizes the falling SMB-
CLK as a collision and re-transmits the interrupt when
the bus becomes available. Upon thermal shutdown or
a transition on an I/O line, the device issues only one
START-STOP interrupt, and won’ t repeat it unless there
has been a collision. However, thermal-shutdown faults,
not being edge triggered, may result in a continuous
stream of START-STOP bits.
Input/Output Pins
Each input/output (I/O) is protected by an internal
20mA (typical) current-limit circuit. The I/O current limit
depends on the supply voltage and the voltage applied
to the I/O pins (see
Typical Operating Characteristics
).
The typical I/O bias current is 0.5µA to VI/O_ = 28V.
The ability of the I/Os to sink current depends on VCC
as well as the voltage on the I/O. Typical pull-down on-
resistance at VCC = 2.7V and 5.5V is 106Ωand 66Ω,
respectively. I/O source and sink capability can affect
the rise and fall times of external power MOSFETs com-
monly used in power-switching applications. Other fac-
tors include the VGS, the input capacitance of the MOS-
FET, and the pull-up resistor value used in the circuit.
Typical MOSFET gate capacitance ranges from 150pF
to 2000pF. Increasing the RC time constant slows down
the MOSFET’s response, but provides for a smoother
transition.
Power-On Reset
The power-on reset circuit keeps the external MOSFETs
off during a power-up sequence. When the supply volt-
age falls below the power-on reset threshold voltage,
the MAX1662/MAX1663’s outputs reset to a high-
impedance state, and the MAX1661’s outputs reset to a
low state. During the initial power-up sequence, as VCC
increases, the ALERT pin goes low and then high,
which indicates the device is powered on. The time
between the low and high state on ALERT is the power-
on delay time. Below VCC = 0.8V (typical) the POR
states can’t be enforced, and the I/O pins of all ver-
sions exhibit increasingly weak pull-down current capa-
bility, eventually becoming high impedance.
Thermal Shutdown
These devices have internal thermal-shutdown circuitry
that turns off all output stages (I/O pins) when the junc-
tion temperature exceeds +140°C typical. Thermal
shutdown only occurs during an overload condition on
the I/O pins. The device cycles between thermal shut-
down and the overcurrent condition until the overload
condition is removed. This could cause a sustained
START-STOP interrupt and, in the extreme case, tie up
the master controller. However, the device asserts
ALERT low, indicating this fault status.
Serial-to-Parallel/Parallel-to-Serial Converters and
Load-Switch Contr ollers with SMBus Interface
10 ______________________________________________________________________________________
START STOP
DATA LINE HELD
LOW BY SLAVE
SMBCLK
SMBDATA
tLOW:SS
tBUF
START-STOP INTERRUPT ALERT RESPONSE ADDRESS
(0001100) ACTUAL SLAVE ADDRESS
(0100000 IN THIS EXAMPLE)
DUMMY BIT (1)
ALERT
SLAVE
ACKNOWLEDGE
(ACK)
Figure 5. START-STOP Software Interrupt Timing Diagram and Alert Response
__________Applications Information
Bypassing and Grounding Considerations
Voltage transients exceeding 500mV at 25V/µs may
trigger a false interrupt and thermal-shutdown indica-
tion. If large VCC transients are expected, add a 100Ω
resistor in series with VCC. Retain the 0.1µF capacitor
from VCC to GND to act as a filter.
P-Channel/N-Channel Load Switch
with Controlled Turn-On
For a more controlled voltage-switching application,
add a series resistor to slow the switch turn-on time.
The external MOSFET gate has typical capacitance of
150pF to 2000pF, but an optional external capaci-
tance can be added to further slow the switching time
(Figure 6).
MAX1661/MAX1662/MAX1663
Serial-to-Parallel/Parallel-to-Serial Converters and
Load-Switch Contr ollers with SMBus Interface
______________________________________________________________________________________ 11
MAX1662
MAX1663
I/O1
TO/FROM
HOST
+5V
VCC
I/O3
I/O2
GND LOAD1 LOAD2 LOAD3
ALERT
0.1µF
0.01µF* 0.01µF*
0.01µF*0.01µF* 0.01µF*
0.01µF*
IRF7406
IRF7413
IRF7406
IRF7413
IRF7406
IRF7413
+12V
10k 10k 10k
SMBCLK
SMBDATA
SMBSUS
ADD
MAX1661
I/O1
TO/FROM
HOST
+5V
VCC
I/O3
I/O2
GND LOAD1 LOAD2 LOAD3
ALERT
0.1µF
10k
100Ω*
100Ω*
10k
10k
10k
10k
10k
10k 10k 10k
200k 200k 200k
200k 200k 200k
SMBCLK
SMBDATA
SMBSUS
ADD
*OPTIONAL
Figure 6. Load Switch with Controlled Turn-On
MAX1661/MAX1662/MAX1663
Battery Switch with
Back-to-Back MOSFETs
For battery-operated applications, use back-to-back
MOSFETs to keep reverse currents from flowing from
the load to the supply (Figure 7). This protects the bat-
tery from potential damage, and isolates the load from
the power source.
LED Drivers
A MAX1661/MAX1662/MAX1663 can be used as a pro-
grammable LED driver (Figure 8). With their low quies-
cent current, these devices are ideal for use as
indicator light drivers on the front panel of a notebook
computer.
Serial-to-Parallel/Parallel-to-Serial Converters and
Load-Switch Contr ollers with SMBus Interface
12 ______________________________________________________________________________________
MAX1662
MAX1663
I/O1
TO/FROM
HOST
+5V +3.3V TO +28V
P
P
VCC
I/O3
I/O2
GND
LOAD
ALERT
0.1µF
100k
IRF7406
IRF7406
SMBCLK
SMBDATA
SMBSUS
ADD
100Ω*
10k 10k 10k
75k**
NOTE: I/O2 AND I/O3 CAN BE CONFIGURED SIMILARLY.
*OPTIONAL
**75kΩ RESISTOR FOR VOLTAGES GREATER THAN +12V.
1M
Figure 7. Battery Switch with Back-to-Back MOSFETs
MAX1661
MAX1662
MAX1663
I/O1
TO/FROM
HOST
+5V
VCC
I/O3
I/O2
GND
ALERT
0.1µF
1k 1k 1k
SMBCLK
SMBDATA
SMBSUS
ADD
100Ω*
*OPTIONAL
10k 10k
Figure 8. LED Drivers
Mechanical Switch Monitor
The ability of the MAX1661/MAX1662/MAX1663 to read
back the logic state of the I/Os makes them suitable for
checking system status. They can be used as an
“open-lid indicator”, sensing a change in the I/O and
sending an interrupt to the master to indicate a change
in status (Figure 9). The same can be done to detect a
chassis intrusion.
Simple High-Voltage Switch
For applications requiring a higher voltage, use a sim-
ple resistive divider to protect the gate from breakdown
yet allow the MOSFETs to handle higher-voltage appli-
cations (Figure 10).
MAX1661/MAX1662/MAX1663
Serial-to-Parallel/Parallel-to-Serial Converters and
Load-Switch Contr ollers with SMBus Interface
______________________________________________________________________________________ 13
MAX1661
MAX1662
MAX1663
I/O1
TO/FROM
HOST
+5V
VCC
I/O3
I/O2
GND
ALERT
0.1µF
100k 100k 100k
SMBCLK
SMBDATA
SMBSUS
ADD
100Ω*
*OPTIONAL
10k 10k 10k
Figure 9. Open-Lid Detect or Chassis Intrusion Detector
MAX1662
MAX1663
I/O1
TO/FROM
HOST
+5V
VCC
I/O3
I/O2
GND LOAD
ALERT
0.1µF
0.01µF*
IRF7406
VIN = 10V TO 28V
200k
SMBCLK
SMBDATA
SMBSUS
ADD
100Ω*
*OPTIONAL
I/O2 AND I/O3 CAN BE CONFIGURED SIMILIARLY.
10k 10k 10k
200k
Figure 10. Simple High-Voltage Switch
___________________Chip Information
TRANSISTOR COUNT: 3334
SUBSTRATE CONNECTED TO GND
MAX1661/MAX1662/MAX1663
Serial-to-Parallel/Parallel-to-Serial Converters and
Load-Switch Contr ollers with SMBus Interface
14 ______________________________________________________________________________________
MAX1662
MAX1663
I/O1
SMBUS
TO/
FROM
HOST
+2.7V
TO
+5.5V VCC
I/O3
I/O2
GND LOAD1 LOAD2 LOAD3
ALERT
0.1µF
P-CH
N-CH
+12V
100k 100k 100k
SMBCLK
SMBDATA
SMBSUS
ADD
MAX1661
I/O1
SMBUS
TO/
FROM
HOST
+2.7V
TO
+5.5V VCC
I/O3
I/O2
GND LOAD1 LOAD2 LOAD3
ALERT
0.1µF
100k 100k 100k
SMBCLK
SMBDATA
SMBSUS
ADD
___________________________________________________Typical Operating Circuit
10LUMAXB.EPS
MAX1661/MAX1662/MAX1663
Serial-to-Parallel/Parallel-to-Serial Converters and
Load-Switch Contr ollers with SMBus Interface
______________________________________________________________________________________ 15
________________________________________________________Package Information
MAX1661/MAX1662/MAX1663
Serial-to-Parallel/Parallel-to-Serial Converters and
Load-Switch Contr ollers with SMBus Interface
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
NOTES
