QS5920A 3.3V SYNC DRAM PLL Clock Driver Q QS5920A QUALITY SEMICONDUCTOR, INC. FEATURES/BENEFITS DESCRIPTION * * * * The QS5920A is a high-performance, low skew, low jitter, multiple output phase-locked loop clock driver which is suitable for PC-100 spread spectrum clock systems. It provides precise phase and frequency alignment of its clock outputs to an externally applied clock input signal. The QS5920A has been specially designed to interface with high speed SDRAM applications in the range of 33MHz to 100MHz and includes an internal RC filter which provides excellent jitter characteristics and eliminates the need for external components. The synchronous output enable (sOE) control sets all outputs except QFB (which may be used to maintain phase lock) LOW on a subsequent negative clock transition: partial output clock pulses are not produced. * * * * * * * * Intel PC100/Spread Spectrum compliant 11 outputs Balanced Drive Outputs 12mA Synchronous output enable (sOE) control for SDRAM power down mode External feedback, internal loop filter Low skew guaranteed between outputs Supports 33MHz to 100MHz SDRAMs JEDEC compatible LVTTL 3.0V to 3.6V supply voltage Industrial temperature range Inputs are 5V tolerant Available in 16- and 24-pin QSOP packages y n pa m o C Figure 1. Logic Block Diagram n a w FREQ_SEL TEST No QFB Q0 Q1 FB Q2 PLL CLKIN Q3 OUTPUT LOGIC Q4 Q5 Q6 Q7 Q8 Q9 sOE MDSC-00036-03 SEPTEMBER 22, 1998 QUALITY SEMICONDUCTOR, INC. 1 4 QS5920A Figure 2. Pin Configuration (All Pins Top View) 16-Pin QSOP CLKIN VCCQ FREQ_SEL VCC Q3 Q2 GND QFB 1 2 3 4 5 6 7 8 24Pin QSOP GNDQ TEST sOE VCC Q0 Q1 GND FB 16 15 14 13 12 11 10 9 QS5920A-04 CLKIN VCCQ FREQ_SEL Q9 Q8 GND VCC Q7 Q6 Q5 QFB FB 1 2 3 4 5 6 7 8 9 10 11 12 GNDQ TEST sOE Q0 GND VCC Q1 Q2 Q3 Q4 GND VCC 24 23 22 21 20 19 18 17 16 15 14 13 y n pa Table 1. Pin Description Pin Name I/O CLKIN I Clock input Q0..Q9 O Clock outputs FB I PLL feedback input normally connected to QFB by user. May be connected to any output if sOE is strapped low. QFB O Dedicated clock output for the FB pin (non-disable) sOE I Synchronous output enable. Asserted LOW for normal operation. When asserted HIGH, clock outputs (except QFB) are forced LOW. I When LOW, PLL is in normal operation. When HIGH, it disables PLL and opens DC bypass. CLKIN goes to all outputs. I VCO frequency select. For optimizing the VCO operating frequency. Set LOW for input frequencies within 33MHz to 75MHz, and HIGH for 66MHz to 100MHz. TEST m o C n a w No FREQ_SEL(1) Functional Description VCC -- Power supply for output buffers VCCQ -- Power supply (quiet) for PLL GND -- Ground supply for output buffers GNDQ -- Ground supply (quiet) for PLL Note: 1. If this input is switched, the function and timing of the outputs may glitch, and the PLL may require an additional tLOCK time before all datasheet limits are achieved. Table 2. Absolute Maximum Ratings Supply Voltage to Ground .................................. -0.5V to 7.0V DC Output Voltage VOUT .......................... -0.5V to VCC + 0.5V DC Input Voltage VIN .......................................... -0.5V to 7.0V DC Input Diode Current with VI < 0 ............................... -20mA Maximum Power Dissipation At TA = 85C, .................... 0.55W TSTG Storage Temperature ................................ -65 to 150C 2 Note: Stresses greater than those listed under absolute maximum ratings may cause permanent damage to QSI devices that result in functional or reliability type failures. QUALITY SEMICONDUCTOR, INC. MDSC-00036-03 SEPTEMBER 22, 1998 QS5920A Table 3. Capacitance TA = 25C, f = 1MHz, VIN = 0V Pins CIN QSOP Typ Max 5 Units 7 pF Note: Capacitance is characterized but not tested. Table 4. Recommended Operating Conditions Symbol Parameter Min Max Unit VCC Power Supply Voltage 3.0 3.6 V VIN Input Voltage 0 VCC V TA Ambient Operating Temperature -40 85 C y n pa Table 5. DC Electrical Characteristics Over Operating Range Symbol Parameter Test Condition VIH Input HIGH Voltage Guaranteed Logic HIGH for inputs VIL Input LOW Voltage Guaranteed Logic LOW for inputs VIC Clamp Diode Voltage VCC = Min., IIN = -18mA VOH Output HIGH Voltage (Q0:9, QFB) VCC = Min., IOH = -12mA VCC = Min., IOH = -8mA VCC = Min., IOH = -100A VOL Output LOW Voltage (Q0:9, QFB) VCC = Min., IOL = 12mA VCC = Min., IOL = 8mA VCC = Min., IOL = 100A Input Leakage Current VCC = Max., 0 VIN VCC w o N IIN an Min m o C 2.0 Typ(1) -0.7 Max V 0.8 V -1.2 V 2.0 2.4 2.8 4 Unit V 0.5 0.4 0.2 V 1 A Typ Max Unit Note: 1. Typical values indicate VCC = 3.3V and TA = 25C. Table 6. Power Supply Characteristics Symbol Parameter Test Conditions ICCQ Quiescent Power Supply Current VCC = Max., TEST = High, CLKIN = Low sOE = Low, All outputs unloaded 15 30 mA ICC Power Supply Current Per Input HIGH(1) VCC = Max., VIN = 3.0V 1.0 30 A ICCD Dynamic Power Supply Current Per Output(1) VCC = Max., CL = 0pF 55 90 A/ MHz IC Total Power Supply Current(1) VCC = 3.3V, fCLKIN = 50MHz(2) VCC = 3.3V, fCLKIN = 100MHz(2) 70 mA 130 Notes: 1. Guaranteed by characterization but not production tested. 2. For 11 outputs each loaded with 15pF. MDSC-00036-03 SEPTEMBER 22, 1998 QUALITY SEMICONDUCTOR, INC. 3 QS5920A Table 7. Switching Characteristics Over Operating Range Symbol Description tPWC Input clock pulse, high or low fCLKIN Input frequency (1) tPD CLKIN input to FB delay, 100MHz tSK1 Output - Output skew, all outputs, same transition,100MHz (1) Min Max Unit 2.5 -- ns 33 100 MHz -250 250 ps -- 200 ps -100 100 ps -200 200 ps 45 55 % (1,5) tJ Cycle to cycle jitter, 100MHz (1) tJ (SSC) Spread Spectrum Clock induced skew, 100MHz (1,3) tPW Output duty cycle distortion tOPW Output pulse width distortion tLOCK CLKIN to phase lock tR,tF Output rise and fall times (0.8V to 2.0V) tDEV Skew between two outputs of different devices (1,2) TCYCLE/2 - 0.65 TCYCLE/2 + 0.65 (1,2) ns 0.1 0.5 ms -- 1.6 ns -- 1.00 ns (1) (1,4) Notes: 1. This parameter is guaranteed by design and verified during production by statistical correlation. 2. Output signal is nominally 50% duty cycle: maximum error is 5% of the period or 0.65ns, whichever is the greater. 3. Spread spectrum clock induced skew is measured under PC-100 conditions of 30kHz to 50kHz modulation with peak deviation of -0.5%. 4. tDEV applies to any device operating under the same conditions (VCC, ambient temperature, package, air flow, etc.) 5. All outputs with 15pF Load. y n pa m o C Figure 3. Waveforms 1ns 3.0V 2.0V Vth = 1.5V 0.8V n a w 0V tR 2.0V 1.5V 0.8V tPWC No 1ns LVTTL Input Test Waveform tF TCYCLE LVTTL Output Waveform Figure 4. AC Timing Diagram CLKIN tPD tPD FB tSK1 tSK1 Q0-Q9 tJ Qn 4 QUALITY SEMICONDUCTOR, INC. MDSC-00036-03 SEPTEMBER 22, 1998 QS5920A Ordering Information QS5 920A Q Clock Management Product Prefix (QS5) Package Q QSOP Package Q QSOP Part Number QS5 920A-04 Q Clock Management Product Prefix (QS5) Part Number y n pa 4 m o C n a w No MDSC-00036-03 SEPTEMBER 22, 1998 QUALITY SEMICONDUCTOR, INC. 5