MDSC-00036-03 QUALITY SEMICONDUCTOR, INC. 1
SEPTEMBER 22, 1998
QS5920A
4
Now an Company
FEATURES/BENEFITS
• Intel PC100/Spread Spectrum compliant
• 11 outputs
• Balanced Drive Outputs ±12mA
• Synchronous output enable (sOE) control for
SDRAM power down mode
• External feedback, internal loop filter
• Low skew guaranteed between outputs
• Supports 33MHz to 100MHz SDRAMs
• JEDEC compatible LVTTL
• 3.0V to 3.6V supply voltage
• Industrial temperature range
• Inputs are 5V tolerant
• Available in 16- and 24-pin QSOP packages
DESCRIPTION
The QS5920A is a high-performance, low skew, low
jitter, multiple output phase-locked loop clock driver
which is suitable for PC-100 spread spectrum clock
systems. It provides precise phase and frequency
alignment of its clock outputs to an externally applied
clock input signal. The QS5920A has been specially
designed to interface with high speed SDRAM
applications in the range of 33MHz to 100MHz and
includes an internal RC filter which provides
excellent jitter characteristics and eliminates the
need for external components. The synchronous
output enable (sOE) control sets all outputs except
QFB (which may be used to maintain phase lock)
LOW on a subsequent negative clock transition:
partial output clock pulses are not produced.
Figure 1. Logic Block Diagram
FB
CLKIN
FREQ_SEL TEST
QFB
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
sOE
PLL
OUTPUT
LOGIC
3.3V SYNC DRAM
PLL Clock Driver
QS5920A
Q
Q
UALITY
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EMICONDUCTOR,
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QS5920A
2QUALITY SEMICONDUCTOR, INC. MDSC-00036-03
SEPTEMBER 22, 1998
Now an Company
Pin Name I/O Functional Description
CLKIN I Clock input
Q0..Q9 O Clock outputs
FB I PLL feedback input normally connected to QFB by user. May be connected
to any output if sOE is strapped low.
QFB O Dedicated clock output for the FB pin (non-disable)
sOE I Synchronous output enable. Asserted LOW for normal operation. When
asserted HIGH, clock outputs (except QFB) are forced LOW.
TEST I When LOW, PLL is in normal operation. When HIGH, it disables PLL and
opens DC bypass. CLKIN goes to all outputs.
FREQ_SEL(1) I VCO frequency select. For optimizing the VCO operating frequency. Set
LOW for input frequencies within 33MHz to 75MHz, and HIGH for 66MHz
to 100MHz.
VCC — Power supply for output buffers
VCCQ — Power supply (quiet) for PLL
GND — Ground supply for output buffers
GNDQ — Ground supply (quiet) for PLL
Table 1. Pin Description
Supply Voltage to Ground .................................. –0.5V to 7.0V
DC Output Voltage VOUT .......................... –0.5V to VCC + 0.5V
DC Input Voltage VIN .......................................... –0.5V to 7.0V
DC Input Diode Current with VI < 0 ...............................–20mA
Maximum Power Dissipation At TA = 85°C,....................0.55W
TSTG Storage Temperature................................ –65° to 150 °C
Table 2. Absolute Maximum Ratings
Note:
1. If this input is switched, the function and timing of the outputs may glitch, and the PLL may require an
additional tLOCK time before all datasheet limits are achieved.
Figure 2. Pin Configuration (All Pins Top View)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLKIN
V
CCQ
FREQ_SEL
V
CC
Q3
Q2
GND
QFB
GNDQ
TEST
sOE
V
CC
Q0
Q1
GND
FB
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLKIN
V
CCQ
FREQ_SEL
Q9
Q8
GND
V
CC
Q7
Q6
Q5
QFB
FB
GNDQ
TEST
sOE
Q0
GND
V
CC
Q1
Q2
Q3
Q4
GND
V
CC
16-Pin QSOP
Note: Stresses greater
than those listed under
absolute maximum ratings
may cause permanent
damage to QSI devices
that result in functional or
reliability type failures.
24Pin QSOP
QS5920A-04
MDSC-00036-03 QUALITY SEMICONDUCTOR, INC. 3
SEPTEMBER 22, 1998
QS5920A
4
Now an Company
Symbol Parameter Test Conditions Typ Max Unit
ICCQ Quiescent Power VCC = Max., TEST = High, CLKIN = Low 15 30 mA
Supply Current sOE = Low, All outputs unloaded
∆ICC Power Supply Current VCC = Max., VIN = 3.0V 1.0 30 µA
Per Input HIGH(1)
ICCD Dynamic Power Supply VCC = Max., CL = 0pF 55 90 µA/
Current Per Output(1) MHz
ICTotal Power Supply Current(1) VCC = 3.3V, fCLKIN = 50MHz(2) 70 mA
VCC = 3.3V, fCLKIN = 100MHz(2) 130
Symbol Parameter Test Condition Min Typ(1) Max Unit
VIH Input HIGH Voltage Guaranteed Logic HIGH for inputs 2.0 V
VIL Input LOW Voltage Guaranteed Logic LOW for inputs 0.8 V
VIC Clamp Diode Voltage VCC = Min., IIN = –18mA –0.7 –1.2 V
VOH Output HIGH Voltage VCC = Min., IOH = –12mA 2.0 V
(Q0:9, QFB) VCC = Min., IOH = –8mA 2.4
VCC = Min., IOH = –100µA 2.8
VOL Output LOW Voltage VCC = Min., IOL = 12mA 0.5 V
(Q0:9, QFB) VCC = Min., IOL = 8mA 0.4
VCC = Min., IOL = 100µA 0.2
IINInput Leakage Current VCC = Max., 0 ≤ VIN ≤ VCC 1µA
Table 5. DC Electrical Characteristics Over Operating Range
Note:
1. Typical values indicate VCC = 3.3V and TA = 25°C.
Table 6. Power Supply Characteristics
Notes:
1. Guaranteed by characterization but not production tested.
2. For 11 outputs each loaded with 15pF.
Symbol Parameter Min Max Unit
VCC Power Supply Voltage 3.0 3.6 V
VIN Input Voltage 0 VCC V
TAAmbient Operating Temperature –40 85 °C
Table 4. Recommended Operating Conditions
Table 3. Capacitance
TA = 25°C, f = 1MHz, VIN = 0V
QSOP
Pins Typ Max Units
CIN 57pF
Note: Capacitance is characterized but not tested.
QS5920A
4QUALITY SEMICONDUCTOR, INC. MDSC-00036-03
SEPTEMBER 22, 1998
Now an Company
Table 7. Switching Characteristics Over Operating Range
Notes:
1. This parameter is guaranteed by design and verified during production by statistical correlation.
2. Output signal is nominally 50% duty cycle: maximum error is ±5% of the period or 0.65ns, whichever is the greater.
3. Spread spectrum clock induced skew is measured under PC-100 conditions of 30kHz to 50kHz modulation with
peak deviation of –0.5%.
4. tDEV applies to any device operating under the same conditions (VCC, ambient temperature, package, air flow, etc.)
5. All outputs with 15pF Load.
Symbol Description Min Max Unit
tPWC Input clock pulse, high or low(1) 2.5 — ns
fCLKIN Input frequency 33 100 MHz
tPD CLKIN input to FB delay, 100MHz(1) –250 250 ps
tSK1 Output - Output skew, all outputs, same transition,100MHz(1,5) — 200 ps
tJCycle to cycle jitter, 100MHz(1) –100 100 ps
tJ (SSC) Spread Spectrum Clock induced skew, 100MHz(1,3) –200 200 ps
tPW Output duty cycle distortion(1,2) 45 55 %
tOPW Output pulse width distortion(1,2) TCYCLE/2 – 0.65 TCYCLE/2 + 0.65 ns
tLOCK CLKIN to phase lock 0.1 0.5 ms
tR,tFOutput rise and fall times (0.8V to 2.0V)(1) — 1.6 ns
tDEV Skew between two outputs of different devices(1,4) — 1.00 ns
Figure 3. Waveforms
Figure 4. AC Timing Diagram
CLKIN
FB
Q0-Q9
Qn
t
PD
t
PD
t
SK1
t
SK1
t
J
≤1ns ≤1ns t
R
t
F
T
CYCLE
2.0V
0.8V
3.0V
0V
V
th
= 1.5V 2.0V
0.8V
1.5V
LVTTL Input Test Waveform LVTTL Output Waveform
t
PWC
MDSC-00036-03 QUALITY SEMICONDUCTOR, INC. 5
SEPTEMBER 22, 1998
QS5920A
4
Now an Company
QS5 920A-04 Q
Ordering Information
QS5 920A Q
Clock Management
Product Prefix (QS5)
Part Number
Package
Q QSOP
Clock Management
Product Prefix (QS5)
Part Number
Package
Q QSOP
