1
IQE006NE2LM5CG
Rev.2.0,2019-12-06Final Data Sheet
1
5
234
6
7
8
9
PG-TTFN-9-1
Drain
Pin 5-8
Gate
Pin 9
Source
Pin 1-4
MOSFET
OptiMOSTM5Power-Transistor,25V
Features
•Verylowon-resistanceRDS(on)
•100%avalanchetested
•Superiorthermalresistance
•N-channel,logiclevel
•Pb-freeleadplating;RoHScompliant
•Halogen-freeaccordingtoIEC61249-2-21
Productvalidation
FullyqualifiedaccordingtoJEDECforIndustrialApplications
Table1KeyPerformanceParameters
Parameter Value Unit
VDS 25 V
RDS(on),max 0.65 mΩ
ID298 A
Qoss 41 nC
QG(0V..4.5V) 29 nC
Type/OrderingCode Package Marking RelatedLinks
IQE006NE2LM5CG PG-TTFN-9-1 006E2LC -
2
OptiMOSTM5Power-Transistor,25V
IQE006NE2LM5CG
Rev.2.0,2019-12-06Final Data Sheet
TableofContents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
OptiMOSTM5Power-Transistor,25V
IQE006NE2LM5CG
Rev.2.0,2019-12-06Final Data Sheet
1Maximumratings
atTA=25°C,unlessotherwisespecified
Table2Maximumratings
Values
Min. Typ. Max.
Parameter Symbol Unit Note/TestCondition
Continuous drain current ID
-
-
-
-
-
-
298
188
41
A
VGS=10V,TC=25°C
VGS=10V,TC=100°C
VGS=4.5V,TA=25°C,
RTHJA=60°C/W1)
Pulsed drain current2) ID,pulse - - 1192 A TA=25°C
Avalanche energy, single pulse3) EAS - - 140 mJ ID=20A,RGS=25Ω
Gate source voltage VGS -16 - 16 V -
Power dissipation Ptot -
-
-
-
89
2.1 WTC=25°C
TA=25°C,RTHJA=60°C/W1)
Operating and storage temperature Tj,Tstg -55 - 150 °C IEC climatic category; DIN IEC 68-1:
55/150/56
2Thermalcharacteristics
Table3Thermalcharacteristics
Values
Min. Typ. Max.
Parameter Symbol Unit Note/TestCondition
Thermal resistance, junction - case RthJC - - 1.4 °C/W -
Device on PCB,
6 cm² cooling area RthJA - - 60 °C/W -
1) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
2) See Diagram 3 for more detailed information
3) See Diagram 13 for more detailed information
4
OptiMOSTM5Power-Transistor,25V
IQE006NE2LM5CG
Rev.2.0,2019-12-06Final Data Sheet
3Electricalcharacteristics
atTj=25°C,unlessotherwisespecified
Table4Staticcharacteristics
Values
Min. Typ. Max.
Parameter Symbol Unit Note/TestCondition
Drain-source breakdown voltage V(BR)DSS 25 - - V VGS=0V,ID=1mA
Gate threshold voltage VGS(th) 1.2 1.6 2 V VDS=VGS,ID=250µA
Zero gate voltage drain current IDSS -
-
0.1
10
1
100 µA VDS=20V,VGS=0V,Tj=25°C
VDS=20V,VGS=0V,Tj=125°C
Gate-source leakage current IGSS - 10 100 nA VGS=16V,VDS=0V
Drain-source on-state resistance RDS(on) -
-
0.50
0.65
0.65
0.80 mΩVGS=10V,ID=20A
VGS=4.5V,ID=20A
Gate resistance1) RG- 0.7 1.2 Ω-
Transconductance gfs - 220 - S |VDS|≥2|ID|RDS(on)max,ID=20A
Table5Dynamiccharacteristics
Values
Min. Typ. Max.
Parameter Symbol Unit Note/TestCondition
Input capacitance1) Ciss - 4100 5453 pF VGS=0V,VDS=12V,f=1MHz
Output capacitance1) Coss - 1700 2261 pF VGS=0V,VDS=12V,f=1MHz
Reverse transfer capacitance1) Crss - 130 195 pF VGS=0V,VDS=12V,f=1MHz
Turn-on delay time td(on) - 5.3 - ns VDD=12V,VGS=4.5V,ID=20A,
RG,ext=1.6Ω
Rise time tr- 2.6 - ns VDD=12V,VGS=4.5V,ID=20A,
RG,ext=1.6Ω
Turn-off delay time td(off) - 27.0 - ns VDD=12V,VGS=4.5V,ID=20A,
RG,ext=1.6Ω
Fall time tf- 5.3 - ns VDD=12V,VGS=4.5V,ID=20A,
RG,ext=1.6Ω
Table6Gatechargecharacteristics2)
Values
Min. Typ. Max.
Parameter Symbol Unit Note/TestCondition
Gate to source charge Qgs - 9.2 - nC VDD=12V,ID=20A,VGS=0to4.5V
Gate charge at threshold Qg(th) - 5.8 - nC VDD=12V,ID=20A,VGS=0to4.5V
Gate to drain charge1) Qgd - 5.6 8.4 nC VDD=12V,ID=20A,VGS=0to4.5V
Switching charge Qsw - 9.0 - nC VDD=12V,ID=20A,VGS=0to4.5V
Gate charge total1) Qg- 28.5 37.9 nC VDD=12V,ID=20A,VGS=0to4.5V
Gate plateau voltage Vplateau - 2.2 - V VDD=12V,ID=20A,VGS=0to4.5V
Gate charge total1) Qg- 61.7 82.1 nC VDD=12V,ID=20A,VGS=0to10V
Gate charge total, sync. FET Qg(sync) - 60.4 - nC VDS=0.1V,VGS=0to10V
Output charge Qoss - 41.3 - nC VDD=12V,VGS=0V
1) Defined by design. Not subject to production test.
2) See ″Gate charge waveforms″ for parameter definition
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OptiMOSTM5Power-Transistor,25V
IQE006NE2LM5CG
Rev.2.0,2019-12-06Final Data Sheet
Table7Reversediode
Values
Min. Typ. Max.
Parameter Symbol Unit Note/TestCondition
Diode continuous forward current IS- - 83 A TC=25°C
Diode pulse current IS,pulse - - 1192 A TC=25°C
Diode forward voltage VSD - 0.75 1 V VGS=0V,IF=20A,Tj=25°C
Reverse recovery charge Qrr - 25 - nC VR=12V,IF=20A,diF/dt=100A/µs
6
OptiMOSTM5Power-Transistor,25V
IQE006NE2LM5CG
Rev.2.0,2019-12-06Final Data Sheet
4Electricalcharacteristicsdiagrams
Diagram1:Powerdissipation
TC[°C]
Ptot[W]
0 20 40 60 80 100 120 140 160
0
20
40
60
80
100
Ptot=f(TC)
Diagram2:Draincurrent
TC[°C]
ID[A]
0 20 40 60 80 100 120 140 160
0
50
100
150
200
250
300
350
ID=f(TC);VGS≥10V
Diagram3:Safeoperatingarea
VDS[V]
ID[A]
10-1 100101102
10-2
10-1
100
101
102
103
104
1 µs
10 µs
100 µs
1 ms
10 ms
DC
ID=f(VDS);TC=25°C;D=0;parameter:tp
Diagram4:Max.transientthermalimpedance
tp[s]
ZthJC[K/W]
10-5 10-4 10-3 10-2 10-1 100
10-2
10-1
100
101
single pulse
0.01
0.02
0.05
0.1
0.2
0.5
ZthJC=f(tp);parameter:D=tp/T
7
OptiMOSTM5Power-Transistor,25V
IQE006NE2LM5CG
Rev.2.0,2019-12-06Final Data Sheet
Diagram5:Typ.outputcharacteristics
VDS[V]
ID[A]
0.0 0.5 1.0 1.5 2.0 2.5 3.0
0
200
400
600
800
1000
1200
4 V
4.5 V
5 V
10 V
3.5 V
3 V
2.8 V
ID=f(VDS),Tj=25°C;parameter:VGS
Diagram6:Typ.drain-sourceonresistance
ID[A]
RDS(on)[mΩ]
0 100 200 300 400 500 600
0.00
0.25
0.50
0.75
1.00
1.25
1.50
2.8 V
3 V
3.5 V
4 V
4.5 V
5 V
10 V
RDS(on)=f(ID),Tj=25°C;parameter:VGS
Diagram7:Typ.transfercharacteristics
VGS[V]
ID[A]
012345
0
200
400
600
800
1000
1200
150 °C
25 °C
ID=f(VGS),|VDS|>2|ID|RDS(on)max;parameter:Tj
Diagram8:Typ.drain-sourceonresistance
VGS[V]
RDS(on)[mΩ]
0246810
0.00
0.25
0.50
0.75
1.00
1.25
1.50
150 °C
25 °C
RDS(on)=f(VGS),ID=20A;parameter:Tj
8
OptiMOSTM5Power-Transistor,25V
IQE006NE2LM5CG
Rev.2.0,2019-12-06Final Data Sheet
Diagram9:Normalizeddrain-sourceonresistance
Tj[°C]
RDS(on)(normalizedto25°C)
-80 -40 0 40 80 120 160
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
RDS(on)=f(Tj),ID=20A,VGS=10V
Diagram10:Typ.gatethresholdvoltage
Tj[°C]
VGS(th)[V]
-80 -40 0 40 80 120 160
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2500 µA
250 µA
VGS(th=f(Tj),VGS=VDS;parameter:ID
Diagram11:Typ.capacitances
VDS[V]
C[pF]
0 5 10 15 20 25
101
102
103
104
Ciss
Coss
Crss
C=f(VDS);VGS=0V;f=1MHz
Diagram12:Forwardcharacteristicsofreversediode
VSD[V]
IF[A]
0.00 0.25 0.50 0.75 1.00 1.25 1.50
101
102
103
104
25 °C
25 °C, max
150 °C
150 °C, max
IF=f(VSD);parameter:Tj
9
OptiMOSTM5Power-Transistor,25V
IQE006NE2LM5CG
Rev.2.0,2019-12-06Final Data Sheet
Diagram13:Avalanchecharacteristics
tAV[µs]
IAV[A]
100101102103
100
101
102
25 °C
100 °C
125 °C
IAS=f(tAV);RGS=25Ω;parameter:Tj,start
Diagram14:Typ.gatecharge
Qgate[nC]
VGS[V]
0 10 20 30 40 50 60 70
0
2
4
6
8
10
5 V
12 V
20 V
VGS=f(Qgate),ID=20Apulsed,Tj=25°C;parameter:VDD
Diagram15:Drain-sourcebreakdownvoltage
Tj[°C]
VBR(DSS)[V]
-80 -40 0 40 80 120 160
23
24
25
26
27
28
VBR(DSS)=f(Tj);ID=1mA
Diagram Gate charge waveforms
10
OptiMOSTM5Power-Transistor,25V
IQE006NE2LM5CG
Rev.2.0,2019-12-06Final Data Sheet
5PackageOutlines
0.65
MILLIMETERS
DIMENSION
- 1.10A
b1
c
D
E1
e
0.32 0.52
0.20
1.50 1.70
MIN. MAX.
3.30
3.30
e1
1
02mm
03
ISSUE DATE
08.11.2019
DOCUMENT NO.
Z8B00192161
EUROPEAN PROJECTION
REVISION
0.395
L0.35 0.55
SCALE 10:1
b0.20 0.40
D1 2.31 2.51
D2 1.58 1.78
E
L1 0.10 0.30
L2 0.40 0.60
L3 1.285 1.485
L4 0.73 0.93
- 0.05A1
Figure1OutlinePG-TTFN-9-1,dimensionsinmm
11
OptiMOSTM5Power-Transistor,25V
IQE006NE2LM5CG
Rev.2.0,2019-12-06Final Data Sheet
copper solder mask stencil apertures
All dimensions are in units mm
0.3
4x
0.4
4x
1.06
2x
0.5
0.38
4x
1.1
4x
0.3
4x
1.6
0.365
0.57
4x
0.155
0.42
2x
0.965
1.59
0.15
0.615
0.975
1.675
0.22
2x
1.235
0.395
0.65
6x
1.629
0.4
2x
1.059
1.15
0.055
2x
0.3
6x
0.35
8x
0.45
1.1
0.8
1.2
0.7
0.45
1.1
0.985
0.45
0.475
1.35
0.15
0.395
0.595
Pin 1
0.975
0.65
6x
Figure2OutlineBoardpad(PG-TTFN-9-1),dimensionsinmm
12
OptiMOSTM5Power-Transistor,25V
IQE006NE2LM5CG
Rev.2.0,2019-12-06Final Data Sheet
Pin1 Marking
The drawing is in compliance with ISO 128-30, Projection Method 1 [ ]
All dimensions are in units mm
12
8 0.3
1.2
3.6
3.6
4
Figure3OutlineTape(PG-TTFN-9-1),dimensionsinmm
13
OptiMOSTM5Power-Transistor,25V
IQE006NE2LM5CG
Rev.2.0,2019-12-06Final Data Sheet
RevisionHistory
IQE006NE2LM5CG
Revision:2019-12-06,Rev.2.0
Previous Revision
Revision Date Subjects (major changes since last revision)
2.0 2019-12-06 Release of final version
Trademarks
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Publishedby
InfineonTechnologiesAG
81726München,Germany
©2019InfineonTechnologiesAG
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Warnings
Duetotechnicalrequirements,componentsmaycontaindangeroussubstances.Forinformationonthetypesinquestion,
pleasecontactthenearestInfineonTechnologiesOffice.
TheInfineonTechnologiescomponentdescribedinthisDataSheetmaybeusedinlife-supportdevicesorsystemsand/or
automotive,aviationandaerospaceapplicationsorsystemsonlywiththeexpresswrittenapprovalofInfineonTechnologies,ifa
failureofsuchcomponentscanreasonablybeexpectedtocausethefailureofthatlife-support,automotive,aviationand
aerospacedeviceorsystemortoaffectthesafetyoreffectivenessofthatdeviceorsystem.Lifesupportdevicesorsystemsare
intendedtobeimplantedinthehumanbodyortosupportand/ormaintainandsustainand/orprotecthumanlife.Iftheyfail,itis
reasonabletoassumethatthehealthoftheuserorotherpersonsmaybeendangered.