General Description
The MAX9600/MAX9601/MAX9602 ultra-high-speed com-
parators feature extremely low propagation delay
(500ps). These dual and quad comparators minimize
propagation delay skew (10ps) and are designed for low
propagation delay dispersion (30ps). These features
make them ideal for applications where high-fidelity track-
ing of narrow pulses and low timing dispersion is critical.
The differential input stage accepts a wide range of signals
in the common-mode range from (VEE + 3V) to (VCC - 2V).
The outputs are complementary digital signals, compatible
with ECL and PECL systems, and provide sufficient current
to directly drive transmission lines terminated in 50Ω.
The MAX9600/MAX9601 dual-channel ECL and dual-chan-
nel PECL output comparators incorporate latch enable
(LE_, LE_), and hysteresis (HYS_). The complementary
latch-enable control permits tracking, track-hold, or sample-
hold mode of operations. The latch enables can be driven
with standard ECL logic for MAX9600 and PECL logic for
MAX9601. The MAX9602 quad-channel PECL output
comparator is ideal for high-density packaging in limit-
ed board space.
The MAX9600/MAX9601 are available in 20-pin TSSOP
packages, and the MAX9602 is offered in a 24-pin
TSSOP package. The MAX9600/MAX9601/MAX9602
are specified for operation from -40°C to +85°C.
Applications
VLSI and High-Speed Memory ATE
High-Speed Instrumentation
Scope/Logic Analyzer Front Ends
High-Speed Triggering
Threshold and Peak Detection
Line Receiving/Signal Restoration
Features
♦500ps Propagation Delay
♦30ps Propagation Delay Dispersion
♦4Gbps Tracking Frequency
♦-2.2V to +3V Input Range with +5V/-5.2V Supplies
♦-1.2V to +4V Input Range with +6V/-4.2V Supplies
♦Differential ECL Outputs (MAX9600)
♦Differential PECL Outputs (MAX9601/MAX9602)
♦Latch Enable (MAX9600/MAX9601)
♦Adjustable Hysteresis (MAX9600/MAX9601)
MAX9600/MAX9601/MAX9602
Dual ECL and Dual/Quad PECL, 500ps,
Ultra-High-Speed Comparators
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-2409; Rev 1; 9/02
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE PIN-PACKAGE
MAX9600EUP -40°C to +85°C 20 TSSOP
MAX9601EUP -40°C to +85°C 20 TSSOP
MAX9602EUG -40°C to +85°C 24 TSSOP
Pin Configurations appear at end of data sheet.
Functional Diagrams
IN_+ Q_
ECL OUTPUT
VT = -2V
LE_
RLRL
IN_-
HYS_
RHYS_
VCC VEE GND
1/2
MAX9600
LE_
Q_
IN_+ Q_
PECL OUTPUT
VT = VCCO_ - 2V
LE_
RLRL
IN_-
HYS_
RHYS_
VCC VEE VCCO_
1/2
MAX9601
LE_
Q_
IN_+ Q_
PECL OUTPUT
VT = VCCO_ - 2V
RLRL
IN_-
VCC VEE VCCO_
1/4
MAX9602
Q_
THE OPEN-EMITTER OUTPUTS REQUIRE EXTERNAL PULLDOWN RESISTORS (RL). USE RESISTORS IN THE RANGE OF 50Ω TO 75Ω CONNECTED TO VT.
CURRENT-CONTROLLED HYSTERESIS REQUIRES A SINGLE EXTERNAL RESISTOR (RHYS_) FROM HYS_ TO GND IN THE RANGE OF 10kΩ TO 35kΩ.
PART PIN-PACKAGE SELECTION
MAX9600EUP 20 TSSOP
Dual ECL Output
Comparator with Latch
Enable and Hysteresis
MAX9601EUP 20 TSSOP
Dual PECL Output
Comparator with Latch
Enable and Hysteresis
MAX9602EUG 24 TSSOP Quad PECL Output
Comparator
Selector Guide
MAX9600/MAX9601/MAX9602
Dual ECL and Dual/Quad PECL, 500ps,
Ultra-High-Speed Comparators
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VS= VCC - VEE ...................................................................12.0V
VCC to GND (MAX9600) .......................................................6.8V
VEE to GND (MAX9600) ......................................................-6.5V
Differential Input Voltage ...................................................±6.5V
Latch Differential Voltage ......................................................±4V
Common-Mode Input Voltage (VCM) .........................VEE to VCC
VCCO_ to VEE
(MAX9601/MAX9602)....................(VEE - 0.3V) to (VCC + 0.3V)
LE_, LE_ to GND
MAX9600 ....................................................(VEE - 0.3V) to 0.3V
MAX9601 ..................................(VEE - 0.3V) to (VCCO_ + 0.3V)
Input Current to Any Input Pin.............................................10mA
HYS_ Current (MAX9600/MAX9601) ...................................-1mA
Continuous Output Current .................................................50mA
Continuous Power Dissipation (TA= +70°C)
20-Pin TSSOP (derate 10.9mW/oC above +70°C) ........879mW
24-Pin TSSOP (derate 12.2mW/°C above +70°C) ........975mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
INPUT (IN_+, IN_-)
Input Differential Voltage Range VID Guaranteed by input bias current tests -5.2 +5.2 V
Input Common-Mode Voltage VCM Guaranteed by input bias current tests VEE + 3 VCC - 2 V
TA = +25°C±1±5
Input Offset Voltage VOS TMIN ≤ TA ≤ TMAX ±9mV
Input Offset-Voltage Tempco TCVOS 8 µV/°C
Input Offset-Voltage Channel
Matching 1mV
Input Bias Current IBVID = ±5.2V 6 20 µA
Input Bias-Current Tempco TCIB10 nA/°C
Input Offset Current IOS 0.3 ±5µA
Differential mode (VID ≤ 10mV) 10 kΩ
Input Resistance RIN Common mode (VEE + 3V) ≤ VCM ≤ (VCC - 2V) 100 MΩ
LATCH INPUT (LE_, LE_)
MAX9600 0.4 2.0
Latch Differential Input Voltage VLD Guaranteed by latch
input current MAX9601 0.25 3.50 V
MAX9600 -2 0
VCCO_ ≥ 3.5V VCCO_
- 3.5 VCCO_Latch Input Voltage Range VLR MAX9601
VCCO_ < 3.5V 0 VCCO_
V
MAX9600 5 20
Latch Input Current ILE, ILE MAX9601 5 20 µA
HYSTERESIS INPUT (HYS_)
RHYS = ∞0
Input-Referred Hysteresis MAX9600/MAX9601 RHYS = 16.4kΩ30 mV
DC ELECTRICAL CHARACTERISTICS
(VCC = 5V, VEE = -5.2V, VCM = 0V, HYS_ = open (MAX9600/MAX9601), LE_ = low, LE_ = high (MAX9600/MAX9601), GND = 0V,
RL= 50Ωto -2V (MAX9600), VCCO_ = 5V, RL= 50Ωto 3V (MAX9601/MAX9602), TA= TMIN to TMAX. Typical values are at
TA= +25°C, unless otherwise noted.) (Note 1)
MAX9600/MAX9601/MAX9602
Dual ECL and Dual/Quad PECL, 500ps,
Ultra-High-Speed Comparators
_______________________________________________________________________________________ 3
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
OUTPUT (Q_, Q__
__)
MAX9600 -1.10 -0.94 -0.75
TA = +25°CMAX9601/MAX9602 VCCO_
- 1.10
VCCO_
- 0.94
VCCO_
- 0.75
MAX9600 -1.2 -1.02 -0.8
TA = TMIN MAX9601/MAX9602 VCCO_
- 1.2
VCCO_
- 1.02
VCCO_
- 0.8
MAX9600 -1.05 -0.87 -0.70
Logic Output High Voltage VOH
TA = TMAX MAX9601/MAX9602 VCCO_
- 1.05
VCCO_
- 0.87
VCCO_
- 0.70
V
MAX9600 -1.95 -1.72 -1.55
TA = +25°CMAX9601/MAX9602 VCCO_
- 1.95
VCCO_
- 1.72
VCCO_
- 1.55
MAX9600 -2.0 -1.78 -1.6
TA = TMIN MAX9601/MAX9602 VCCO_
- 2.0
VCCO_
- 1.78
VCCO_
- 1.6
MAX9600 -1.9 -1.66 -1.50
Logic Output Low Voltage VOL
TA = TMAX MAX9601/MAX9602 VCCO_
- 1.9
VCCO_
- 1.66
VCCO_
- 1.5
V
SUPPLY
Positive Supply Voltage VCC Guaranteed by output swing tests 4.3 5 6.3 V
Negative Supply Voltage VEE Guaranteed by output swing tests -6 -5.2 -4 V
Supply Voltage Difference VSVS = (VCC - VEE), guaranteed by
output swing tests 9.5 11.5 V
Logic Supply Voltage VCCO_ MAX9601/MAX9602 2.4 VCC V
MAX9600 16 24
MAX9601 19 27
Positive Supply Current ICC (Note 2)
MAX9602 28 39
mA
MAX9600 21 28
MAX9601 24 33
Negative Supply Current IEE (Note 2)
MAX9602 38 49
mA
MAX9600 190 266
MAX9601 220 307Power-Supply Dissipation PDISS (Note 2)
MAX9602 338 450
mW
Common-Mode Rejection Ratio CMRR (VEE + 3V) ≤ VCM ≤ (VCC - 2V) 70 dB
Power-Supply Rejection Ratio PSRR 4.3V ≤ VCC ≤ 6.3V, -6V ≤ VEE ≤ -4V,
9.5V ≤ VS ≤ 11.5V 65 dB
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 5V, VEE = -5.2V, VCM = 0V, HYS_ = open (MAX9600/MAX9601), LE_ = low, LE_ = high (MAX9600/MAX9601), GND = 0V,
RL= 50Ωto -2V (MAX9600), VCCO_ = 5V, RL= 50Ωto 3V (MAX9601/MAX9602), TA= TMIN to TMAX. Typical values are at
TA= +25°C, unless otherwise noted.) (Note 1)
MAX9600/MAX9601/MAX9602
Dual ECL and Dual/Quad PECL, 500ps,
Ultra-High-Speed Comparators
4 _______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS
(VCC = 5V, VEE = -5.2V, VCM = 0V, HYS_ = open (MAX9600/MAX9601), LE_ = low, LE_ = high (MAX9600/MAX9601), CL= 5pF,
GND = 0V, RL= 50Ωto -2V (MAX9600), VCCO_ = 5V, RL= 50Ωto 3V (MAX9601/MAX9602), TA= TMIN to TMAX. Typical values are at
TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Tracking Frequency Toggle Rate fMAX VOUT = 550mVP-P, input overdrive = 100mV 4 Gbps
Minimum Pulse Width tPW VOUT = 550mVP-P, input overdrive = 100mV 250 ps
Propagation Delay tPD-
,
tPD+ Input overdrive = 100mV, Figure 1, (Note 3) 500 700 ps
Propagation Delay Tempco TCtPD 0.5 ps/°C
Propagation Delay Skew tPDSKEW Input overdrive = 100mV (Note 4) 10 ps
Propagation Delay Match Input overdrive = 100mV (Note 5) 40 ps
10mV to 100mV 15
Propagation Delay Dispersion
Overdrive 100mV to 2V 40 ps
Propagation Delay Dispersion
Common-Mode Voltage (VEE + 3V) ≤ VCM ≤ (VCC - 2V) 10
Propagation Delay Dispersion
Input Slew Rate 0.2V/ns to 10V/ns 40
Propagation Delay Dispersion
Duty Cycle 10% to 90% at 250MHz 30
Propagation Delay Dispersion
Pulse Width
VIN = 1VP-P
input
overdrive =
100mV
350ps to 1ns 20
ps
Unit-to-Unit Propagation Delay
Match Input overdrive = 100mV 50 ps
Output Jitter VIN = 2VP-P; 50MHz 300 fs
Input Capacitance CIN IN_+ or IN_, with respect to GND 2 pF
Latch Setup Time tLS Figure 1, (Notes 3, 6) 250 80 ps
Latch Hold Time tLH Figure 1, (Notes 3, 6) 300 85 ps
Minimum Pulse Width tLPW Figure 1 250 ps
Latch to Output Delay tLPD Figure 1 200 ps
Rise Time and Fall Time tR, tF20% to 80%, Figure 1 200 ps
Note 1: All devices are 100% production tested at TA= +25°C. Specifications over temperature are guaranteed by design.
Note 2: Does not include output state current in Q_, Q_.
Note 3: Guaranteed by design.
Note 4: Propagation delay skew (tPDSKEW) is for a single channel and is the difference between the propagation delay to the high-
to-low output transition vs. the low-to-high output transition.
Note 5: Propagation delay match is the difference of tPD- or tPD+ of one channel to the tPD- or tPD+ of another channel of the same device.
Note 6: Latch setup and hold-timing specifications are for a differentially driven latch signal.
MAX9600/MAX9601/MAX9602
Dual ECL and Dual/Quad PECL, 500ps,
Ultra-High-Speed Comparators
_______________________________________________________________________________________ 5
MAX9600/1/2 toc01
INPUT OVERDRIVE (mV)
PROPAGATION DELAY (ps)
9080706050403020
480
490
500
510
520
530
470
10 100
PROPAGATION DELAY vs. INPUT OVERDRIVE
(VCC = 10mV TO 100mV)
MAX9600/1/2 toc02
INPUT OVERDRIVE (V)
PROPAGATION DELAY (ps)
1.81.60.2 0.4 0.6 1.0 1.20.8 1.4
420
440
460
480
500
520
540
560
400
0 2.0
PROPAGATION DELAY vs. INPUT OVERDRIVE
(VOD = 0.1V TO 2V)
MAX9600/1/2 toc03
SOURCE IMPEDANCE (Ω)
PROPAGATION DELAY (ps)
500400300200100
3500
0
0 600
PROPAGATION DELAY
vs. SOURCE IMPEDANCE
500
1000
1500
2000
2500
3000
PROPAGATION DELAY
vs. CAPACITIVE LOAD
MAX9600/1/2 toc04
CAPACITIVE LOAD (pF)
PROPAGATION DELAY (ps)
252015105
250
500
750
1000
1250
1500
0
030
MAX9600/1/2 toc05
TEMPERATURE (°C)
PROPAGATION DELAY (ps)
7550-25 0 25
480
490
500
510
520
530
540
550
470
-50 100
PROPAGATION DELAY
vs. TEMPERATURE
MAX9600/1/2 toc05
COMMON-MODE VOLTAGE (V)
PROPAGATION DELAY (ps)
210-1-2
480
490
500
510
520
530
470
-3 3
PROPAGATION DELAY
vs. COMMON-MODE VOLTAGE
Typical Operating Characteristics
(VCC = 5V, VEE = -5.2V, VCM = 0V, HYS _ = open (MAX9600/MAX9601), LE_ = low, LE_ = high (MAX9600/MAX9601), CL= 5pF, GND = 0V,
RL= 50Ωto -2V (MAX9600), VCCO_ = 5V, RL= 50Ωto 3V (MAX9601/MAX9602), input slew rate = 2V/ns, duty cycle = 50%,
TA= TMIN to TMAX. Typical values are at TA= +25°C, unless otherwise noted.) (Note 1)
MAX9600/MAX9601/MAX9602
Dual ECL and Dual/Quad PECL, 500ps,
Ultra-High-Speed Comparators
6 _______________________________________________________________________________________
PROPAGATION DELAY
vs. PULSE WIDTH
MAX9600/1/2 toc07
PULSE WIDTH (ps)
PROPAGATION DELAY (ps)
900800600 700500400
460
470
480
490
500
510
520
530
540
550
450
300 1000
MAX9600/1/2 toc08
INPUT SLEW RATE (V/ns)
PROPAGATION DELAY (ps)
987654321
480
490
500
510
520
530
540
470
010
PROPAGATION DELAY
vs. INPUT SLEW RATE
PROPAGATION DELAY
vs. DUTY CYCLE
MAX9600/1/2 toc09
DUTY CYCLE (%)
PROPAGATION DELAY (ps)
908060 7020 30 40 5010
460
470
480
490
500
510
520
530
540
550
450
0 100
FREQUENCY = 250MHz
MAX9600/1/2 toc10
TEMPERATURE (°C)
INPUT OFFSET VOLTAGE (µV)
7550250-25
-200
-100
0
100
200
300
-300
-50 100
INPUT OFFSET VOLTAGE
vs. TEMPERATURE
MAX9600/1/2 toc11
RHYS (kΩ)
HYSTERESIS (mV)
3530252015
10
20
30
40
50
60
70
0
10 40
HYSTERESIS
vs. RHYS TO GND
MAX9600/1/2 toc12
TEMPERATURE (°C)
HYSTERESIS (mV)
7550250-25
26
27
28
29
30
31
32
33
34
35
25
-50 100
HYSTERESIS
vs. TEMPERATURE
RHYS = 16.4kΩ
Typical Operating Characteristics (continued)
(VCC = 5V, VEE = -5.2V, VCM = 0V, HYS _ = open (MAX9600/MAX9601), LE_ = low, LE_ = high (MAX9600/MAX9601), CL= 5pF, GND = 0V,
RL= 50Ωto -2V (MAX9600), VCCO_ = 5V, RL= 50Ωto 3V (MAX9601/MAX9602), input slew rate = 2V/ns, duty cycle = 50%,
TA= TMIN to TMAX. Typical values are at TA= +25°C, unless otherwise noted.) (Note 1)
MAX9600/MAX9601/MAX9602
Dual ECL and Dual/Quad PECL, 500ps,
Ultra-High-Speed Comparators
_______________________________________________________________________________________ 7
MAX9600/1/2 toc13
TEMPERATURE (°C)
INPUT BIAS CURRENT (µA)
7550-25 0 25
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
4.0
-50 100
INPUT BIAS CURRENT
vs. TEMPERATURE
MAX9600/1/2 toc14
INPUT VOLTAGE DIFFERENTIAL (V)
INPUT BIAS CURRENT (µA)
420-2-4
0
5
10
15
20
-5
-6 6
INPUT BIAS CURRENT
vs. INPUT VOLTAGE DIFFERENTIAL
TA = +85°C
TA = +25°C
TA = -40°C
MAX9600/1/2 toc15
TEMPERATURE (°C)
OUTPUT VOLTAGE HIGH (V)
7550250-25
-1.00
-0.95
-0.90
-0.85
-0.80
-0.75
-1.05
-50 100
RL = 200Ω
OUTPUT VOLTAGE HIGH
vs. TEMPERATURE
RL = 100Ω
RL = 50Ω
MAX9600/1/2 toc16
TEMPERATURE (°C)
75
50250-25
-1.75
-1.70
-1.65
-1.60
-1.55
-1.80
-50 100
OUTPUT VOLTAGE LOW
vs. TEMPERATURE
RL = 100Ω
RL = 200Ω
RL = 50Ω
OUTPUT VOLTAGE LOW (V)
OUTPUT RESPONSE TO 100MHz INPUT
2ns/div
QOUT
200mV/div
VIN
50mV/div
MAX9600/1/2 toc17
OUTPUT RESPONSE TO 4Gbps INPUT
200ps/div
VIN
50mV/div
MAX9600/1/2 toc18
QOUT - QOUT
200mV/div
Typical Operating Characteristics (continued)
(VCC = 5V, VEE = -5.2V, VCM = 0V, HYS _ = open (MAX9600/MAX9601), LE_ = low, LE_ = high (MAX9600/MAX9601), CL= 5pF, GND = 0V,
RL= 50Ωto -2V (MAX9600), VCCO_ = 5V, RL= 50Ωto 3V (MAX9601/MAX9602), input slew rate = 2V/ns, duty cycle = 50%,
TA= TMIN to TMAX. Typical values are at TA= +25°C, unless otherwise noted.) (Note 1)
MAX9600/MAX9601/MAX9602
Dual ECL and Dual/Quad PECL, 500ps,
Ultra-High-Speed Comparators
8 _______________________________________________________________________________________
Pin Descriptions
PIN
MAX9600 MAX9601 NAME FUNCTION
1 1 QA Channel A Output
22QA Channel A Complementary Output
3—GND Channel A Output Ground
—3V
CCOA Channel A Output Driver Positive Supply
4 4 LEA Channel A Latch-Enable Input
55LEA Channel A Latch-Enable Complementary Input
6, 15 6, 15 VEE Negative Supply Voltage
7, 14 7, 14 VCC Positive Supply Voltage
8 8 HYSA Channel A Hysteresis Input
9 9 INA- Channel A Minus Input
10 10 INA+ Channel A Plus Input
11 11 INB+ Channel B Plus Input
12 12 INB- Channel B Minus Input
13 13 HYSB Channel B Hysteresis Input
16 16 LEB Channel B Latch-Enable Complementary Input
17 17 LEB Channel B Latch-Enable Input
18 —GND Channel B Output Ground
—18 VCCOB Channel B Output Driver Positive Supply
19 19 QB Channel B Complementary Output
20 20 QB Channel B Output
MAX9600/MAX9601
tLPW
VLD
LE_
LATCH
20% 20%
80% 80%
LATCH
VLR (MAX)
VLR (MIN)
COMPARE
IN_-
IN_+
tLPD
tFW(MIN) tLH
tLS
VLE + VLE
2
VOH + VOL
2
VID
VOH – VOL
VCM
LE_
Q_
Q_
tPD- tPD+
tRtF
Figure 1. MAX9600/MAX9601/MAX9602 Timing Diagram
Timing Diagram
Detailed Description
The MAX9600/MAX9601/MAX9602 ultra-high-speed com-
parators feature extremely low propagation delay
(500ps). These dual and quad comparators minimize
channel-to-channel skew (10ps) and are designed for low
propagation delay dispersion. These features make them
ideal for applications where high-fidelity tracking of nar-
row pulses and low timing dispersion is critical. The
devices operate from either standard supply levels of
-5.2V/+5V or shifted levels of -4.2V/+6V.
The differential input stage accepts a wide range of sig-
nals in the common-mode range from (VEE + 3V) to (VCC
- 2V) with a CMRR of 70dB (typ). The outputs are com-
plementary digital signals, compatible with ECL and
PECL systems, and provide sufficient current to directly
drive transmission lines terminated in 50Ω. The ultra-fast
operation makes signal processing possible at a data
rate up to 4Gbps. Figure 2 shows a 1Gbps (500MHz)
example with an input-signal level of 100mVP-P.
MAX9600/MAX9601/MAX9602
Dual ECL and Dual/Quad PECL, 500ps,
Ultra-High-Speed Comparators
_______________________________________________________________________________________ 9
PIN NAME FUNCTION
1 INA+ Channel A Plus Input
2 INA- Channel A Minus Input
3, 9 VEE Negative Supply Voltage
4 INB+ Channel B Plus Input
5 INB- Channel B Minus Input
6, 12 VCC Positive Supply Voltage
7 INC+ Channel C Plus Input
8 INC- Channel C Minus Input
10 IND+ Channel D Plus Input
11 IND- Channel D Minus Input
13 QD Channel D Complementary Output
14 QD Channel D Output
15 VCCOD Channel D Output Driver Positive Supply
16 QC Channel C Complementary Output
17 QC Channel C Output
18 VCCOC Channel C Output Driver Positive Supply
19 QB Channel B Complementary Output
20 QB Channel B Output
21 VCCOB Channel B Output Driver Positive Supply
22 QA Channel A Complementary Output
23 QA Channel A Output
24 VCCOA Channel A Output Driver Positive Supply
MAX9602
Pin Descriptions (continued)
INPUT
50mV/div
OUTPUT
200mV/div
-0.9V
-1.7V
0V
500ps/div
Figure 2. Signal Processed at 500MHz with Input-Signal Level
of 100mVRMS.
MAX9600/MAX9601/MAX9602
The MAX9600/MAX9601 incorporate latch-enable and
hysteresis control. Hysteresis rejects noise and pre-
vents oscillations on low-slew input signals. The latch-
enable control permits tracking or sampling mode of
operations. Drive the complementary latch enable with
standard ECL logic for MAX9600 and PECL logic for
MAX9601. The MAX9602 quad-channel PECL output
comparator does not include the latch-enable or hys-
teresis control functions.
Applications Information
Layout
Special layout precautions exist due to the large gain-
bandwidth characteristic of the MAX9600/MAX9601/
MAX9602. Use a printed circuit board with a good, low-
inductance ground plane. Mount 0.01µF ceramic
decoupling capacitors as close to the power-supply
inputs as possible. Minimize lead lengths on the inputs
and outputs to avoid unwanted parasitic feedback
around the comparators. Use surface-mount chip com-
ponents to minimize lead inductance. Pay close atten-
tion to the bandwidth of the decoupling and terminating
components.
Use microstrip layout and terminations at the input and
output. Avoid discontinuities in differential impedance.
Maximize common-mode noise immunity by maintain-
ing the distance between differential traces and avoid
sharp corners. Minimize the number of vias to prevent
impedance discontinuities. Match the electrical length
of the traces to minimize skew.
Input Slew-Rate Requirements
As with all high-speed comparators, the high gain-
bandwidth product of these devices can create oscilla-
tion problems when the input goes through the
threshold region. This is typically due to parasitic paths,
which cause positive feedback to occur. For clean
switching without oscillation or steps in the output
waveform for the MAX9600/MAX9601, use an input with
a slew rate of 5V/µs or faster. For the MAX9602, use a
slew rate of 25V/µs or faster. The tendency of the part
to oscillate is a function of the layout and source imped-
ance of the circuit employed. Poor layout and larger
source impedance increases the minimum slew-rate
requirement. Adding hysteresis accommodates slower
inputs (see the Hysteresis section).
Hysteresis (MAX9600/MAX9601)
Hysteresis can be introduced to prevent oscillation or
multiple transitions due to noise. The MAX9600/
MAX9601 feature current-controlled hysteresis, which is
set by placing a resistor between HYS_ and GND. The
value of the current-setting resistor is determined by the
output voltage of 2.5V at HYS_ divided by the desired
hysteresis current level in the range of 0 to 200µA.
RHYS of 10kΩto 35kΩresistors provides hysteresis of
60mV to 5mV (see the Hysteresis vs. RHYS to GND
graph in the Typical Operating Characteristics section).
For a zero hysteresis (0µA hysteresis current), leave
HYS_ open or connect it to VCC.
Propagation Delay Dispersion
Propagation delay dispersion is defined as a variation
in propagation delay as a function of change in input
conditions. In an automatic test system pin-driver elec-
tronics, for example, the dispersion determines the
maximum edge resolution.
Many factors can affect the dispersion, such as common-
mode voltage, overdrive, input slew rate, duty cycle, and
pulse width. The typical propagation delay dispersions of
the MAX9600/MAX9601/MAX9602 are less than 10ps to
40ps (see the Typical Operating Characteristics and
Electrical Characteristics sections).
Comparators with Latch Enable
(MAX9600/MAX9601)
The latch-enable function allows the comparator to be
used in a sampling mode. When LE_ is low (LE_ is high),
the comparator tracks the input signal. When LE_ is dri-
ven high (LE_ is low), the outputs are forced to an unam-
biguous logic state, dependent on the input conditions at
the time of the latch input transition. If the latch-enable
function is not used, connect the appropriate LE_ input
to a low ECL/PECL logic, and its complementary LE_
input to a high ECL/PECL logic level (see Table 1).
The input range of the MAX9600 differential latch-
enable inputs is 400mV to 2V. The logic-input swing
excursion must fall within an input-voltage range (VLR)
of -2V to 0 to work properly. The input range of the
MAX9601 differential latch-enable inputs is 250mV to
3.5V. The logic-input swing excursion must fall within an
input-voltage range (VLR) of 0 to 3.5V for (VCCO_ <
3.5V) or VLR of (VCCO_ - 3.5V) to VCCO_ for (VCCO_ ≥
3.5V) to work properly.
Dual ECL and Dual/Quad PECL, 500ps,
Ultra-High-Speed Comparators
10 ______________________________________________________________________________________
LATCH-ENABLE INPUT
LE_ LE__
__ OPERATION
01
Compare Mode. Output follows
input state.
10
Latch Mode. Output latches to
last known output state.
00
11
Invalid condition, output is in
unknown state.
Table 1. Latch-Enable Truth Table
MAX9600/MAX9601/MAX9602
Dual ECL and Dual/Quad PECL, 500ps,
Ultra-High-Speed Comparators
______________________________________________________________________________________ 11
Timing Information (MAX9600/MAX9601)
The timing diagram (Figure 1) illustrates the operation
of a comparator with latch enable. The top line of the
diagram illustrates a latch-enable pulse. Initially, the
latch-enable input (LE, LE_) is differentially high, which
places the comparator in latch mode. When the input
signal (IN_+, IN_-) switches from low to high, the output
(Q_, Q_) remains latched to the previous low state.
When the latch-enable input goes differentially low,
starting the compare function, the output responds to
the input and transitions to high after a time (tLPD). The
leading edges of the subsequent input signal switch
the comparator after time interval tPD+ or tPD- (depend-
ing on the direction of the input transitions) until a high
latch-enable pulse places the device in latch mode
again. The input signal must occur at minimum time
(tLS) before the latch rising edge, and must maintain its
state for at least tLH after the rising edge. A minimum
latch-pulse width (tLPW) of 250ps (typ) is needed for
proper latch operation.
ECL/PCL
The MAX9600/MAX9601/MAX9602 outputs are emitter
followers that require external resistive connections to a
voltage source (VT) more negative than the lowest VOL
for proper static and dynamic operation. When properly
terminated, the outputs provide appropriate levels, VOL
or VOH, for ECL (MAX9600) or PECL (MAX9601/
MAX9602). Output-current polarity always sinks into the
termination scheme during proper operation.
ECL-output signal levels are referenced to GND, and
PECL-output signals are referenced to VCCO_.
Chip Information
MAX9600 TRANSISTOR COUNT: 558
MAX9601 TRANSISTOR COUNT: 600
MAX9602 TRANSISTOR COUNT: 608
PROCESS: Bipolar
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
QB
QB
VCCOB
LEBLEA
VCCOA
QA
QA
LEB
VEE
VCC
HYSBHYSA
VCC
VEE
LEA
12
11
9
10
INB-
INB+INA+
INA-
MAX9601
TSSOP-20
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
VCCOA
QA
QA
VCCOB
INB+
VEE
INA-
INA+
QB
QB
VCCOC
QCINC-
INC+
VCC
INB-
16
15
14
13
9
10
11
12
QC
VCCOD
QD
QDVCC
IND-
IND+
VEE
TSSOP-24
MAX9602
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
QB
QB
GND
LEBLEA
GND
QA
QA
TOP VIEW
LEB
VEE
VCC
HYSBHYSA
VCC
VEE
LEA
12
11
9
10
INB-
INB+INA+
INA-
MAX9600
TSSOP-20
Pin Configurations
MAX9600/MAX9601/MAX9602
Dual ECL and Dual/Quad PECL, 500ps,
Ultra-High-Speed Comparators
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
TSSOP4.40mm.EPS
