GND
VOLUME
CONTROL
POWER
SUPPLY
Digital
Interface
LM48824
Left
Right
SCL
SDA
V+
V-
LM48824
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SNAS479D –MARCH 2009–REVISED MAY 2013
LM48824 Class G Headphone Amplifier
with I
2
C Volume Control
Check for Samples: LM48824
1FEATURES DESCRIPTION
The LM48824 is a Class G, ground-referenced stereo
2• Class G Power Savings headphone amplifier designed for portable devices.
• Ground Referenced Headphone Outputs – The LM48824 features TI’s ground-referenced
Eliminates Output Coupling Capacitors architecture, which eliminates the large DC blocking
• Common-Mode Sense capacitors required by traditional headphone
amplifiers, saving board space and minimizing
• I2C Volume and Mode Control system cost.
• High Output Impedance in Shutdown The LM48824 takes advantage of TI’s patent-pending
• Differential Inputs Class G architecture offering power savings
• Advanced Click-and-Pop Suppression compared to a traditional Class AB headphone
• Low Supply Current amplifier. Additionally, output noise is improved by
common-mode sensing that corrects for any
• Low THD Mode Option differences between the amplifier ground and the
potential at the headphone return terminal, minimizing
APPLICATIONS noise created by any ground mismatches.
• Mobile Phones, PDAs, MP3 Players A high output impedance mode allows the LM48824's
• Portable Electronic Devices, Notebook PCs outputs to be driven by an external source without
degrading the signal. Other features include flexible
KEY SPECIFICATIONS power supply requirements, differential inputs for
improved noise rejection, a low power (2.5μA)
• Quiescent Power Supply Current at 3.6V: shutdown mode, and a 32-step I2C volume control
0.9mA (typ) with mute function.
• Output Power/Channel at VDD = 3.6V (RL= 16Ω,The LM48824's superior click and pop suppression
THD+N ≤1%): 37 mW (Typ) eliminates audible transients on power-up/down and
• Output Power/Channel at VDD = 3.6V (RL= 32Ω,during shutdown. The LM48824 is available in an
THD+N ≤1%): 29 mW (Typ) ultra-small 16-bump, 0.4mm pitch DSBGA package
• PSRR at 217Hz: 100 dB (Typ) (1.69mm x 1.69mm)
• Shutdown Current: 2.5 μA (Typ)
Simplified Block Diagram
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2009–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
VOLUME
CONTROL OUTPUT LEVEL
DETECT
CHARGE PUMP
REGULATOR
CONTROL
I2C INTERFACE
INL+
INL-
SDA
SCL
INR+
INR-
C1P
C1N
HPVSS
VDD
OUTL
OUTR
COM
GND
CIN
C1
C2
SW
HPVDD
CIN
CIN
CIN
5 k:5 k:
1 PF
1 PF
1 PF
1 PF
1 PF
10 PF
2.2 PF
2.4V to 5.5V
2.3V to 5.5V 3.3 PH
2.2 PF
C3
C4
LM48824
SNAS479D –MARCH 2009–REVISED MAY 2013
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Typical Application
Figure 1. Typical Audio Amplifier Application Circuit
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INL+
INR+
INR-
OUTL
HPVDD
COM
OUTR
HPVSS
A
B
C
D
SW
C1N
SDA
INL-
C1P
VDD
GND
SCL
2
14
3
LM48824
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SNAS479D –MARCH 2009–REVISED MAY 2013
Connection Diagram
Top View
Figure 2.
DSBGA Package (1.7mm x 1.7mm x 0.6mm)
See Package Number YFQ0016DDA
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)(3)(4)
Supply Voltage(1) 6V
Storage Temperature −65°C to +150°C
Input Voltage -0.3V to VDD + 0.3V
Power Dissipation(5) Internally Limited
ESD Rating(6) 2000V
ESD Rating(7) 200V
ESD Rating(8) 500V
Junction Temperature 150°C
Vapor Phase (60 sec.) 215°C
Soldering Information Infrared (15 sec.) 220°C
Thermal Resistance θJA (YFQ0016DDA) 60°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified
(2) The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(3) Soldering Information: See AN-1112 “Micro SMD Wafer Level Chip Scale package”
(4) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(5) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX ,θJA, and the ambient temperature,
TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings,
whichever is lower.
(6) Human body model, applicable std. JESD22-A114C.
(7) Machine model, applicable std. JESD22-A115-A.
(8) Charged Device Model, applicable std. JESD22-C101-C.
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Operating Ratings
Temperature Range (TMIN ≤TA≤TMAX)−40°C ≤TA≤+85°C
Supply Voltage (VDD) 2.4V ≤VDD ≤5.5V
Electrical Characteristics VDD = 3.6V(1)(2)
The following specifications apply for AV= 0dB, RL= 32Ω, f = 1kHz, unless otherwise specified. Limits apply to TA= 25°C.
LM48824 Units
Parameter Test Conditions (Limits)
Typ(3) Limit(4)
VIN = 0V, both channels active, RL=∞0.9 1.3 mA (max)
IDD Quiescent Power Supply Current RL=∞, Low THD mode 1.55 mA
PO= 100µW, two channels in phase, 3dB 1.8 2.5 mA (max)
Crest Factor, RL= 32Ω+ 15Ω
PO= 100µW, two channels in phase, 3dB
Crest Factor, RL= 32Ω+ 15Ω, 2.2 mA
Low THD mode
PO= 500µW, two channels in phase, 3dB 3.1 3.8 mA (max)
Crest Factor RL= 32Ω+ 15Ω
IDD(OP) Operating Power Supply Current PO= 500µW, two channels in phase, 3dB
Crest Factor RL= 32Ω+ 15Ω, 3.4 mA
Low THD mode
PO= 1mW, two channels in phase, 3dB 4.1 4.9 mA (max)
Crest Factor, RL= 32Ω+ 15Ω
PO= 1mW, two channels in phase, 3dB
Crest Factor, RL= 32Ω+ 15Ω, 4.4 mA
Low THD mode
ISD Shutdown Current Shutdown Enabled, VSCL = VSDA = 1.8V 2.5 3.9 µA (max)
VOS Output Offset Voltage VIN = 0V 0.15 0.65 mV (max)
TWU Wake Up Time From Shutdown 2 ms
–58 dB (max)
Minimum Gain Setting –59 –60 dB (min)
AVGain 4.5 dB (max)
Maximum Gain Setting 4 3.5 dB (min)
AV(MUTE) Mute Attenuation –110 dB
AV= 4dB 24 20 kΩ(min)
RIN Input Resistance AV= –59dB 64 80 kΩ(max)
f = 1kHz, THD+N = 1% 37 30 mW (min)
Two channels in phase, RL= 16Ω
POOutput Power f = 1kHz, THD+N = 1% 29 23 mW (min)
Two channels in phase, RL= 32Ω
THD+N = 1%, Two Channels in Phase VRMS
RL= 16Ω0.77 0.7 (min)
VRMS
VOOutput Swing RL= 32Ω0.96 0.86 (min)
RL= 32Ω+ 15Ω1.05 VRMS
VRMS
RL= 10kΩ1.3 1.1 (min)
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified
(2) The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(3) Typical values represent most likely parametric norms at TA= +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured.
(4) Datasheet min/max specification limits are specified by test or statistical analysis.
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LM48824
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SNAS479D –MARCH 2009–REVISED MAY 2013
Electrical Characteristics VDD = 3.6V(1)(2) (continued)
The following specifications apply for AV= 0dB, RL= 32Ω, f = 1kHz, unless otherwise specified. Limits apply to TA= 25°C.
LM48824 Units
Parameter Test Conditions (Limits)
Typ(3) Limit(4)
f = 1kHz, Single Channel
VO= 600mVRMS, RL= 16Ω0.05 %
VO= 600mVRMS, RL= 16Ω,0.03 %
Low THD Mode
VO= 800mVRMS, RL= 32Ω, 0.035 %
THD+N Total Harmonic Distortion + Noise VO= 800mVRMS, RL= 32Ω,0.02 %
Low THD Mode
VO= 900mVRMS, RL= 32Ω+ 15Ω0.027 0.04 %(max)
VO= 900mVRMS, RL= 32Ω+ 15Ω,0.015 %
Low THD Mode
VRIPPLE = 200mVP-P, Inputs AC GND, CIN = 1μF, input referred
PSRR Power Supply Rejection Ratio fRIPPLE = 217Hz 100 94 dB (min)
fRIPPLE = 1kHz 100 dB
CMRR Common Mode Rejection Ratio VRIPPLE = 1VP-P, fRIPPLE = 217Hz 60 dB
RL≥16Ω, PO= 5mW, f = 1kHz 80 70 dB (min)
XTALK Crosstalk RL≥10kΩ, VOUT = 1VRMS, f = 1kHz 110 95 dB (min)
VOUT = 1VRMS, f = 1kHz 102 98 dB (min)
SNR Signal-to-Noise Ratio VOUT = 1VRMS, f = 1kHz, 105 dB
Low THD Mode
AV= 4dB, A-Weighted Filter 8 12 μV(max)
∈OS Output Noise AV= 4dB, A-weighted Filter, Low THD 7μV
Mode
Charge pump-only mode enabled
f < 40kHz 43 30 kΩ(min)
ROUT Output Impedance f = 6MHz 500 Ω(min)
f = 36MHz 75 Ω(min)
No Sustained Oscillations
CLMaximum Capacitive Load with 5Ωseries resistance 100 nF
with no series resistance 100 pF
Voltage applied to amplifier outputs in VRMS
VOUT Maximum Voltage Swing 1.1 1.0
charge pump-only mode (min)
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I2C Interface Characteristics VDD = 3.6V(1)(2)
The following specifications apply for AV= 0dB, RL= 16Ω, f = 1kHz, unless otherwise specified. Limits apply to TA= 25°C.
LM48824 Units
Parameter Test Conditions (Limits)
Typ(3) Limit(4)
t1SCL Period 2.5 μs (min)
t2SDA Setup Time 250 ns (min)
t3SDA Stable Time 250 ns (min)
t4Start Condition Time 250 ns (min)
t5Stop Condition Time 250 ns (min)
VIH Input High Voltage 1.2 V (min)
VIL Input Low Voltage 0.6 V (max)
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified
(2) The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(3) Typical values represent most likely parametric norms at TA= +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured.
(4) Datasheet min/max specification limits are specified by test or statistical analysis.
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Product Folder Links: LM48824
0.001
100
0.01
0.1
1
10
20 20k100 1k 10k
FREQUENCY (Hz)
THD + N (%)
0.001
100
0.01
0.1
1
10
20 20k100 1k 10k
FREQUENCY (Hz)
THD + N (%)
0.001
100
0.01
0.1
1
10
20 20k100 1k 10k
FREQUENCY (Hz)
THD + N (%)
0.001
100
0.01
0.1
1
10
20 20k100 1k 10k
FREQUENCY (Hz)
THD + N (%)
0.001
100
0.01
0.1
1
10
20 20k100 1k 10k
FREQUENCY (Hz)
THD + N (%)
0.001
100
0.01
0.1
1
10
20 20k100 1k 10k
FREQUENCY (Hz)
THD + N (%)
LM48824
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SNAS479D –MARCH 2009–REVISED MAY 2013
Typical Performance Characteristics
THD+N vs Frequency
VDD = 3.6V, RL= 16Ω, VO= 600VRMS THD+N vs Frequency
Low THD Mode VDD = 3.6V, RL= 16Ω, VO= 600VRMS
Figure 3. Figure 4.
THD+N vs Frequency
VDD = 3.6V, RL= 32Ω, VO= 800VRMS THD+N vs Frequency
Low THD Mode VDD = 3.6V, RL= 32Ω, VO= 800VRMS
Figure 5. Figure 6.
THD+N vs Frequency
VDD = 3.6V, RL= 47Ω, VO= 900VRMS THD+N vs Frequency
Low THD Mode VDD = 3.6V, RL= 47Ω, VO= 900VRMS
Figure 7. Figure 8.
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100m 2200m 300m 500m 700m 1
0.01
100
0.1
1
10
THD + N (%)
OUTPUT VOLTAGE (V)
100m 2200m300m 500m 700m 1
0.01
100
0.1
1
10
THD + N (%)
OUTPUT VOLTAGE (V)
100m 2200m300m 500m700m 1
0.01
100
0.1
1
10
THD + N (%)
OUTPUT VOLTAGE (V)
100m 2200m300m 500m 700m 1
0.01
100
0.1
1
10
THD + N (%)
OUTPUT VOLTAGE (V)
1
0.01
100
0.1
1
10
THD + N (%)
100m 200m 400m 600m800m
OUTPUT VOLTAGE (V)
0.01
100
0.1
1
10
THD + N (%)
100m 1
200m 400m 600m 800m
OUTPUT VOLTAGE(V)
LM48824
SNAS479D –MARCH 2009–REVISED MAY 2013
www.ti.com
Typical Performance Characteristics (continued)
THD+N vs Output Voltage
VDD = 3.6V, RL= 16Ω, f = 1kHz THD+N vs Output Voltage
Low THD Mode VDD = 3.6V, RL= 16Ω, f = 1kHz
Figure 9. Figure 10.
THD+N vs Output Voltage
VDD = 3.6V, RL= 32Ω, f = 1kHz THD+N vs Output Voltage
Low THD Mode VDD = 3.6V, RL= 32Ω, f = 1kHz
Figure 11. Figure 12.
THD+N vs Output Voltage
VDD = 3.6V, RL= 47Ω, f = 1kHz THD+N vs Output Voltage
Low THD Mode VDD = 3.6V, RL= 47Ω, f = 1kHz
Figure 13. Figure 14.
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Product Folder Links: LM48824
20
40
60
80
100
120
0 5 10 15 20 25 30 35 40
OUTPUT POWER/CHANNEL (mW)
TOTAL POWER DISSIPATION (mW)
Low THD Mode
0
140
45
Normal Mode
10
20
30
40
50
60
70
0 5 10 15 20 25 30 35 40
OUTPUT POWER/CHANNEL (mW)
TOTAL POWER DISSIPATION (mW)
Low THD Mode
Normal Mode
0
80
0.01
100
0.1
1
10
THD + N (%)
1m 100m2m 5m 10m 20m 50m
OUTPUT POWER (W)
0.01
100
0.1
1
10
THD + N (%)
1m 100m2m 5m 10m 20m 50m
OUTPUT POWER (W)
0.01
100
0.1
1
10
THD + N (%)
1m 100m2m 5m 10m 20m 50m
OUTPUT POWER (W)
0.01
100
0.1
1
10
THD + N (%)
1m 100m2m 5m 10m 20m 50m
OUTPUT POWER (W)
LM48824
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SNAS479D –MARCH 2009–REVISED MAY 2013
Typical Performance Characteristics (continued)
THD+N vs Output Power
VDD = 3.6V, RL= 16Ω, f = 1kHz THD+N vs Output Power
Low THD Mode VDD = 3.6V, RL= 16Ω, f = 1kHz
Figure 15. Figure 16.
THD+N vs Output Power
VDD = 3.6V, RL= 32Ω, f = 1kHz THD+N vs Output Power
Low THD Mode VDD = 3.6V, RL= 32Ω, f = 1kHz
Figure 17. Figure 18.
Power Dissipation vs Output Power Power Dissipation vs Output Power
VDD = 3.6V, RL= 16Ω, f = 1kHz VDD = 3.6V, RL= 32Ω, f = 1kHz
Figure 19. Figure 20.
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-61
-60
-59
-58
-57
-56
10 100 1000 10000 100000
FREQUENCY (Hz)
CMRR (dB)
0.5
0.75
1
1.25
1.5
1.75
2
2 2.5 3 3.5 4 4.5 5 5.5 6
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
Normal Mode
Low THD Mode
20
25
30
35
40
45
50
2 2.5 3 3.5 4 4.5 5 5.5 6
SUPPLY VOLTAGE (V)
OUTPUT POWER/CHANNEL (mW)
THD+N = 1%
THD+N = 10%
15
15
20
25
30
35
40
2 2.5 3 3.5 4 4.5 5 5.5 6
SUPPLY VOLTAGE (V)
OUTPUT POWER/CHANNEL (mW)
THD+N = 1%
THD+N = 10%
5
10
15
20
25
30
0 5 10 15 20 25 30 35
OUTPUT POWER/CHANNEL (mW)
TOTAL POWER DISSIPATION (mW)
Low THD Mode
0
35 Normal Mode
40
45
50
10
20
30
40
50
60
70
2 2.5 3 3.5 4 4.5 5 5.5 6
SUPPLY VOLTAGE (V)
OUTPUT POWER/CHANNEL (mW)
THD+N = 1%
THD+N = 10%
LM48824
SNAS479D –MARCH 2009–REVISED MAY 2013
www.ti.com
Typical Performance Characteristics (continued)
Power Dissipation vs Output Power Output Power vs Supply Voltage
VDD = 3.6V, RL= 47Ω, f = 1kHz RL= 16Ω, f = 1kHz
Figure 21. Figure 22.
Output Power vs Supply Voltage Output Power vs Supply Voltage
RL= 32Ω, f = 1kHz RL= 47Ω, f = 1kHz
Figure 23. Figure 24.
CMRR vs Frequency
VDD = 3.6V, VRIPPLE = 1VP-P
Supply Current vs Supply Voltage No Load RL= 32Ω
Figure 25. Figure 26.
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-120
-100
-80
-60
-40
-20
10 100 1000 10000 100000
FREQUENCY (Hz)
PSRR (dB)
0
-100
-90
-80
-60
-60
-50
10 100 1000 10000 100000
FREQUENCY (Hz)
CROSSTALK (dB)
-40
LM48824
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SNAS479D –MARCH 2009–REVISED MAY 2013
Typical Performance Characteristics (continued)
PSRR vs Frequency Crosstalk vs Frequency
VDD = 3.6V, VRIPPLE = 200VP-P VDD = 3.6V, PO= 5mW
RL= 32ΩRL= 32Ω
Figure 27. Figure 28.
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SDA
SCL SP
START condition STOP condition
LM48824
SNAS479D –MARCH 2009–REVISED MAY 2013
www.ti.com
APPLICATION INFORMATION
I2C COMPATIBLE INTERFACE
The LM48824 is controlled through an I2C compatible serial interface that consists of a serial data line (SDA) and
a serial clock (SCL). The clock line is uni-directional. The data line is bi-directional (open drain). The LM48824
and the master can communicate at clock rates up to 400kHz. Figure 29 shows the I2C interface timing diagram.
Data on the SDA line must be stable during the HIGH period of SCL. The LM48824 is a transmit/receive slave-
only device, reliant upon the master to generate the SCL signal. Each transmission sequence is framed by a
START condition and a STOP condition (Figure 30). Each data word, device address and data, transmitted over
the bus is 8 bits long and is always followed by an acknowledge pulse (Figure 31). The LM48824 device address
is 1100000.
I2C BUS FORMAT
The I2C bus format is shown in Figure 31. The START signal, the transition of SDA from HIGH to LOW while
SCL is HIGH, is generated, alerting all devices on the bus that a device address is being written to the bus.
The 7-bit device address is written to the bus, most significant bit (MSB) first, followed by the R/W bit (R/W = 0
indicates the master is writing to the LM48824, R/W = 1 indicates the master wants to read data from the
LM48824). Data is latched into the device on the rising clock edge. Each address bit must be stable while SCL is
HIGH. After the last address bit is transmitted, the master device releases SDA, during which time, an
acknowledge clock pulse is generated by the slave device. If the LM48824 receives the correct address, the
device pulls the SDA line low, generating an acknowledge bit (ACK).
Once the master device registers the ACK bit, the 8-bit register address word is sent. Each data bit should be
stable while SCL is HIGH. After the 8-bit register address is sent, the LM48824 sends another ACK bit. Following
the acknowledgment of the register address, the 8-bit register data word is sent. Each data bit should be stable
while SCL is HIGH. After the 8-bit register data is sent, the LM48824 sends another ACK bit. Following the
acknowledgement of the register data word, the master issues a STOP bit, allowing SDA to go high while SCL is
high.
Figure 29. I2C Timing Diagram
Figure 30. Start and Stop Diagram
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ack from slave
ack from slave
w rs r stop
ack from slave ack from masterrepeated start data from slave
start w ack ack rs r ack ack stop
start
SCL
SDA
MSB Chip Address LSB
slave address = 1100000 register address = 0x00h
MSB Register 0x00h LSB MSB Data LSB
MSB Chip Address LSB
slave address = 1100000 register 0x00h data
ack ack ack ack
START MSB DEVICE ADDRESS LSB ACK
SCL
SDA STOPMSB REGISTER DATA LSB ACK
R/W
LM48824
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SNAS479D –MARCH 2009–REVISED MAY 2013
Figure 31. I2C Write Cycle
Figure 32. Example I2C Read Cycle
Table 1. Device Address
B7 B6 B5 B4 B3 B2 B1 B0 (R/W)
Device 1 1 0 0 0 0 0 X
Address
Table 2. I2C Control Registers(1)
Register Register B7 B6 B5 B4 B3 B2 B1 B0
Address Name
MODE
0x01h HPL_EN HPR_EN 0 0 0 0 THRM SHDN
CONTROL
VOLUME
0x02h MUTE_L MUTE_R VOL4 VOL3 VOL2 VOL1 VOL0 0
CONTROL
OUTPUT
0x03h 0 0 0 0 LOW_THD 0 HiZ_L HiZ_R
CONTROL
DEVICE
0x04h INFORMATIO 0 1 0 0 0 0 0 0
N (Read-Only)
(1) All registers default to 0 on initial power-up except SHDN, MUTE_L, MUTE_R bits default to 1 at power-up.
Table 3. Mode Control Register
Bit Name Value Description
0 Device enabled
B0 SHDN 1 Device disabled
0 Thermal-protection inactive
THRM
B1 (Read Only) 1 Thermal-protection active
0 Right channel amplifier disabled
B6 HPR_EN 1 Right channel amplifier enabled
0 Left channel amplifier disabled
B7 HPL_EN 1 Left channel amplifier enabled
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Table 4. Volume Control Register
Bit Name Value Description
B5:B1 VOL4:VOL0 These bits set the volume level. See Table 5.
0 Right Channel Mute Disabled
B6 MUTE_R 1 Right Channel Mute Enabled
0 Left Channel Mute Disabled
B7 MUTE_L 1 Left Channel Mute Enabled
Table 5. Volume Control
Volume Step VOL4 VOL3 VOL2 VOL1 VOL0 HP Gain (dB)
0 0 0 0 0 0 -59
1 0 0 0 0 1 -55
2 0 0 0 1 0 -51
3 0 0 0 1 1 -47
4 0 0 1 0 0 -43
5 0 0 1 0 1 -39
6 0 0 1 1 0 -35
7 0 0 1 1 1 -31
8 0 1 0 0 0 -27
9 0 1 0 0 1 -25
10 0 1 0 1 0 -23
11 0 1 0 1 1 -21
12 0 1 1 0 0 -19
13 0 1 1 0 1 -17
14 0 1 1 1 0 -15
15 0 1 1 1 1 -13
16 1 0 0 0 0 -11
17 1 0 0 0 1 -10
18 1 0 0 1 0 -9
19 1 0 0 1 1 -8
20 1 0 1 0 0 -7
21 1 0 1 0 1 -6
22 1 0 1 1 0 -5
23 1 0 1 1 1 -4
24 1 1 0 0 0 -3
25 1 1 0 0 1 -2
26 1 1 0 1 0 -1
27 1 1 0 1 1 0
28 1 1 1 0 0 1
29 1 1 1 0 1 2
30 1 1 1 1 0 3
31 1 1 1 1 1 4
14 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LM48824
HPVDD(HV)
HPVSS(HV)
HPVSS(LV)
HPVDD(LV)
0
Power dissipated in Class G
Power dissipated in Class AB
Power savings in Class G
+
Buck Converter Output
LM48824
www.ti.com
SNAS479D –MARCH 2009–REVISED MAY 2013
Table 6. Output Control Register
Bit Name Value Description
0 Right channel high impedance mode disabled
B0 HiZ_R 1 Right channel high impedance mode enabled
0 Left channel high impedance mode disabled
B1 HiZ_L 1 Left channel high impedance mode enabled
0 LOW_THD mode disabled
B3 LOW_THD 1 LOW_THD mode enabled, improves overall THD
GENERAL DEVICE FUNCTION
The LM48824 integrates a high efficiency step down (buck) DC-DC switching regulator with a ground reference
headphone amplifier. The switching regulator delivers a constant voltage from an input voltage ranging from 2.4V
to 5.5V. The switching regulator uses a voltage-mode architecture with synchronous rectification, improving
efficiency and reducing component count.
The LM48824 headphone amplifier features TI’s ground referenced architecture that eliminates the large DC-
blocking capacitors required at the outputs of traditional single-ended headphone amplifiers. A low-noise
inverting charge pump creates a negative supply (HPVSS) from the positive supply voltage (VDD). The headphone
amplifiers operate from these bipolar supplies, with the amplifier outputs biased about GND. Because there is no
DC component on the output signals, the large DC-blocking, AC coupling capacitors (typically 220µF) are not
necessary, conserving board space, reducing system cost, and improving frequency response.
CLASS G OPERATION
Class G is a modification of some other class of amplifier (normally Class B or Class AB) to increase efficiency
and reduce power dissipation. Class G works off the fact that musical and voice signals have a high peak to
mean ratio with most of the signal content at low levels. To decrease power dissipation, Class G has multiple
voltage supplies. The LM48824 has two discrete voltage supplies at the output of the buck, 1.1V and 1.8V. When
the output reached the threshold to switch to the higher voltage rails, the rails will switch from 1.1V to 1.8V.
When the output falls below the required voltage rails for a set period of time, it will switch back to the lower rail
until the next time the threshold is reached. Power dissipation is greatly reduced for typical musical or voice
sources. The drawing below shows how a musical output may look. The green lines are the supply voltages at
the output of the buck converter.
Figure 33. Class G Operation
Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LM48824
LM48824
SNAS479D –MARCH 2009–REVISED MAY 2013
www.ti.com
DIFFERENTIAL AMPLIFIER EXPLANATION
The LM48824 features a differential input stage, which offers improved noise rejection compared to a single-
ended input amplifier. Because a differential input amplifier amplifies the difference between the two input
signals, any component common to both signals is cancelled.
SYNCHRONOUS RECTIFIER
The buck converter in the LM48824 uses an internal NFET synchronous rectifier to reduce rectifier forward
voltage drop and associated power loss. Synchronous rectification provides a significant improvement in
efficiency whenever the output voltage is relative low compared to the voltage drop across an ordinary rectifier
diode and eliminating the need for the diode.
CURRENT LIMITING
A current limit of the buck converter in the LM48824 allows the device to protect itself and external components
during overload conditions.
PFM OPERATION
During PFM(Pulse-Frequency Modulation) operation, if the output voltage of the buck converter is below the
‘high’ PFM comparator threshold, the PMOS power switch is turned on. It remains on until the output voltage
reaches the ‘high’ PFM threshold or the peak current exceeds the IPFM level set for PFM mode. The typical peak
current in PFM mode is IPFM = 112mA + VDD/27Ω.
Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps
to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output
voltage is below the ‘high’ PFM comparator threshold, the PMOS switch is again turned on and the cycle is
repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM threshold, the NMOS
switch is turned on briefly to ramp the inductor current to zero and then both output switches are turned off and
the part enters an extremely low power mode.
Figure 34. PFM Operation
SOFT START
The buck converter has a soft-start circuit that limits in-rush current during start-up. During start-up the switch
current limit is increased in steps. Soft start is activated only if global SHDN goes from 1 to 0 after VDD reaches
2.7V. Soft start is implemented by increasing switch current limit in steps of 70mA, 140mA, 280mA, and 750mA
(typical switch current limit). The start-up time thereby depends on the output capacitor and load current of the
buck converter. Typical start-up times with a 10uF output capacitor and 150mA load is 280us and with 5mA load
is 240us.
16 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LM48824
AUDIO
INPUT
COM
COMMON MODE SENSE
EQUIVALENT CIRCUIT
LM48824
www.ti.com
SNAS479D –MARCH 2009–REVISED MAY 2013
COMMON-MODE SENSE
The LM48824 features a ground (common mode) sensing feature. In noisy applications, or where the headphone
jack is used as a line out to other devices, noise pick up and ground imbalance can degrade audio quality. The
LM48824 COM input senses and corrects any noise at the headphone return, or any ground imbalance between
the headphone return and device ground, improving audio reproduction. Connect COM directly to the headphone
return terminal of the headphone jack (Figure 35). No additional external components are required. Connect
COM to GND if the common-mode sense feature is not in use.
Figure 35. COM Connection
SHUTDOWN FUNCTION
The LM48824 features individual amplifier shutdown control and a global device shutdown control.
Bit B0 (SHDN) of the MODE CONTROL register controls the global shutdown for the entire device. Set SHDN =
1 to put the device into current-saving shutdown mode, and set SHDN = 0 for normal operation. SHDN defaults
to 1 at power-up.
Bit B7 (HPL_EN) and Bit B6 (HPR_EN) of the MODE CONTROL register (register address 0x01h) controls the
left and right headphone amplifier shutdown respectively. Set HPL_EN = 0 to set the left channel headphone
amplifier to shutdown and set HPL_EN = 1 to enable left channel operation. Set HPR_EN = 0 to set the right
channel headphone amplifier to shutdown and set HPR_EN = 1 to enable right channel operation. The left and
right channel amplifier shutdowns operate individually.
The LM48824 has a shutdown time of 3ms to complete the internal shutdown sequence. After SHDN is set to 1,
any new I2C commands should only be sent after the 3ms shutdown time to ensure proper operation of the
device.
MUTE FUNCTION
The LM48824 features independent left and right channel mute functions.
Bit B7 (MUTE_L) and Bit B6 (MUTE_R) of the VOLUME CONTROL register (register address 0x02h) controls
the mute function of the left and right channels respectively. Set MUTE_L = 1 to mute the left channel and set
the MUTE_R = 1 to mute the right channel. Set MUTE_L = 0 and MUTE_R = 0 to disable mute on the respective
channels. MUTE_L and MUTE_R defaults to 1 at power-up.
LOW THD+N MODE
The LM48824 features a Low THD mode that reduces THD+N to improve audio qaulity. Set B3 (Low_THD) of
the OUTPUT CONTROL register (register address 0x03h) to 1 to enable the Low THD mode. There is a
quiescent and operating current increase in Low THD mode. See Electrical Characteristics and Typical
Performance Characteristics for reference.
Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LM48824
LM48824
SNAS479D –MARCH 2009–REVISED MAY 2013
www.ti.com
PROPER SELECTION OF EXTERNAL COMPONENTS
INDUCTOR SELECTION
There are two main considerations when choosing an inductor; the inductor saturation current and the inductor
current ripple should be small enough to achieve the desired output voltage ripple. Different saturation current
rating specifications are followed by different manufacturers so attention must be given to details. Saturation
current ratings are typically specified at 25°C, ratings at the maximum ambient temperature of application should
be requested from the manufacturer. Shielded capacitors are preferred since these capacitors radiate less noise.
Inductors with low DCR should also be considered to minimize the efficiency.
Inductor value involves trade-offs in performance. Larger inductors reduce inductor triple current, which typically
means less output voltage ripple (for a given size of output capacitor).
REGULATOR INPUT CAPACITOR SELECTION (C3)
A ceramic input capacitor of 1µF, 6.3V is sufficient for most applications. Place the input capacitor as close as
possible to the VDD pin of the device. A larger value may be used for improved input voltage filtering. Use X7R or
X5R types; do not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting
case sizes like 0805 and 0603.
REGULATOR OUTPUT CAPACITOR SELECTION (C4)
A low ESR ceramic output capacitor of 10µF, 6.3V is sufficient for most applications. Use X7R or X5R types; do
not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like
0805 and 0603. DC bias characteristics vary from manufacturer to manufacturer and dc bias curves should be
requested from them as part of the capacitor selection process.
CHARGE PUMP CAPACITOR SELECTION
Use low ESR ceramic capacitors (less than 100mΩ) for optimum performance.
CHARGE PUMP FLYING CAPACITOR (C1)
The flying capacitor (C1) affects the load regulation and output impedance of the charge pump. A C1 value that
is too low results in a loss of current drive, leading to a loss of amplifier headroom. A higher valued C1 improves
load regulation and lowers charge pump output impedance to an extent. Above 2.2µF, the RDS(ON) of the charge
pump switches and the ESR of C1 and C2 dominate the output impedance. A lower value capacitor can be used
in systems with low maximum output power requirements.
CHARGE PUMP HOLD CAPACITOR (C2)
The value and ESR of the hold capacitor (C2) directly affects the ripple on CPVSS. Increasing the value of C2
reduces output ripple. Decreasing the ESR of C2 reduces both output ripple and charge pump output impedance.
A lower value capacitor can be used in systems with low maximum output power requirements.
Amplifier Input Capacitor Selection
Input capacitors may be required for some applications, or when the audio source is single-ended. Input
capacitors block the DC component of the audio signal, eliminating any conflict between the DC component of
the audio source and the bias voltage of the LM48824. The input capacitors create a high-pass filter with the
input resistors RIN. The -3dB point of the high-pass filter is found using the equation below.
f = 1 / 2πRINCIN (Hz) (1)
Where the value of RIN is given in the Electrical Characteristics VDD = 3.6V.
High-pass filtering the audio signal can be beneficial for some applications. When the LM48824 is using a single-
ended source, power supply noise on the ground is seen as an input signal. Setting the high-pass filter point
above the power supply noise frequencies, 217Hz in a GSM phone, for example, filters out the noise such that it
is not amplified and heard on the output. Capacitors with a tolerance of 10% or better are recommended for
impedance matching and improved CMRR and PSRR.
18 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LM48824
VOLUME
CONTROL OUTPUT LEVEL
DETECT
CHARGE PUMP
REGULATOR
CONTROL
I2C INTERFACE
INL+
INL-
SDA
SCL
INR+
INR-
C1P
C1N
HPVSS
VDD
OUTL
OUTR
COM
GND
CIN
C1
C2
SW
HPVDD
CIN
CIN
CIN
5 k:5 k:
1 PF
1 PF
1 PF
1 PF
1 PF
10 PF
2.2PF
2.2 PF
2.4V to 5.5V
2.3V to 5.5V 3.3 PH
Single-Ended
Audio Input
Single-Ended
Audio Input
C3
C4
LM48824
www.ti.com
SNAS479D –MARCH 2009–REVISED MAY 2013
SINGLE-ENDED AUDIO AMPLIFIER CONFIGURATION
The LM48824 is compatible with single-ended sources. Figure 36 shows the typical single-ended applications
circuit. Input coupling capacitors are required for single-ended configuration.
Figure 36. Single-Ended Input Configuration
PCB LAYOUT CONFIGURATION
Table 7. LM48824TM Demoboard Bill of Materials
Designator Quantity Description
C1 1 10µF ±10% 16V 500ΩTantalum Capacitor (B Case) AVX TPSB106K016R0500
C2 1 1μF ±10% 16V X5R Ceramic Capacitor (603) Panasonic ECJ-1VB1C105K
C3, C8, C9 3 2.2μF ±10% 10V X5R Ceramic Capacitor (603) Panasonic ECJ-1VB1A225K
C4 – C7 4 1μF ±10% 16V X7R Ceramic Capacitor (1206) Panasonic ECJ-3YB1C105K
R1, R2 2 5kΩ±5% 1/10W Thick Film Resistor (603) Vishay CRCW06035R1KJNEA
L1 1 3.3μH ± 30% 1.2A Inductor Murata LQM2MPN3R3NG0L
J1 1 Stereo Headphone Jack
J2 1 16-Pin Boardmount Socket 3M 8516-4500JL
JU1 1 3 Pin Header
JU2 1 2 Pin Header
LM4822TM 1 LM48824TM (16-Bump microSMD)
Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LM48824
LM48824
SNAS479D –MARCH 2009–REVISED MAY 2013
www.ti.com
Revision History
Rev Date Description
1.0 08/06/09 Initial released of the full datasheet.
1.01 08/31/09 Text edits.
D 05/02/2013 Changed layout of National Data Sheet to TI format.
24 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LM48824
PACKAGE OPTION ADDENDUM
www.ti.com 2-May-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
LM48824TM/NOPB ACTIVE DSBGA YFQ 16 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 GL6
LM48824TMX/NOPB ACTIVE DSBGA YFQ 16 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 GL6
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM48824TM/NOPB DSBGA YFQ 16 250 178.0 8.4 1.85 2.01 0.76 4.0 8.0 Q1
LM48824TMX/NOPB DSBGA YFQ 16 3000 178.0 8.4 1.85 2.01 0.76 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 8-May-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM48824TM/NOPB DSBGA YFQ 16 250 210.0 185.0 35.0
LM48824TMX/NOPB DSBGA YFQ 16 3000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 8-May-2013
Pack Materials-Page 2
MECHANICAL DATA
YFQ0016xxx
www.ti.com
TMD16XXX (Rev A)
E
0.600±0.075
D
A
. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
NOTES:
4215081/A 12/12
D: Max =
E: Max =
1.715 mm, Min =
1.715 mm, Min =
1.655 mm
1.655 mm
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