MAX792/MAX820
Microprocessor and Nonvolatile
Memory Supervisory Circuits
________________________________________________________________ Maxim Integrated Products 1
19-0147; Rev. 4; 11/05
General Description
The MAX792/MAX820 microprocessor (µP) supervisory
circuits provide the most functions for power-supply
and watchdog monitoring in systems without battery
backup. Built-in features include the following:
•µP reset: Assertion of RESET and
RESET
outputs during
power-up, power-down, and brownout conditions.
RESET
is guaranteed valid for VCC down to 1V.
•Manual-reset input.
•Two-stage power-fail warning: A separate low-line
comparator compares VCC to a preset threshold
120mV above the reset threshold; the low-line and
reset thresholds can be programmed externally.
•Watchdog fault output: Assertion of
WDO
if the watchdog
input is not toggled within a preset timeout
period.
•Pulsed watchdog output: Advance warning of
impending
WDO
assertion from watchdog timeout that
causes hardware shutdown.
•Write protection of CMOS RAM, EEPROM, or other
memory devices.
The MAX792 and MAX820 are identical, except the
MAX820 guarantees higher low-line and reset threshold
accuracy (±2%).
Applications
Computers
Controllers
Intelligent Instruments
Critical µP Power Monitoring
Features
♦Manual-Reset Input
♦200ms Power-OK/Reset Time Delay
♦Independent Watchdog Timer—Preset or Adjustable
♦On-Board Gating of Chip-Enable Signals
♦Memory Write-Cycle Completion
♦10ns (max) Chip-Enable Gate Propagation Delay
♦Voltage Monitor for Overvoltage Warning
♦±2% Reset and Low-Line Threshold Accuracy
(MAX820, external programming mode)
MAX792
4
5
7
89
1
10
6
14 ADDRESS
DECODER
RESET IN/INT
LLIN/
REFOUT
OVI
SWT
3
VCC
GND
12
MR
RESET
LOW LINE
OVO
CE IN
CE OUT
0.1µF
VCC
RAM
A0-A15
VCC
GND
NMI
RESET
µP
13
Typical Operating Circuit
PART** TEMP. RANGE PIN-PACKAGE
MAX792_CPE 0°C to +70°C 16 Plastic DIP
MAX792_CSE 0°C to +70°C 16 Narrow SO
MAX792_C/D 0°C to +70°C Dice*
SUFFIX RESET THRESHOLD (V)
4.62
4.37
3.06
2.91
2.61
L
M
T
S
R
For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
Ordering Information
Ordering Information continued at end of data sheet.
*Dice are tested at TA= +25°C, DC parameters only.
**These parts offer a choice of five different reset threshold voltages.
Select the letter corresponding to the desired nominal reset threshold
voltage and insert it into the blank to complete the part number.
Devices in PDIP, SO and µMAX packages are available in both lead-
ed and lead-free packaging. Specify lead free by adding the + sym-
bol at the end of the part number when ordering. Lead free not avail-
able for CERDIP package.
MAX792/MAX820
Input Voltage (with respect to GND)
VCC .......................................................................-0.3V to +6V
All Other Inputs.......................................-0.3V to (VCC + 0.3V)
Input Current
GND ................................................................................25mA
All Other Outputs ............................................................25mA
Continuous Power Dissipation (TA= +70°C)
Plastic DIP (derate 10.53mW/°C above +70°C) ..........842mW
Narrow SO (derate 9.52mW/°C above +70°C) ............762mW
CERDIP (derate 10.00mW/°C above +70°C)...............800mW
Operating Temperature Ranges:
MAX792_C__/MAX820_C__ ...............................0°C to +70°C
MAX792_E__/MAX820_E_ _.............................-40°C to +85°C
MAX792_MJE__/MAX820_MJE_ _ .................-55°C to +125°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
2_______________________________________________________________________________________
Microprocessor and Nonvolatile
Memory Supervisory Circuits
PARAMETER
Reset Active Timeout Period
CONDITIONS
MAX820R, TA= +25°C, VCC falling 2.55 2.66
MIN TYP MAX UNITS
VCC rising
MAX820S, TA= +25°C, VCC falling 2.85 2.96
RESET Output Voltage
Reset Threshold Voltage—
Internal Threshold Mode
(VTH)
MAX820T, TA= +25°C, VCC falling 3.00 3.11
V
140 200 280
MAX792, VCC = 5V or VCC = 3V 1.25 1.30 1.35
Reset Threshold Voltage
External Threshold Mode (VTH)MAX820, VCC = 5V or VCC = 3V 1.274 1.30 1.326 V
RESET IN/INT Mode Threshold
(Note 2) Internal threshold mode 60 mV
RESET IN/INT Leakage Current ±0.01 ±25 nA
Reset Threshold Hysteresis 0.016 x VTH V
Reset Comparator Delay VCC falling 70 µs
ms
RESET Output Voltage
ISINK = 50µA, VCC = 1V, VCC falling 0.01 0.3
ISOURCE = 1mA
2.75 V
Supply Current
VCC - 1
ISINK = 1.6mA 0.1 0.4
70 150 µA
ISOURCE = 100µA VCC - 0.5
ISOURCE = 1mA VCC - 1
V
MAX792L, MAX820L
ISOURCE = 100µA
4.50 4.62 4.75
VCC - 0.5
V
MAX792M, MAX820M 4.25 4.37 4.50
MAX792R, MAX820R
ISINK = 1.6mA
2.55 2.61 2.70
0.1 0.4
MAX792S, MAX820S 2.85 2.91 3.00
MAX792T, MAX820T 3.00 3.06 3.15
MAX820L, TA= +25°C, VCC falling 4.55 4.70
MAX820M, TA= +25°C, VCC falling 4.30 4.45
ELECTRICAL CHARACTERISTICS
(VCC = 2.75V to 5.5V, TA= TMIN to TMAX, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
RESET COMPARATOR
Operating Voltage Range
(Note 1)
MAX792/MAX820
_______________________________________________________________________________________ 3
Microprocessor and Nonvolatile
Memory Supervisory Circuits
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.75V to 5.5V, TA= TMIN to TMAX, unless otherwise noted.)
PARAMETER CONDITIONS
ms
MIN TYP MAX UNITS
µA
LOWLINE Short-Circuit Current Output source current, VCC = 5.5V 10 50
SWT connected to VCC, VCC = 5V 1.00 1.60 2.25
SWT connected to VCC, VCC = 3V 1.00 1.60 2.25
4.7nF capacitor connected from SWT to GND,
VCC = 3V 70
Watchdog Timeout Period
4.7nF capacitor connected from SWT to GND,
VCC = 5V
MAX792/MAX820L/M
100
sec
50 120 210
Low-Line Threshold Voltage
(Internal Threshold Mode)—VTH MAX792/MAX820R/S/T
VCC = 5V
40 100 210 mV
100
MAX792, VCC = 5V OR VCC = 3V
Watchdog Input Pulse Width VIL = 0V, VIH = VCC
1.25 1.30 1.35
Low-Line Threshold Voltage
(External Programming Mode)
VCC = 3V
MAX820, VCC = 5V OR VCC = 3V
300 ns
1.274 1.30 1.326 V
Low-Line Hysteresis
(Internal Threshold Mode)
ISINK = 50µA, VCC = 1V, VCC falling
20 mV
0.01 0.30
ISINK = 1.6mA 0.1 0.4
ISOURCE = 1mA VCC - 1
WDO Output Voltage
ISOURCE = 100µA VCC - 0.5
V
ISOURCE = 100µA
WDPO to WDO Delay 70 ns
WDPO Duration 0.5 1.7 6.0 ms
ISINK = 50µA, VCC = 1V, VCC falling 0.01 0.3
ISINK = 1.6mA 0.1 0.4
VIH
ISOURCE = 1mA VCC - 1
WDPO Output Voltage
VIL
VCC - 0.5
V
VIH
0.75 x VCC
VIL
VCC = 4.25V 0.8
0.9 x VCC
WDI Threshold Voltage
VCC = 2.55V 0.2
V
WDI Input Current ±1 µA
LLIN/REFOUT Leakage Current
External Programming Mode ±0.01 ±25 nA
Low-Line Comparator Delay VCC falling 450 µs
ISINK = 3.2mA 0.4
LOWLINE Voltage ISOURCE = 1µA VCC - 1 V
LOW-LINE COMPARATOR
WATCHDOG FUNCTION
MAX792/MAX820
4_______________________________________________________________________________________
Microprocessor and Nonvolatile
Memory Supervisory Circuits
Note 1: The minimum operating voltage is 2.75V; however, the MAX792R and MAX820R are guaranteed to operate down to their
preset reset thresholds.
Note 2: Pulling RESET IN/INT below 60mV selects internal threshold mode and connects the internal voltage divider to the reset
and low-line comparators. External programming mode allows an external resistor divider to set the low-line and reset
thresholds (see Figure 4).
Note 3: The Chip-Enable Propagation delay is measured from the 50% point at CE IN to the 50% point at CE OUT.
PARAMETER CONDITIONS
VCC = 5V or VCC = 3V
MIN TYP MAX UNITS
ISINK = 3.2mA
ISOURCE = 1µA
Output source current, VCC = 5.5V
VOD = 100mV, OVI rising
MR Pull-Up Current
VIH 0.75 x VCC
MR = 0V
VCC = 2.5V
VCC = 4.25V VIL 0.8
1
VIH 0.75 x VCC
CE IN Threshold Voltage
VCC = 2.55V VIL 0.2
V
CE IN Leakage Current
50Ωsource impedance driver,
CLOAD = 50pF
Disabled mode ±0.005 ±1 µA
VCC = 5V
VCC = 3V
VCC = 5V 75 150
610
CE IN to CE OUT Resistance
OVI Input Threshold
Enabled mode VCC = 3V 150 300
1.25 1.30 1.35 V
OVI Leakage Current
Ω
±0.01 ±25 nA
VCC = 5V 0.5 2.5
CE OUT Short-Circuit Current
0.4
OVO Output Voltage
Disabled mode, CEOUT = 0V VCC = 3V 0.05 0.2 0.4
VCC - 1 V
mA
Chip-Enable Propagation Delay
(Note 3)
10 50
813 ns
IOUT = -100µA VCC - 1
Chip-Enable Output Voltage
High (Reset Active) IOUT = 10µA VCC - 0.5 V
Reset Active to CE OUT High VCC falling 15 µs
MR Minimum Pulse Width 25 µs
MR to RESET Propagation Delay 12 µs
MR Threshold Range 1.1 1.3 1.5 V
VCC = 4.25V
to VCC = 5.5V 52380 µA
OVO Short-Circuit Current µA
13
OVI to OVO Delay VOD = 100mV, OVI falling 55 µs
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.75V to +5.5V, TA= TMIN to TMAX, unless otherwise noted.)
MANUAL RESET
CHIP-ENABLE GATING
OVERVOLTAGE COMPARATOR
MAX792/MAX820
Microprocessor and Nonvolatile
Memory Supervisory Circuits
_________________________________________________________________________________________________ 5
400
-60
LOW-LINE COMPARATOR
PROPAGATION DELAY vs. TEMPERATURE
100
300
200
MAX792-3a
TEMPERATURE (°C)
PROPAGATION DELAY (µs)
500
600
-30 0 30 60 90 120 150
VCC = 5V
VCC = 3V
VCC FALLING
15mV OVERDRIVE
EXTERNAL PROGRAMMING MODE
__________________________________________Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
80
0
-60 150
SUPPLY CURRENT vs. TEMPERATURE
20
60
MAX792-1
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
40
10
30
50
70
90
100
-30 0 30 60 90 120
VCC = 2V
VCC = 3V
VCC = 4V
VCC = 5V SWT = VCC
ALL OUTPUTS
UNLOADED
50
40
-60
OVERVOLTAGE COMPARATOR
PROPAGATION DELAY vs. TEMPERATURE
30
MAX792-2
TEMPERATURE (°C)
PROPAGATION DELAY (µs)
60
70
-30 0 30 60 90 120 150
VIH TO VOL
VIN = 20mV
OVERDRIVE = 15mV
40
-60
RESET COMPARATOR
PROPAGATION DELAY vs. TEMPERATURE
50
MAX792-3
TEMPERATURE (°C)
PROPAGATION DELAY (µs)
60
70
60
80
-30 0 30 90 120 150
VCC FALLING
15mV OVERDRIVE
EXTERNAL PROGRAMMING MODE
0
-60
POWER-UP RESET DELAY
vs. TEMPERATURE
100
MAX792-4
TEMPERATURE (°C)
DELAY (ms)
60
300
200
50
150
250
-30 0 30 90 120 150
1.0
NOMINAL WATCHDOG TIMEOUT
PERIOD vs. VCC
MAX792-5
VCC (V)
NOMINAL WATCHDOG TIMEOUT PERIOD (s)
4
3.0
2.0
235
1.5
2.5
MAX792/MAX820
Microprocessor and Nonvolatile
Memory Supervisory Circuits
6_______________________________________________________________________________________
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
100k
10
1n 1m
WATCHDOG TIMEOUT PERIOD
vs. SWT LOAD CAPACITANCE
1k
10k
MAX792-10
CSWT (F)
WATCHDOG TIMEOUT PERIOD (ms)
10n 100n
100
VCC = 5V
VCC = 3V
20
0
025 125 250
CHIP-ENABLE PROPAGATION DELAY
vs. CE OUT LOAD CAPACITANCE
5
15
MAX792-11
CLOAD (pF)
PROPAGATION DELAY (ns)
75 200
10
50 100 150 175 225
VCC = +5V
VCE IN = 0V TO 5V
DRIVER SOURCE
IMPEDANCE = 50Ω
1.25
0120
REF OUT VOLTAGE
vs. TEMPERATURE
MAX792-7
TEMPERATURE (°C)
REF OUT (V)
1.26
1.27
1.28
1.29
1.30
1.31
1.32
1.33
150
906030-30-60
RESET IN / INT = 0V
160
20
060120
CHIP-ENABLE ON-RESISTANCE
vs. TEMPERATURE
40
120
MAX792-8
TEMPERATURE (°C)
ON-RESISTANCE (Ω)
80
180
200
60
100
140
90 15030-30-60
VCC = 5V
VCE IN = 2.5V
0
VCC = 3V
VCE IN = 1.5V
0.900
060 150
INTERNAL-MODE RESET THRESHOLD
vs. TEMPERATURE (NORMALIZED)
MAX792-6
TEMPERATURE (°C)
RESET THRESHOLD
1209030-30-60
0.925
0.950
1.000
1.025
1.050
1.075
1.100
1.125
0.975
THE RESET THRESHOLD IS SHOWN
NORMALIZED TO 1, REPRESENTING
ALL AVAILABLE MAX792/MAX820
MAX792/MAX820
Microprocessor and Nonvolatile
Memory Supervisory Circuits
_______________________________________________________________________________________ 7
______________________________________________________________Pin Description
PIN NAME FUNCTION
1RESET
2RESET Reset is the inverse of RESET.
3V
CC Input Supply Voltage
4RESET IN/INT
5LLIN/REF OUT
6OVO
7OVI
8SWT
9MR
10 LOW LINE
11 WDI
12 GND Ground
13 CE OUT
Active-Low Reset Output goes low whenever VCC falls below the reset threshold in internal thresh-
old programming mode, or RESET IN falls below 1.30V in external threshold programming mode.
RESET remains low for 200ms typ after the threshold is exceeded on power-up.
Reset-Input/Internal-Mode Select. Connect this input to GND to select internal threshold mode.
Select external programming mode by pulling this input 600mV or higher through an external volt-
age divider.
Low-Line Input/Reference Output connects directly to the low-line comparator in external program-
ming mode (RESET IN/INT ≥600mV). Connects directly to the internal 1.30V reference in internal
threshold mode (RESET IN/INT ≤ 60mV).
Overvoltage Comparator Output goes low when OVI is greater than 1.30V. This is an uncommitted
comparator and has no effect on any other internal circuitry.
Inverting Input to the Overvoltage Comparator. When OVI is greater than 1.30V, OVO goes low.
Connect OVI to GND or VCC when not used.
Set Watchdog-Timeout Input. Connect this input to VCC to select the default 1.6sec watchdog
timeout period. Connect a capacitor between this input and GND to select another watchdog-
timeout period. Watchdog timeout period = k x (capacitor value in nF)mV, where k = 27 for
VCC = 5V and k = 16.2 for VCC = 3V. If the watchdog function is unused, connect SWT to VCC.
16 WDPO
15 WDO
14 CE IN
Manual-Reset Input. This input can be tied to an external momentary pushbutton switch, or to a
logic gate output. Internally pulled up to VCC.
Low-Line Output. LOW LINE goes low 120mV above the reset threshold in internal threshold mode,
or when LLIN/REFOUT goes below 1.30V in external programming mode.
Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout period,
WDPO pulses low and WDO goes low. WDO remains low until the next transition at WDI. Connect to
GND or VCC if unused.
Chip-Enable Output. CE OUT goes low only when CE IN is low and reset is not asserted. If CE IN is
low when reset is asserted, CE OUT will stay low for 15µs or until CE IN goes high, whichever
occurs first.
Chip-Enable Input—the input to the chip-enable transmission gate. Connect to GND or VCC if not
used.
Watchdog Output. WDO goes low if WDI remains either high or low longer than the watchdog time-
out period. WDO returns high on the next transition at WDI.
Watchdog-Pulse Output. Upon the absence of a transition at WDI, WDPO will pulse low for a mini-
mum of 500µs. WDPO precedes WDO by typically 70ns.
MAX792/MAX820
Microprocessor and Nonvolatile
Memory Supervisory Circuits
8_______________________________________________________________________________________
Detailed Description
Manual-Reset Input
Many µP-based products require manual-reset capabil-
ity, allowing the operator to initiate a reset. The manu-
al/external-reset input (
MR) ca
n connect directly to a
switch without an external pull-up resistor or debounc-
ing network.
MR
internally connects to a 1.30V com-
parator, and has a high-impedance pull-up to VCC, as
shown in Figure 1. The propagation delay from assert-
ing
MR
to reset asserted is typically 12µs. Pulsing
MR
low for a minimum of 25µs asserts the reset function
(see Reset Function section). The reset output remains
active as long as
MR
is held low, and the reset timeout
period begins after
MR
returns high (Figure 2). To pro-
vide extra noise immunity in high-noise environments,
pull
MR
up to VCC with a 100kΩresistor.
Use
MR
as either a digital logic input or as a second low-
line comparator. Normal TTL/CMOS levels can be
wire-OR connected via pull-down diodes (Figure 3),
and open-drain/collector outputs can be wire-ORed
directly.
Monitoring the Regulated Supply
The MAX792/MAX820 offer two modes for monitoring
the regulated supply and providing reset and non-
maskable interrupt (NMI) signals to the µP: internal
threshold mode uses the factory preset low-line and
reset thresholds, and external programming mode
allows the low-line and reset thresholds to be pro-
grammed externally using a resistor voltage divider
(Figure 4).
Internal Threshold Mode
Connecting the reset-input/internal-mode select pin
(RESET IN
/INT
) to ground selects internal threshold
mode (Figure 4a). In this mode, the low-line and reset
thresholds are factory preset by an internal voltage
divider (Figure 1) to the threshold voltages specified in
the Electrical Characteristics (Reset Threshold Voltage
and Low-Line Threshold Voltage). Connect the low-line
output (
LOWLINE
) to the µP NMI pin, and connect the
active-high reset output (RESET) or active-low reset
output
(RESET
) to the µP reset input pin.
Additionally, the low-line input/reference-output pin
(LLIN/REFOUT) connects to the internal 1.30V refer-
ence in internal threshold mode. Buffer LLIN/REFOUT
with a high-impedance buffer to use it with external
circuitry. In this mode, when VCC is falling,
LOWLINE
is
guaranteed to be asserted prior to reset assertion.
External Programming Mode
Connecting RESET IN
/INT
to a voltage above 600mV
selects external programming mode. In this mode, the
low-line and reset comparators disconnect from the inter-
nal voltage divider and connect to LLIN/REFOUT and
RESET IN
/INT
, respectively (Figure 1). This mode allows
flexibility in determining where in the operating voltage
range the NMI and reset are generated. Set the low-line
and reset thresholds with an external resistor divider, as in
Figure 4b or Figure 4c. RESET typically remains valid for
VCC down to 2.5V;
RESET
is guaranteed to be valid with
VCC down to 1V.
Calculate the values for the resistor voltage divider in
Figure 4b using the following equations:
1) R3 = (1.30 x VCC MAX)/(VLOW LINE x IMAX)
2) R2 = [(1.30 x VCC MAX)/(VRESET x IMAX)] - R3
3) R1 = (VCC MAX/IMAX) - (R2 + R3).
First choose the desired maximum current through the
voltage divider (IMAX) when VCC is at its highest (VCC
MAX). There are two things to consider here. First, IMAX
contributes to the overall supply current for the circuit, so
you would generally make it as small as possible.
Second, IMAX cannot be too small or leakage currents will
adversely affect the programmed threshold voltages; 5µA
is often appropriate. Determine R3 after you have chosen
IMAX. Use the value for R3 to determine R2, then use both
R2 and R3 to determine R1.
For example, to program a 4.75V low-line threshold and a
4.4V reset threshold, first choose IMAX to be 5µA when
VCC = 5.5V and substitute into equation 1.
R3 = (1.30 x 5.5)/(4.75 x 5E-6) = 301.05kΩ.
301kΩis the nearest standard 0.1% value. Substitute
into equation 2:
R2 = [(1.30 x 5.5)/(4.4 x 5E-6)] - 301kΩ= 23.95kΩ.
The nearest 0.1% resistor value is 23.7kΩ. Finally, sub-
stitute into equation 3:
R1 = (5.5/5E-6) - (23.7kΩ+ 301kΩ) = 775kΩ.
The nearest 0.1% value resistor is 787kΩ. Determine the
actual low-line threshold by rearranging equation 1 and
plugging in the standard resistor values. The actual low-
line threshold is 4.75V and the actual reset threshold is
4.40V. An additional resistor allows the MAX792/MAX820
to monitor the unregulated supply and provide an NMI
before the regulated supply begins to fall (Figure 4c).
Both of these thresholds will vary from circuit to circuit
with resistor tolerance, reference variation, and compara-
tor offset variation. The initial thresholds for each circuit
will also vary with temperature due to reference and off-
set drift. For highest accuracy, use the MAX820.
MAX792/MAX820
Microprocessor and Nonvolatile
Memory Supervisory Circuits
_______________________________________________________________________________________ 9
MAX792
MAX820
INTERNAL/
EXTERNAL
MODE
CONTROL
CHIP-ENABLE
OUTPUT
CONTROL
RESET
GENERATOR
TIMEBASE FOR
RESET AND
WATCHDOG
VCC
WATCHDOG
TIMER
WATCHDOG
TRANSITION
DETECTOR
OVERVOLTAGE
COMPARATOR
P
N
INTERNAL
EXTERNAL
60mV
VCC
VCC
VCC
1.30V
LOW-LINE
COMPARATOR
MANUAL
RESET
COMPARATOR
RESET
COMPARATOR
VCC
VCC
P
VCC
*
4
5
9
14
8
11
7
6
15
16
13
10
1
2
3
RESET
RESET
LOW LINE
CE OUT
WDPO
WDO
OVO
12
GND
OVI
WDI
SWT
CE IN
MR
LLIN/
REFOUT
RESET IN/
INT
VCC
* SWITCHES ARE SHOWN IN INTERNAL
THRESHOLD MODE POSITION
Figure 1. MAX792/MAX820 Block Diagram
MAX792/MAX820
Microprocessor and Nonvolatile
Memory Supervisory Circuits
10 ______________________________________________________________________________________
Low-Line Output
In internal threshold mode, the low-line comparator
monitors VCC with a threshold voltage typically 120mV
above the reset threshold, and with 15mV of hysteresis.
For normal operation (VCC above the reset threshold),
LOWLINE
is pulled to VCC. Use
LOWLINE
to provide an NMI
to the µP, as described in the previous section, when
VCC begins to fall (Figure 4).
Reset Function
The MAX792/MAX820 provide both RESET and
RESET
outputs. The RESET and
RESET
outputs ensure that the
µP powers up in a known state, and prevent code-exe-
cution errors during power-up, power-down, or
brownout conditions.
The reset function will be asserted during the following
conditions:
1) VCC less than the programmed reset threshold.
2)
MR
less than 1.30V typ.
3) Reset remains asserted for 200ms typ after VCC
rises above the reset threshold or after
MR
has
exceeded 1.30V typ.
When reset is asserted, all the internal counters are
reset, the watchdog output (
WDO)
and watchdog-pulse
output
(WDPO)
are set high, and the set watchdog-time-
out input (SWT) is set to (VCC - 0.6V) if it is not already
connected to VCC (for internal timeouts). The chip-
enable transmission gate is also disabled while reset is
asserted; the chip-enable input (
CE
IN) becomes high
impedance and the chip-enable output (
CE
OUT) is
pulled up to VCC.
MR
RESET
CE IN OV
CE OUT
25µs MIN
12µs TYP
15µs TYP
Figure 2. Manual-Reset Timing Diagram
MAX792
MAX820
MANUAL RESET
OTHER
RESET
SOURCES
9MR
*
*
*
.
.
.
DIODES NOT REQUIRED ON OPEN-DRAIN OUTPUTS
Figure 3. Diode "OR" connections allow multiple reset sources
to connect to
MR
.
MAX792
12
GND
3
VCC
LLIN/REFOUT
RESET
RESET
LOW LINE
RESET IN/INT
4
5
2
10
1
TO µP
TO µP
TO µP NMI
VIN
Figure 4a. Connection for Internal Threshold Mode
MAX792
GND
VCC
TO µP
TO µP
TO µP NMI
2
1
10
RESET IN/INT
LLIN/REFOUT
RESET
RESET
LOW LINE
12
VIN
R3 = 1.30V x VCC MAX
VLOW LINE x IMAX
R2 = 1.30V x VCC MAX
VRESET x IMAX
– R3
R1 = VCC MAX
IMAX – (R2 + R3)
IMAX = THE MAXIMUM DESIRED CURRENT
THROUGH THE VOLTAGE DIVIDED.
3
R3
R2
R1
Figure 4b. Connection for External Threshold Programming Mode
MAX792/MAX820
Microprocessor and Nonvolatile
Memory Supervisory Circuits
______________________________________________________________________________________ 11
Reset Outputs (RESET and
RESET
)
The
RESET
output is active low and typically sinks 1.6mA
at 0.1V. When deasserted,
RESET
sources 1.6mA at typi-
cally VCC - 1.5V. The RESET output is the inverse of
RESET.RESET
is guaranteed to be valid down to VCC = 1V,
and an external 10kΩpull-down resistor on
RESET
ensures that it will be valid with VCC down to GND
(Figure 5). As VCC goes below 1V, the gate drive to the
RESET
output switch reduces accordingly, increasing the
rDS(ON) and the saturation voltage. The 10kΩpull-down
resistor ensures that the parallel combination of switch
plus resistor will be around 10kΩand the saturation
voltage will be below 0.4V while sinking 40µA. When
using an external pull-down resistor of 10kΩ, the high
state for the
RESET
output with VCC = 4.75V is typically
4.60V.
Overvoltage Comparator
The overvoltage comparator is an uncommitted com-
parator that has no effect on the operation of other chip
functions. Use this input to provide overvoltage indica-
tion by connecting a voltage divider from the input sup-
ply, as in Figure 6.
Connect OVI to ground if the overvoltage function is not
used.
OVO
goes low when OVI goes above 1.30V. With
OVI below 1.30V,
OVO
is actively pulled to VCC and can
source1µA.
Watchdog Function
The watchdog monitors µP activity via the watchdog
input (WDI). If the µP becomes inactive,
WDO
and
WDPO
are asserted. To use the watchdog function, connect
WDI to a µP bus line or I/O line. If WDI remains high or
low for longer than the watchdog timeout period (1.6s
nominal),
WDPO
and
WDO
are asserted, indicating a soft-
ware fault condition (see Watchdog-Pulse Output and
Watchdog Output sections).
Watchdog Input
If the watchdog function is unused, connect WDI to VCC
or GND. A change of state (high-to-low, low-to-high, or
a minimum 100ns pulse) at WDI during the watchdog
period resets the watchdog timer. The watchdog timer
MAX792
MAX820
GND
VCC
REGULATOR
R1
R2
R3
R4
TO µP
TO µP
TO µP NMI
2
1
10
RESET IN/INT
LLIN/REFOUT
RESET
RESET
LOW LINE
VLOW LINE = 1.3 R1 + R2
R2 )
(
VRESET = 1.3 R3 + R4
R4 )
(
Figure 4c. Alternative Connection for External Programming Mode
RESET
MAX792
MAX820
TO µP RESET
1
10k
Figure 5. Adding an external pull-down resistor ensures
RESET
is valid with VCC down to GND.
MAX792
MAX820
6
7
12
GND
3
VCC
OVI
OVO OVERVOLTAGE
VOLTAGE REGULATOR
1.30V
Figure 6. Detecting an Overvoltage Condition
MAX792/MAX820
Microprocessor and Nonvolatile
Memory Supervisory Circuits
12 ______________________________________________________________________________________
default is 1.6s. Select alternative timeout periods by
connecting an external capacitor from SWT to GND
(see Selecting an Alternative Watchdog Timeout sec-
tion). When VCC is below the reset threshold, the watch-
dog function is disabled.
Watchdog Output
WDO
remains high if there is a transition or pulse at WDI
during the watchdog timeout period. The watchdog
function is disabled and
WDO
is a logic high when VCC
is below the reset threshold. If a system reset is desired
on every watchdog fault, simply diode-OR connect
WDO
to
MR
(Figure 8). When a watchdog fault occurs in this
mode,
WDO
goes low, pulling
MR
low and causing a
reset pulse to be issued. As soon as reset is asserted,
the watchdog timer clears and
WDO
goes high. With
WDO
connected to
MR
, a continuous high or low on WDI
will cause 200ms reset pulses to be issued every
1.6sec (SWT connected to VCC). When reset is not
asserted, if no transition occurs at WDI during the
watchdog timeout period,
WDO
goes low 70ns after the
falling edge of
WDPO
and remains low until the next tran-
sition at WDI (Figure 7). A single additional flip-flop can
force the system into a hardware shutdown if there are
two successive watchdog faults (Figure 8). When the
MAX792/MAX820 are operated from a 5V supply,
WDO
has a 2 x TTL output characteristic.
Watchdog-Pulse Output
As described in the preceding section,
WDPO
can be
used as the clock input to an external D flip-flop. Upon
the absence of a watchdog edge or pulse at WDI at the
end of a watchdog timeout period,
WDPO
will pulse low
for 1.7ms. The falling edge of
WDPO
precedes
WDO
by
70ns. Since
WDO
is high when
WDPO
goes low, the flip-
flop’s Q output remains high after
WDO
goes low (Figure
8). If the watchdog timer is not reset by a transition at
WDI,
WDO
remains low and the next
WDPO
following a
second watchdog timeout period clocks a logic low to
the Q output, pulling
MR
low and causing the
MAX792/MAX820 latch in reset. If the watchdog timer is
reset by a transition at WDI,
WDO
will go high and the
flip-flop’s Q output will remain high. Thus a system
shutdown is only caused by two successive watchdog
faults.
Selecting an Alternative Watchdog Timeout Period
The SWT input controls the watchdog timeout period.
Connecting SWT to VCC selects the internal 1.6sec
watchdog timeout period. Select an alternative watch-
dog timeout period by connecting a capacitor between
SWT and GND. Do not leave SWT floating and do not
connect it to ground. The following formula determines
the watchdog timeout period:
Watchdog Timeout Period =
k x (capacitor value in nF)ms
where k = 27 for VCC = 3V, and k = 16.2 for VCC = 5V.
This applies for capacitor values in excess of 4.7nF. If
the watchdog function is unused, connect SWT to VCC.
WDPO
WDO
WDI
70ns
1.6s
MIN 100ns (VCC = 5V)
MIN 300ns (VCC = 3V)
VCC = 5V
Figure 7. WDI,
WDO,
and
WDPO
Timing Diagram
MAX792
MAX820
* FOR SYSTEM RESET ON EVERY
WATCHDOG FAULT, OMIT THE
FLIP-FLOP, AND DIODE–OR
CONNECT WDO TO MR.
12
GND
3
VCC
VCC
0.1µF
9MR
4.7k
+5V
1
RESET
0.1µF
11
WDI
16
WDPO
15
WDO
µP POWER
VCC
RESET
I/O
DCLOCK
CLEAR
Q
Q
VCC
TWO
CONSECUTIVE
WATCHDOG
FAULT
INDICATION
REACTIVATE
*
Figure 8. Two consecutive watchdog faults latch the system in
reset.
MAX792/MAX820
Microprocessor and Nonvolatile
Memory Supervisory Circuits
______________________________________________________________________________________ 13
Chip-Enable Signal Gating
The MAX792/MAX820 provide internal gating of chip-
enable (CE) signals, which prevents erroneous data
from corrupting CMOS RAM in the event of an under-
voltage condition. The MAX792/MAX820 use a series
transmission gate from
CE
IN to
CE
OUT (Figure 1).
During normal operation (reset not asserted), the CE
transmission gate is enabled and passes all CE transi-
tions. When reset is asserted, this path becomes dis-
abled, preventing erroneous data from corrupting the
CMOS RAM. The 10ns max CE propagation delay from
CE
IN to
CE
OUT enables the MAX792/MAX820 to be
used with most µPs. If
CE
IN is low when reset asserts,
CE
OUT remains low for a short period to permit com-
pletion of the current write cycle.
Chip-Enable Input
The CE transmission gate is disabled and
CE
IN is high
impedance (disabled mode) while reset is asserted.
During a power-down sequence when VCC passes the
reset threshold, the CE transmission gate disables and
CE
IN immediately becomes high impedance if the volt-
age at
CE
IN is high. If
CE
IN is low when reset is assert-
ed, the CE transmission gate will disable at the moment
CE
IN goes high or 15µs after reset is asserted,
whichever occurs first (Figure 9). This permits the cur-
rent write cycle to complete during power-down.
During a power-up sequence, the CE transmission gate
remains disabled and
CE
IN remains high impedance
regardless of
CE
IN activity, until reset is deasserted fol-
lowing the reset timeout period.
While disabled,
CE
IN is high impedance. When the CE
transmission gate is enabled, the impedance of
CE
IN
will appear as a 75Ω(VCC = 5V) resistor in series with
the load at
CE
OUT.
The propagation delay through the CE transmission
gate depends on VCC, the source impedance of the
drive connected to
CE
IN, and the loading on
CE
OUT
(see the Chip-Enable Propagation Delay vs.
CE
OUT
Load Capacitance graph in the Typical Operating
Characteristics). The CE propagation delay is produc-
tion tested from the 50% point on
CE
IN to the 50%
point on
CE
OUT using a 50Ωdriver and 50pF of load
capacitance (Figure 10). For minimum propagation
delay, minimize the capacitive load at
CE
OUT, and use
a low-output-impedance driver.
Chip-Enable Output
When the CE transmission gate is enabled, the imped-
ance of
CE
OUT is equivalent to 75Ωin series with the
source driving
CE
IN. In the disabled mode, the 75Ω
transmission gate is off and an active pull-up connects
from
CE
OUT to VCC. This source turns off when the
transmission gate is enabled.
Applications Information
Connect a 0.1µF ceramic capacitor from VCC to GND,
as close to the device pins as possible. This reduces
the probability of resets due to high-frequency power-
supply transients. In a high-noise environment, addi-
tional bypass capacitance from VCC to ground may be
required. If long leads connect to the chip inputs,
ensure that these lines are free from ringing, etc., which
would forward bias the chip’s protection diodes.
VCC
CE IN
RESET
THRESHOLD
CE OUT
RESET
RESET
70µs
15µs
70µs
Figure 9. Reset and Chip-Enable Timing
MAX792
MAX820
50Ω DRIVER
1314
12
+5V
GND
CLOAD
3
VCC
CE IN CE OUT
Figure 10. CE Propagation Delay Test Circuit
MAX792/MAX820
Microprocessor and Nonvolatile
Memory Supervisory Circuits
14 ______________________________________________________________________________________
Alternative Chip-Enable Gating
Using memory devices with both CE and
CE
inputs
allows the MAX792/MAX820 CE propagation delay
to be bypassed. To do this, connect
CE
IN to ground,
pull up
CE
OUT to VCC, and connect
CE
OUT to the
CE
input of each memory device (Figure 11). The CE input
of each memory device then connects directly to the
chip-select logic, which does not have to be gated by
the MAX792/MAX820.
Interfacing to µPs with Bidirectional
Reset Inputs
µPs with bidirectional reset pins, such as the Motorola
68HC11 series, can contend with the MAX792/MAX820
RESET
output. If, for example, the MAX792/MAX820
RESET
output is asserted high and the µP wants to pull it low,
indeterminate logic levels may result. To avoid this,
connect a 4.7kΩresistor between the MAX792/MAX820
RESET
output and the µP reset I/O, as in Figure 12.
Buffer the MAX792/MAX820
RESET
output to other sys-
tem components.
Negative-Going VCC Transients
While issuing resets to the µP during power-up, power-
down, and brownout conditions, these supervisors are
relatively immune to short-duration negative-going VCC
transients (glitches). It is usually undesirable to reset
the µP when VCC experiences only small glitches.
Figure 13 shows maximum transient duration vs. reset-
comparator overdrive, for which reset pulses are not
generated. The graph was produced using negative-
going VCC pulses, starting at 5V and ending below the
reset threshold by the magnitude indicated (reset-
comparator overdrive). The graph shows the maximum
pulse width a negative-going VCC transient may typi-
cally have without causing a reset pulse to be issued.
As the amplitude of the transient increases (i.e., goes
farther below the reset threshold), the maximum allow-
able pulse width decreases. Typically, a VCC transient
that goes 100mV below the reset threshold and lasts for
30µs or less will not cause a reset pulse to be issued.
A 100nF bypass capacitor mounted close to the VCC
pin provides additional transient immunity.
MAX792
MAX820
1314
12
+5V
GND
3
VCC
CE IN CE OUT
CE
CE
CE
CE
CE
CE
CE
CE
RAM 1
RAM 2
RAM 3
RAM 4
ACTIVE-HIGH CE
LINES FROM LOGIC
MAXIMUM RP VALUE DEPENDS ON
THE NUMBER OF RAMS.
MINIMUM RP VALUE IS 1kΩ
*
RP*
Figure 11. Alternate CE Gating
VCC
VCC VCC
BUFFER
TO OTHER
SYSTEM RESET
INPUTS
4.7k
1RESET
RESET
GND
GND
12
MAX792
MAX820
µP
3
Figure 12. Interfacing to µPs with Bidirectional
RESET
Pins
Figure 13. Maximum Transient Duration Without Causing a
Reset Pulse vs. Reset-Comparator Overdrive
100
0
10 100 10,000
40
20
80
60
MAX791 -13
RESET COMPARATOR OVERDRIVE, (VTH - VCC) (mV)
MAXIMUM TRANSIENT DURATION (µs)
1000
VCC = 5V
TA = +25°C
SUFFIX RESET THRESHOLD (V)
L
M
T
S
R
4.62
4.37
3.06
2.91
2.61
MAX792/MAX820
Microprocessor and Nonvolatile
Memory Supervisory Circuits
______________________________________________________________________________________ 15
_Ordering Information (continued)
Pin Configuration
PART** TEMP. RANGE PIN-PACKAGE
MAX792_EPE -40°C to +85°C 16 Plastic DIP
MAX792_ESE -40°C to +85°C 16 Narrow SO
MAX792_EJE -40°C to +85°C 16 CERDIP
MAX792_MJE -55°C to +125°C 16 CERDIP
MAX820_CPE -0°C to +70°C 16 Plastic DIP
MAX820_CSE -0°C to +70°C 16 Narrow SO
MAX820_EPE -40°C to +85°C 16 Plastic DIP
MAX820_ESE -40°C to +85°C 16 Narrow SO
MAX820_EJE -40°C to +85°C 16 CERDIP
MAX820_MJE -55°C to +125°C 16 CERDIP
MR
SWTOVI
0.078"
(1.981mm)
0.070"
(1.778mm)
RESET IN/
INT
LLIN/
REF OUT
OVO
LOW LINE
WDI
GND
CE OUT
RESET
RESET
WDPO
WDO
VCC
CE IN
___________________Chip Topography
TRANSISTOR COUNT: 950
SUBSTRATE CONNECTED TO VCC
*Dice are tested at TA= +25°C, DC parameters only.
**These parts offer a choice of five different reset threshold volt-
ages. Select the letter corresponding to the desired nominal
reset threshold voltage and insert it into the blank to complete
the part number.
Devices in PDIP, SO and µMAX packages are available in both
leaded and lead-free packaging. Specify lead free by adding
the + symbol at the end of the part number when ordering. Lead
free not available for CERDIP package.
MAX792/MAX820
Microprocessor and Nonvolatile
Memory Supervisory Circuits
________________________________________________________Package Information
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
©2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
SOICN .EPS
PACKAGE OUTLINE, .150" SOIC
1
1
21-0041 B
REV.DOCUMENT CONTROL NO.APPROVAL
PROPRIETARY INFORMATION
TITLE:
TOP VIEW
FRONT VIEW
MAX
0.010
0.069
0.019
0.157
0.010
INCHES
0.150
0.007
E
C
DIM
0.014
0.004
B
A1
MIN
0.053A
0.19
3.80 4.00
0.25
MILLIMETERS
0.10
0.35
1.35
MIN
0.49
0.25
MAX
1.75
0.050
0.016L0.40 1.27
0.3940.386D
D
MINDIM
D
INCHES
MAX
9.80 10.00
MILLIMETERS
MIN MAX
16 AC
0.337 0.344 AB8.758.55 14
0.189 0.197 AA5.004.80 8
NMS012
N
SIDE VIEW
H0.2440.228 5.80 6.20
e0.050 BSC 1.27 BSC
C
HE
eBA1
A
D
0∞-8∞
L
1
VARIATIONS:
SOICW.EPS
PACKAGE OUTLINE, .300" SOIC
1
1
21-0042 B
REV.DOCUMENT CONTROL NO.APPROVAL
PROPRIETARY INFORMATION
TITLE:
TOP VIEW
FRONT VIEW
MAX
0.012
0.104
0.019
0.299
0.013
INCHES
0.291
0.009
E
C
DIM
0.014
0.004
B
A1
MIN
0.093A
0.23
7.40 7.60
0.32
MILLIMETERS
0.10
0.35
2.35
MIN
0.49
0.30
MAX
2.65
0.050
0.016L0.40 1.27
0.5120.496D
D
MINDIM
D
INCHES
MAX
12.60 13.00
MILLIMETERS
MIN MAX
20 AC
0.447 0.463 AB11.7511.35 18
0.398 0.413 AA10.5010.10 16
NMS013
SIDE VIEW
H0.4190.394 10.00 10.65
e0.050 1.27
D0.6140.598 15.20 2415.60 AD
D0.7130.697 17.70 2818.10 AE
H
E
N
D
A1
B
e
A
0∞-8∞
C
L
1
VARIATIONS: