PCK12429 25-800 MHz Differential PECL Clock Generator Family The PCK12429 provides a fully integrated crystal oscillator, PLL with integrated loop filter, and programmable frequency divider ratios to generate a high-quality, low-jitter differential 25 GND 26 TEST 27 VCC 28 VCC 29 GND 30 FOUT 31 FOUT 32 VCC PECL output clock from an external quartz crystal reference. S_CLOCK 1 Semiconductors 24 NC S_DATA 2 23 N[1] S_LOAD 3 22 N[0] PLL-VCC 4 PCK12429BD PLL-VCC 5 20 M[7] N/C 16 M [3] 15 M [2] 14 17 M[4] M [1] 13 18 M[5] M [0] 12 NC 7 XTAL1 8 P_LOAD 11 19 M[6] OE 10 NC 6 XTAL2 9 Description 21 M[8] Features * * * * * One 25-400 MHz differential PECL clock output 25 ps peak-to-peak output jitter Fully integrated PLL and loop filter - no external components needed Integrated series-resonant crystal oscillator - no external components needed besides crystal Frequency programmable to 1 MHz or finer resolution Parallel or 3-wire serial programming interface Synchronous output enable Synchronous frequency ramp-down on power-down (PCK12439) Offered in 28-pin PLCC, 32-pin LQFP and 28-pin SO packages Pin Configuration 26 XTAL2 4 25 XTAL1 M [4] 5 24 NC 25 VCC M [5] 6 23 NC OE 6 24 FOUT M [6] 7 22 PLL-VCC P_LOAD 7 23 FOUT M [7] 8 21 S_LOAD M [8] 9 20 S_DATA N [0] 10 19 S_CLOCK N [1] 11 18 VCC GND 12 17 FOUT TEST 13 16 FOUT VCC 14 15 GND 26 S_CLOCK 3 M [3] 27 S_DATA M [2] 1 PLL-VCC VCC 28 S_LOAD P_LOAD 27 2 NC 28 2 3 NC 1 4 XTAL1 M [0] M [1] XTAL2 5 M [0] 8 PCK12429A 22 GND N[1] 18 N[0] 17 M[8] 16 M[7] 15 19 GND M[6] 14 20 TEST M [3] 11 M[5] 13 21 VCC M [2] 10 M[4] 12 M [1] 9 PCK12429D * * * * Order Information Package SO LQFP PLCC Container Tube T&R T&R Tray, single Tray, multiple Tube T&R PCK12429 PCK12429D PCK12429D-T PCK12429BD-T PCK12429BD PCK12429BD PCK12429A PCK12429A-T The PCK12429 uses an external quartz crystal reference frequency with an input range of 10-20 MHz to generate one output with a frequency between 25 and 400 MHz, programmable through either serial or parallel interface. In the typical case of a 16 MHz crystal, the PCK12429 derives an internal reference frequency of 1 MHz, which drives an internal PLL. The loop divider ratio, M, is programmable between 200 and 400 to create a VCO output frequency between 200 MHz and 400 MHz. The VCO output frequency can then be further divided by the output divider ratio N, which can be programmed to values of 1, 2, 4 or 8, for an overall output frequency range of 25 MHz (M=200, N=8) up to 400 MHz (M=400, N=1). The PCK12429 has a fully integrated PLL loop filter and uses a pure series-resonant crystal oscillator, eliminating the need for external components. It uses separate voltage supplies to minimize noise-induced jitter. The resulting output is a high-quality differential PECL output clock signal with extremely low jitter of 25 ps peak-to-peak. Frequency lock is achieved in less than 10 ms with minimal frequency overshoot. The basic function in this family is PCK12429, programmable from 25 MHz to 400 MHz. PCK12429S adds spread spectrum capability. For operation from 50 MHz to 800 MHz, PCK12430 can be used, or PCK12439 which adds a gradual frequency step-down function supporting system power-down modes. Applications * * * High-performance UNIX computing platforms IA-64 ItaniumTM 2 architecture server motherboards High-performance PECL reference clock generation Operating Characteristics * * * * Operates from a 3.3 V power supply 0C to +70C operating temperature range Input crystal frequency range between 10 MHz and 20 MHz Serial programming interface operates at up to 10 MHz PCK12429S PCK12429SD PCK12429SD-T PCK12429SBD-T PCK12429SBD PCK12429SBD PCK12429SA PCK12429SA-T PCK12430 PCK12430D PCK12430D-T PCK12430BD-T PCK12430BD PCK12430BD PCK12430A PCK12430A-T PCK12439 PCK12439D PCK12439D-T PCK12439BD-T PCK12439BD PCK12439BD PCK12439A PCK12439A-T PCK12429 25-800 MHz Differential PECL Clock Generator Family w w w. s e m i c o n d u c t o r s . p h i l i p s . c o m Functional Block Diagram Example of a PECL Clock Tree Using PCK12429 with Several Clock Distribution ICs PCK12429/29S/30/39 PCK111 1:10 FOUT 1-1 FOUT 1-2 FOUT 1-10 16 MHz Crystal Oscillator DIV 16 DIV N PLL FOUT PCK12429 25..400MHz FOUT PCKEP14 1:5 synchronous output enable DIV M FOUT 1 FOUT 2 FOUT 3 FOUT 4 FOUT 5 PCK111 1:10 FOUT 2-1 FOUT 2-2 FOUT 2-10 FOUT 4-1 Serial Data Programming Interface PCK210 2x1:5 M (9 bits) FOUT 5-5 N (2 bits) Jitter Performance as a Function of Output Frequency Divider ratios and output frequency ranges* 25 N Output Division Ratio 00 1 01 2 10 4 20 RMS jitter [ps] RMS jitter [ps] 6.25 ps reference (1-sigma) 15 10 6.25 5 11 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 1 1001 0000 ... 0 1100 1000 1 1001 0000 ... 0 1100 1000 1 1001 0000 ... 0 1100 1000 1 1001 0000 ... 0 1100 1000 PLL Division Ratio 400 ... 200 400 ... 200 400 ... 200 400 ... 200 Output Frequency 400 ... 200 200 ... 100 100 Frequency Step Increment 1 MHz 500 kHz 250 kHz 50 50 125 kHz 25 Philips Semiconductors Family Overview PCK12430 PCK12439 8 M * using a 16 MHz crystal as an example reference frequency Output Frequency [MHz] Part Number PCK12429 PCK12429S FOUT 4-5 FOUT 5-1 Function 25-400 MHz differential PECL clock 25-400 MHz differential PECL clock with spread spectrum 50-800 MHz differential PECL clock 50-800 MHz differential PECL clock with frequency ramp-down mode generator generator generator generator Philips Semiconductors is a worldwide company with over 100 sales offices in more than 50 countries. For a complete up-to-date list of our sales offices please e-mail sales.addresses@www.semiconductors.philips.com. A complete list will be sent to you automatically. You can also visit our website http://www.semiconductors.philips.com/sales (c) Koninklijke Philips Electronics N.V. 2002 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: August 2002 document order number: 9397 750 10201 Published in U.S.A.