74AC08, 74ACT08 — Quad 2-Input AND Gate
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC08, 74ACT08 Rev. 1.5.1
January 2008
74AC08, 74ACT08
Quad 2-Input AND Gate
Features
■
I
CC
reduced by 50% on 74AC only
■
Outputs source/sink 24mA
General Description
The AC08/ACT08 contains four, 2-input AND gates.
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Connection Diagram
Pin Description
Logic Symbol
IEEE/IEC
Order
Number
Package
Number Package Description
74AC08SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74AC08SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC08MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74AC08PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74ACT08SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74ACT08MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74ACT08PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Pin Names Description
A
n
, B
n
Inputs
O
n
Outputs
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC08, 74ACT08 Rev. 1.5.1 2
74AC08, 74ACT08 — Quad 2-Input AND Gate
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol Parameter Rating
V
CC
Supply Voltage –0.5V to +7.0V
I
IK
DC Input Diode Current
V
I
=
–0.5V –20mA
V
I
=
V
CC
+ 0.5 +20mA
V
I
DC Input Voltage –0.5V to V
CC
+ 0.5V
I
OK
DC Output Diode Current
V
O
=
–0.5V –20mA
V
O
=
V
CC
+ 0.5V +20mA
V
O
DC Output Voltage –0.5V to V
CC
+ 0.5V
I
O
DC Output Source or Sink Current ±50mA
I
CC
or I
GND
DC V
CC
or Ground Current per Output Pin ±50mA
T
STG
Storage Temperature –65°C to +150°C
T
J
Junction Temperature 140°C
Symbol Parameter Rating
V
CC
Supply Voltage
AC 2.0V to 6.0V
ACT 4.5V to 5.5V
V
I
Input Voltage 0V to V
CC
V
O
Output Voltage 0V to V
CC
T
A
Operating Temperature –40°C to +85°C
∆
V
/
∆
t Minimum Input Edge Rate, AC Devices:
V
IN
from 30% to 70% of V
CC
,
V
CC
@ 3.3V, 4.5V, 5.5V
125mV/ns
∆
V
/
∆
t Minimum Input Edge Rate, ACT Devices:
V
IN
from 0.8V to 2.0V, V
CC
@ 4.5V, 5.5V
125mV/ns
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC08, 74ACT08 Rev. 1.5.1 3
74AC08, 74ACT08 — Quad 2-Input AND Gate
DC Electrical Characteristics for AC
Notes:
1. All outputs loaded; thresholds on input associated with output under test.
2. Maximum test duration 2.0ms, one output loaded at a time.
3. I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
Symbol Parameter
V
CC
(V) Conditions
T
A
=
+25°C T
A
=
–40°C to +85°C
UnitsTyp. Guaranteed Limits
V
IH
Minimum HIGH Level
Input Voltage
3.0 V
OUT
=
0.1V or
V
CC
– 0.1V
1.5 2.1 2.1 V
4.5 2.25 3.15 3.15
5.5 2.75 3.85 3.85
V
IL
Maximum LOW Level
Input Voltage
3.0 V
OUT
=
0.1V or
V
CC
– 0.1V
1.5 0.9 0.9 V
4.5 2.25 1.35 1.35
5.5 2.75 1.65 1.65
V
OH
Minimum HIGH Level
Output Voltage
3.0 I
OUT
=
–50µA 2.99 2.9 2.9 V
4.5 4.49 4.4 4.4
5.5 5.49 5.4 5.4
3.0 V
IN
=
V
IL
or V
IH
,
I
OH
=
–12mA
2.56 2.46
4.5 V
IN
=
V
IL
or V
IH
,
I
OH
=
–24mA
3.86 3.76
5.5 V
IN
=
V
IL
or V
IH
,
I
OH
=
–24mA
(1)
4.86 4.76
V
OL
Maximum LOW Level
Output Voltage
3.0 I
OUT
=
50µA 0.002 0.1 0.1 V
4.5 0.001 0.1 0.1
5.5 0.001 0.1 0.1
3.0 V
IN
=
V
IL
or V
IH
,
I
OL
=
12mA
0.36 0.44
4.5 V
IN
=
V
IL
or V
IH
,
I
OL
=
24mA
0.36 0.44
5.5 V
IN
=
V
IL
or V
IH
,
I
OL
=
24mA
(1)
0.36 0.44
I
IN(3)
Maximum Input
Leakage Current
5.5 V
I
=
V
CC
, GND ±0.1 ±1.0 µA
I
OLD
Minimum Dynamic
Output Current
(2)
5.5 V
OLD
=
1.65V Max. 75 mA
I
OHD 5.5 VOHD = 3.85V Min. –75 mA
ICC(3) Maximum Quiescent
Supply Current
5.5 VIN = VCC or GND 2.0 20.0 µA
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC08, 74ACT08 Rev. 1.5.1 4
74AC08, 74ACT08 — Quad 2-Input AND Gate
DC Electrical Characteristics for ACT
Notes:
4. All outputs loaded; thresholds on input associated with output under test.
5. Maximum test duration 2.0ms, one output loaded at a time.
Symbol Parameter
VCC
(V) Conditions
TA = +25°C TA = –40°C to +85°C
UnitsTyp. Guaranteed Limits
VIH Minimum HIGH Level
Input Voltage
4.5 VOUT = 0.1V or
VCC – 0.1V
1.5 2.0 2.0 V
5.5 1.5 2.0 2.0
VIL Maximum LOW Level
Input Voltage
4.5 VOUT = 0.1V or
VCC – 0.1V
1.5 0.8 0.8 V
5.5 1.5 0.8 0.8
VOH Minimum HIGH Level
Output Voltage
4.5 IOUT = –50µA 4.49 4.4 4.4 V
5.5 5.49 5.4 5.4
4.5 VIN = VIL or VIH,
IOH = –24mA
3.86 3.76
5.5 VIN = VIL or VIH,
IOH = –24mA(4)
4.86 4.76
VOL Maximum LOW Level
Output Voltage
4.5 IOUT = 50µA 0.001 0.1 0.1 V
5.5 0.001 0.1 0.1
4.5 VIN = VIL or VIH,
IOL = 24mA
0.36 0.44
5.5 VIN = VIL or VIH,
IOL= 24mA(4)
0.36 0.44
IIN Maximum Input
Leakage Current
5.5 VI = VCC, GND ±0.1 ±1.0 µA
ICCT Maximum ICC/Input 5.5 VI = VCC – 2.1V 0.6 1.5 mA
IOLD Minimum Dynamic
Output Current(5) 5.5 VOLD = 1.65V Max. 75 mA
IOHD 5.5 VOHD = 3.85V Min. –75 mA
ICC Maximum Quiescent
Supply Current
5.5 VIN = VCC or GND 4.0 40.0 µA
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC08, 74ACT08 Rev. 1.5.1 5
74AC08, 74ACT08 — Quad 2-Input AND Gate
AC Electrical Characteristics for AC
Note:
6. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V.
AC Electrical Characteristics for ACT
Note:
7. Voltage range 5.0 is 5.0V ± 0.5V.
Capacitance
Symbol Parameter VCC (V)(6)
TA = +25°C,
CL = 50pF
TA = –40°C to +85°C,
CL = 50pF
UnitsMin. Typ. Max. Min. Max.
tPLH Propagation Delay 3.3 1.5 7.5 9.5 1.0 10.0 ns
5.0 1.5 5.5 7.5 1.0 8.5
tPHL Propagation Delay 3.3 1.5 7.0 8.5 1.0 9.0 ns
5.0 1.5 5.5 7.0 1.0 7.5
Symbol Parameter VCC (V)(7)
TA = +25°C,
CL = 50pF
TA = –40°C to +85°C,
CL = 50pF
UnitsMin. Typ. Max. Min. Max.
tPLH Propagation Delay 5.0 1.0 6.5 9.0 1.0 10.0 ns
tPHL Propagation Delay 5.0 1.0 6.5 9.0 1.0 10.0 ns
Symbol Parameter Conditions Typ. Units
CIN Input Capacitance VCC = OPEN 4.5 pF
CPD Power Dissipation Capacitance VCC = 5.0V 20.0 pF
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC08, 74ACT08 Rev. 1.5.1 6
74AC08, 74ACT08 — Quad 2-Input AND Gate
Physical Dimensions
Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
LAND PATTERN RECOMMENDATION
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AB, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD:
SOIC127P600X145-14M
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
PIN ONE
INDICATOR
8°
0°
SEATING PLANE
DETAIL A
SCALE: 20:1
GAGE PLANE
0.25
X45°
1
0.10
C
C
BC A
7
M
14 B
A
8
SEE DETAIL A
5.60
0.65
1.70 1.27
8.75
8.50
7.62
6.00 4.00
3.80
(0.33)
1.27 0.51
0.35
1.75 MAX
1.50
1.25 0.25
0.10 0.25
0.19
(1.04)
0.90
0.50
0.36
R0.10
R0.10
0.50
0.25
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC08, 74ACT08 Rev. 1.5.1 7
74AC08, 74ACT08 — Quad 2-Input AND Gate
Physical Dimensions (Continued)
Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC08, 74ACT08 Rev. 1.5.1 8
74AC08, 74ACT08 — Quad 2-Input AND Gate
Physical Dimensions (Continued)
Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND TIE BAR EXTRUSIONS
F. DRAWING FILE NAME: MTC14REV6
R0.09 min
12.00°TOP & BOTTO
M
0.43 TYP
1.00
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 1982
R0.09min
E. LANDPATTERN STANDARD: SOP65P640X110-14M
0.65
6.10
1.65
0.45
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
B. DIMENSIONS ARE IN MILLIMETERS
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC08, 74ACT08 Rev. 1.5.1 9
74AC08, 74ACT08 — Quad 2-Input AND Gate
Physical Dimensions (Continued)
Figure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
14 8
7
1
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BA
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANCES PER
ASME Y14.5-1994
E) DRAWING FILE NAME: MKT-N14AREV7
6.60
6.09
8.12
7.62
0.35
0.20
19.56
18.80
3.56
3.30 5.33 MAX
0.38 MIN
1.77
1.14
0.58
0.35 2.54
3.81
3.17 8.82
(1.74)
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC08, 74ACT08 Rev. 1.5.1 10
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ative or In Design This datasheet contains the design specifications for product
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This datasheet contains preliminary data; supplementary data will be
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discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I32
74AC08, 74ACT08 — Quad 2-Input AND Gate
