MCP6071T-E/OT - Microchip Technology, Inc.

MCP6071/2/4

Features

• Low Offset Voltage: ±150 µV (maximum)

• Low Quiescent Current: 110 µA (typical)

• Rail-to-Rail Input and Output

• Wide Supply Voltage Range: 1.8V to 6.0V

• Gain Bandwidth Product: 1.2 MHz (typical)

• Unity Gain Stable

• Extended Temperature Range: -40°C to +125°C

• No Phase Reve rsal

Applications

• Automotive

• Portable Instrumentation

• Sensor Conditioning

• Battery Powered Systems

• Medical Instrumentation

• Test Equi pment

• Analog Filters

Design Aids

• SPICE Ma cr o Mo del s

•FilterLab

® Software

• MAPS (Microchip Advanced Part Selector)

• Analog Demonstration and Evaluation Boards

• Application N otes

Typical Application

Description

The Microchip Technology Inc. MCP6071/2/4 family of

operational amplifiers (op amps) has low input offset

voltage (±150 µV, maximum) and rail-to-rail input and

output operation. This family is unity gain stable and

has a gain bandwidth product of 1.2 MHz (typical).

These devices operate with a single supply voltage as

low as 1.8V, while drawing low quiescent current per

amplifier (110 µA, typical). These features make the

family of op amps well suited for single-supply, high

precision, battery-powered applications.

The MCP6071/2/4 family is offered in single

(MCP6071), dual (MCP6072), and quad (MCP6074)

configurations.

The MCP6071/2/4 is designed with Microchip’s

advanced CMOS process. All devices are available in

the extended temperature range, with a power supply

range of 1.8V to 6.0V.

Package Types

VOUT

Gyrator

ZIN

ZIN RLjωL+=

LRC=

MCP6071

* Includes Exposed Thermal Pad (EP); see Table 3-1.

9VDD

VOUT

VIN+

VIN–

VSS

NC 1

9VOUTB

VINB–

VINB+

VDD

VINA+

VINA–

VSS

VOUTA

VINA+

VINA–

VDD

VOUTA VOUTD

VIND–

VIND+

VSS

VINB+510 VINC+

VINB–69

VOUTB 7 8 VOUTC

VINC–

VINA+

VINA–

VSS

VOUTA VDD

VOUTB

VINB–

VINB+

VIN+

VIN–

VSS

NC NC

VDD

VOUT

MCP6071

SOIC

MCP6071

2x3 TDFN

MCP6072

2x3 TDFN

MCP6072

SOIC

MCP6074

SOIC, TSSOP

VIN+VIN–

VSS

VDD

VOUT

MCP6071

SOT-23-5

110 µA, High Precision Op Amps

MCP6071/2/4

NOTES:

MCP6071/2/4

1.0 ELECTRICAL CHARACTERISTICS

1.1 Absolute Maximum Ratings †

VDD – VSS ........................................................................7.0V

Current at Input Pins.....................................................±2 mA

Analog Inputs (VIN+, VIN-)†† .......... VSS – 1.0V to VDD + 1.0V

All Other Inputs and Outputs ......... VSS – 0.3V to VDD + 0.3V

Difference Input Voltage ...................................... |VDD – VSS|

Output Short-Circuit Current .................................continuous

Current at Output and Supply Pins ............................ ±30 mA

Storage Temperature ............................. .... .. .-65°C to +150°C

Maximum Junction Temperature (TJ)..........................+150°C

ESD protection on all pins (HBM; MM) ................ ≥ 4 kV; 400V

† Notice: Stresses above those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional

operatio n of the devic e at those or an y other con ditions

above those indicated in the operational listings of this

specification is not implied. Exposure to maximum

rating conditions for extended periods may affect

device reliability.

†† See 4.1.2 “Input Voltage Limits”

1.2 Specifications

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless oth erwise in dicat ed, VDD = +1.8 V to +6.0V, VSS= GND, T A= +25°C, V CM = VDD/2,

VOUT ≈VDD/2, VL = VDD/2 and RL = 10 kΩ to VL. (Refer to Figure 1-1).

Parameters Sym Min Typ Max Units Conditions

Input Offset

Input Offset Voltage VOS -150 — +150 µV VDD = 3.0V,

VCM = VDD/3

Input Offset Drift with Temperature ΔVOS/ΔTA—±1.5—µV/°CT

A= -40°C to +85°C,

VDD = 3.0V, VCM = VDD/3

ΔVOS/ΔTA—±4.0—µV/°CT

A= +85°C to +125°C,

VDD = 3.0V, VCM = VDD/3

Power Supply Rejection Ratio PSRR 70 87 — dB VCM = VSS

Input Bias Current and Impedance

Input Bias Current IB— ±1.0 100 pA

IB—60—pAT

A = +85°C

IB— 1100 5000 pA TA = +125°C

Input Offset Current IOS — ±1.0 — pA

Common Mode Input Impedance ZCM —10

13||6 — Ω||pF

Differential Input Impedance ZDIFF —10

13||6 — Ω||pF

Common Mode

Common Mode Input Voltage Range VCMR VSS−0.15 — VDD+0.15 V VDD = 1.8V (Note 1)

VCMR VSS−0.3 — VDD+0.3 V VDD = 6.0V (Note 1)

Common Mode Rejection Ratio CMRR 72 89 — dB VCM = -0.15V to 1.95V,

VDD = 1.8V

74 91 — dB VCM = -0.3V to 6.3V,

VDD = 6.0V

72 87 — dB VCM = 3.0V to 6.3V,

VDD = 6.0V

74 89 — dB VCM = -0.3V to 3.0V,

VDD = 6.0V

Note 1: Figure 2-13 shows how VCMR changed across temperature.

MCP6071/2/4

TABLE 1-2: AC ELECTRICAL SPECIFICATIONS

TABLE 1-3: TEMPERATURE SPECIFICATIONS

Open-Loop Gain

DC Open-Loop Gain

(Large Signal) AOL 95 115 — dB 0.2V < VOUT <(VDD-0.2V)

VCM = VSS

Output

Maximum Output Voltage Swing VOL, VOH VSS+15 — VDD–15 mV 0.5V input overdrive

Output Short -Circ uit Curren t ISC —±7—mAV

DD = 1.8V

—±28—mAV

DD = 6.0V

Power Supply

Supply Voltage VDD 1.8 — 6.0 V

Quiescent Current per Amplifier IQ50 110 170 µA IO = 0, VDD = 6.0V

VCM = 0.9VDD

Electrical Characteristics: Unless otherw ise i ndica ted, TA = +25°C, VDD = +1.8 to +6.0V, VSS = GND, VCM = VDD/2,

VOUT ≈VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF. (Refer to Figure 1-1).

Parameters Sym Min Typ Max Units Conditions

AC Response

Gain Bandwidth Product GBWP — 1.2 — MHz

Phase Margin PM — 57 — ° G = +1 V/V

Slew Rate SR — 0.5 — V/µs

Noise

Input Noise Voltage Eni — 4.3 — µVp-p f = 0.1 Hz to 10 Hz

Input Noise Voltage Density eni —19—nV/√Hz f = 10 kHz

Input Noise Current Density ini —0.6—fA/√Hz f = 1 kHz

Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +6.0V and VSS = GND.

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Operati ng Tempe rature Range TA-40 — +125 °C Note 1

Storage Temperature Range TA-65 — +150 °C

Thermal Package Resistances

Thermal Resistance, 5L-SOT-23 θJA — 220.7 — °C/W

Thermal Resistance, 8L-2x3 TDFN θJA —52.5—°C/W

Thermal Resistance, 8L-SOIC θJA — 149.5 — °C/W

Thermal Resistance, 14L-SOIC θJA —95.3 —°C/W

Thermal Resistance, 14L-TSSOP θJA —100 —°C/W

Note 1: The internal junction temperature (TJ) must not exceed the absolute maximum specification of +150°C.

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless oth erwis e indicat ed, VDD = +1.8 V to +6.0V, VSS= GND, T A= +2 5°C, VCM = VDD/2,

VOUT ≈VDD/2, VL = VDD/2 and RL = 10 kΩ to VL. (Refer to Figure 1-1).

Parameters Sym Min Typ Max Units Conditions

Note 1: Figure 2-13 shows how VCMR changed across temperature.

MCP6071/2/4

1.3 Test Circuits

The circuit used for most DC and AC tests is shown in

Figure 1-1. This circuit can independently set VCM and

VOUT; see Equation 1-1. Note that VCM is not the

circuit’s common mode voltage ((VP+V

M)/2) , an d t ha t

VOST includes VOS plus the effects (on the input offset

error, VOST) of temperature, CMRR, PSRR and AOL.

EQUATION 1-1:

FIGURE 1-1: AC and DC Test Circuit for

Most Spe cific ations.

GDM RFRG

⁄=

VCM VPVDD 2⁄+()2⁄=

VOUT VDD 2⁄()VPVM

–()VOST 1GDM

+()++=

Where:

GDM = Differential Mode Gain (V/V)

VCM = Op Amp’s Common Mode

Input Voltage (V)

VOST = Op Amp’s Total Input Offset

Voltage (mV)

VOST VIN–VIN+

–=

VDD

RGRF

VOUT

CB2

CB1

100 kΩ

RGRF

VDD/2

VP100 kΩ

100 kΩ

60 pF10 kΩ

1µF100 nF

VIN–

VIN+

6.8 pF

MCP607X

MCP6071/2/4

NOTES:

MCP6071/2/4

2.0 TYPICAL PERFORMANCE CURVES

Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,

VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF.

FIGURE 2-1: Input Offset Voltage with

VDD = 3.0V.

FIGURE 2-2: Input Offset Voltage Drift

with VDD = 3.0V and TA

≤

+85°C.

FIGURE 2-3: Input Offset Voltage Drift

with VDD = 3.0V and TA

≥

+85°C.

FIGURE 2-4: Input Offset Voltage vs.

Common Mode Input Voltage with VDD = 6.0V.

FIGURE 2-5: Input Offset Voltage vs.

Common Mode Input Voltage with VDD = 3.0V.

FIGURE 2-6: Input Offset Voltage vs.

Common Mode Input Voltage with VDD = 1.8V.

Note: The gra phs and tab les prov ided fo llow ing this note are a sta tistic al sum mary b ased on a limit ed numb er of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

10%

12%

14%

-150

-120

-90

-60

-30

120

150

Input Offset Voltage (µV)

Percentage of Occurences

1244 Samples

DD = 3.0V

CM = VDD /3

12%

15%

18%

21%

24%

27%

-20

-16

-12

-8

-4

Input Offset Drift with Temperature (µV/°C)

Percentage of Occurences

1244 Samples

VDD = 3.0V

VCM = VDD/3

TA = -40°C to +85°C

12%

15%

18%

21%

24%

27%

-20

-16

-12

-8

-4

Input Offset Drift with Temperature (µV/°C)

Percentage of Occurences

1244 Samples

VDD = 3.0V

VCM = VDD

TA = +85°C to +125°C

-1000

-800

-600

-400

-200

200

400

600

800

1000

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

Common Mode Input Voltage (V)

Input Offset Voltage (µV)

TA = -40°C

TA = +25°C

TA = +85°C

TA = +125°C

VDD = 6.0V Representative Part

-1000

-800

-600

-400

-200

200

400

600

800

1000

-0.5

-0.2

0.1

0.4

0.7

1.0

1.3

1.6

1.9

2.2

2.5

2.8

3.1

3.4

Common Mode Input Voltage (V)

Input Offset Voltage (µV)

TA = -40°C

TA = +25°C

TA = +85°C

TA = +125°C

VDD = 3.0V Representative Part

-1000

-800

-600

-400

-200

200

400

600

800

1000

-0.5

-0.3

-0.1

0.1

0.3

0.5

0.7

0.9

1.1

1.3

1.5

1.7

1.9

2.1

2.3

Common Mode Input Voltage (V)

Input Offset Voltage (µV)

VDD = 1.8V Representative Part

TA = -40°C

TA = +25°C

TA = +85°C

TA = +125°C

MCP6071/2/4

Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,

VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF.

FIGURE 2-7: Input Offset Voltage vs.

Output Voltage.

FIGURE 2-8: Input Offset Voltage vs.

Power Supply Voltage.

FIGURE 2-9: Input Noise Voltage Density

vs. Frequency.

FIGURE 2-10: Input Noise Voltage Density

vs. Common Mode Input Voltage.

FIGURE 2-11: CMRR, PSRR vs.

Frequency.

FIGURE 2-12: CMRR, PSRR vs. Ambient

Temperature.

-350

-250

-150

-50

150

250

350

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Output Voltage (V)

Input Offset Voltage (µV)

VDD = 6.0V

VDD = 1.8V

VDD = 3.0V

Representative Part

-1000

-800

-600

-400

-200

200

400

600

800

1000

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

Power Supply Voltage (V)

Input Offset Voltage (µV)

TA = -40°C

TA = +25°C

TA = +85°C

TA = +125°C

Representative Part

100

1,000

1.E-1 1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5

Frequency (Hz)

Input Noise Voltage Density

(nV/√Hz)

0.1 1 10 100 1k 10k 100k

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

Common Mode Input Voltage (V)

Input Noise Voltage Density

(nV/√Hz)

f = 10 kHz

VDD = 6.0V

100

110

10 100 1000 10000 100000 1000000

Frequency (Hz)

CMRR, PSRR (dB)

Representative Part

CMRR

PSRR+

PSRR-

10 100 1k 10k 100k 1M

100

105

110

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

PSRR, CMRR (dB)

PSRR (VDD = 1.8V to 6.0V, VCM = VSS)

CMRR (VDD = 6.0V, VCM = -0.3V to 6.3V)

MCP6071/2/4

Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,

VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF.

FIGURE 2-13: Common Mode Input

Voltage Range Limit vs. Ambient Temperature.

FIGURE 2-14: Input Bias, Offset Currents

vs. Ambient Temperature.

FIGURE 2-15: Input Bias Current vs.

Common Mode Input Voltage.

FIGURE 2-16: Quiescent Current vs

Ambient Temperature with VCM = 0.9VDD.

FIGURE 2-17: Quiescent Current vs.

Power Supply Voltage with VCM = 0.9VDD.

FIGURE 2-18: Open-Loop Gain, Phase vs.

Frequency.

-0.35

-0.30

-0.25

-0.20

-0.15

-0.10

-0.05

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

-50-25 0 255075100125

Ambient Temperature (°C)

Common Mode Input Voltage

Range Limit (V)

VCMR_L - VSS @ VDD = 1.8

VOL - VSS @ VDD = 3.0

VOL - VSS @ VDD = 6.0

VCMR_H - VDD @ VDD = 6.0V

@ VDD = 3.0V

@ VDD = 1.8V

100

1000

10000

25 45 65 85 105 125

Ambient Temperature (°C)

Input Bias and Offset

Currents (pA)

VDD = 6.0V

VCM = VDD

Input Bias Current

Input Offset Current

100

1000

10000

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Common Mode Input Votlage (V)

Input Bias Current (pA)

VDD = 6.0V

TA = +125°C

TA = +85°C

100

110

120

130

140

150

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

Quiescent Current

(µA/Amplifier)

VDD = 6.0V

VCM = 0.9VDD

VDD = 1.8V

VCM = 0.9VDD

100

120

140

160

180

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

7.0

Power Supply Voltage (V)

Quiescent Current

(µA/Amplifier)

VDD = 6.0V

VCM = 0.9VDD

TA = +125°C

TA = +85°C

TA = +25°C

TA = -40°C

-20

100

120

1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07

Frequency (Hz)

Open-Loop Gain (dB)

-210

-180

-150

-120

-90

-60

-30

Open-Loop Phase (°)

Open-Loop Gain

Open-Loop Phase

VDD = 6.0V

0.1 1 10 100 1k 10k 100k 1M 10M

Frequency (Hz)

MCP6071/2/4

Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,

VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF.

FIGURE 2-19: DC Open-Loop Gain vs.

Power Supply Voltage.

FIGURE 2-20: DC Open-Loop Gain vs.

Output Voltage Headroom.

FIGURE 2-21: Channel-to-Channel

Separation vs. Frequency ( MCP6072/4 only).

FIGURE 2-22: Gain Bandwidth Product,

Phase Margin vs. Common Mode Input Voltage.

FIGURE 2-23: Gain Bandwidth Product,

Phase Margin vs. Ambient Temperature.

FIGURE 2-24: Gain Bandwidth Product,

Phase Margin vs. Ambient Temperature.

100

105

110

115

120

125

130

135

140

145

150

1.52.02.53.03.54.04.55.05.56.0

Power Supply Voltage (V)

DC-Open-Loop Gain (dB)

RL = 10 kΩ

VSS + 0.2V < VOUT < VDD - 0.2V

100

105

110

115

120

125

130

135

140

145

150

0.00 0.05 0.10 0.15 0.20 0.25

Output Voltage Headroom

VDD - VOH or VOL - VSS (V)

DC-Open-Loop Gain (dB)

VDD = 6.0V

VDD = 1.8V

Large Signal AOL

100

110

120

130

140

150

1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06

Frequency (Hz)

Channel to Channel

Separation (dB)

Input Referred

100 1k 10k 100k 1M

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

Common Mode Input Voltage (V)

Gain Bandwidth Product

(MHz)

100

120

140

160

180

Phase Margin (°)

Phase Margin

Gain Bandwidth Product

VDD = 6.0V

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

Gain Bandwidth Product

(MHz)

100

120

140

160

180

Phase Margin (°)

Gain Bandwidth Product

Phase MarginVDD = 6.0V

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

-50-25 0 255075100125

Ambient Temperature (°C)

Gain Bandwidth Product

(MHz)

100

120

140

160

180

Phase Margin (°)

Gain Bandwidth Product

Phase Margin

VDD = 1.8V

MCP6071/2/4

Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,

VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF.

FIGURE 2-25: Ouput Short Circuit Current

vs. Power Supply Voltage.

FIGURE 2-26: Output Voltage Swing vs.

Frequency.

FIGURE 2-27: Ratio of Output Voltage

Headroom to Output Current vs. Output Current.

FIGURE 2-28: Output Voltage Headroom

vs. Ambient Temperature.

FIGURE 2-29: Sl ew Rate vs . Ambien t

Temperature.

FIGURE 2-30: Small Signal Non-Inverting

Pulse Response.

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Power Supply Voltage (V)

Output Short Circuit Current

(mA)

TA = -40°C

TA = +25°C

TA = +85°C

TA = +125°C

0.1

1000 10000 100000 1000000

Frequency (Hz)

Output Voltage Swing (VP-P)

VDD = 1.8V

VDD = 6.0V

1k 10k 100k 1M

0.1 1 10

Output Current (mA)

Ratio of Output Headroom to

Current (mV/mA)

(VOL - VSS)/(-IOUT)

(VDD - VOH)/IOUT VDD = 1.8V

(VDD - VOH)/IOUT

(VOL - VSS)/(-IOUT)

VDD = 6.0V

0.0

2.0

4.0

6.0

8.0

10.0

12.0

14.0

16.0

-50-25 0 255075100125

Ambient Temperature (°C)

Output Voltage Headroom

VDD - VOH or VOL - VSS (mV)

VDD - VOH

VOL - VSS

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

-50-25 0 255075100125

Ambient Temperature (°C)

Slew Rate (V/µs)

Falling Edge, VDD = 6.0V

Falling Edge, VDD = 1.8V

Rising Edge, VDD = 6.0V

Rising Edge, VDD = 1.8V

Time (2 µs/div)

Output Voltage (50 mV/div)

VDD = 6.0V

G = +1 V/V

MCP6071/2/4

Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,

VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF.

FIGURE 2-31: Small Signal Inverting Pulse

Response.

FIGURE 2-32: Large Signal Non-Inverting

Pulse Response.

FIGURE 2-33: Large Signal Inverting Pulse

Response.

FIGURE 2-34: T he MCP607 1/2/4 Shows

No Phase Re versal.

FIGURE 2-35: Closed Loop Output

Impedance vs. Frequency.

FIGURE 2-36: Measured Input Current vs.

Input Voltage (below VSS).

Time (2 µs/div)

Output Voltage (50 mV/div)

VDD = 6.0V

G = -1 V/V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Time (0.02 ms/div)

Output Voltage (V)

VDD = 6.0V

G = +1 V/V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Time (0.02 ms/div)

Output Voltage (V)

VDD = 6.0V

G = -1 V/V

-1.0

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

Time (0.1 ms/div)

Output Voltage (V)

VDD = 6.0V

G = +2 V/V

VOUT

VIN

100

1000

10 100 1000 10000 100000 1000000

Frequency (Hz)

Closed Loop Output

Impedance (Ω)

GN:

101 V/V

11 V/V

1 V/V

10 100 1k 10k 100k 1M

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0

VIN (V)

-IIN (A)

TA = -40°C

TA = +25°C

TA = +85°C

TA = +125°C

100

100n

10n

100

MCP6071/2/4

3.0 PIN DESCRIPTIONS

Descriptio ns of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

3.1 Analog Outputs

The output pins are low-impedance voltage sources.

3.2 Analog Inputs

The non-inverting and inverting inputs are high-

impedance CMOS inputs with low bias currents.

3.3 Power Supply Pins

The pos iti ve pow e r s upp ly (VDD) is 1. 8V to 6.0V high er

than the negative power supply (VSS). For normal

operation, the other pins are at voltages between VSS

and VDD.

Typically, these parts are used in a single (positive)

supply configuration. In this case, VSS is connected to

ground and VDD is connected to the supply. VDD will

need bypass capacitors.

3.4 Exposed Thermal Pad (EP)

There is an internal electrical connection between the

Exposed Thermal Pad (EP) and th e VSS pi n; they must

be connected to the same potential on the Printed

Circuit Board (PCB).

MCP6071 MCP6072 MCP6074

Symbol Description

SOIC SOT-23-5 2x3 TDFN SOIC 2x3 TDFN SOIC,

TSSOP

61 611 1V

OUT, VOUTA Analog Output (op amp A)

24 222 2V

IN–, VINA– Inverting Input (op amp A)

33 333 3V

IN+, VINA+ Non-inverting Input (op amp A)

75 788 4 V

DD Positive Power Supply

—— —5 5 5 V

INB+ Non-inverting Input (op amp B)

—— —6 6 6 VINB–Inverting Input (op amp B)

—— —7 7 7 V

OUTB Analog Output (op amp B)

—— ——— 8 V

OUTC Analog Output (op amp C)

—— ——— 9 V

INC– Inverting Input (op amp C)

—— ——— 10 V

INC+ Non-inverting Input (op amp C)

42 444 11 V

SS Negative Power Supply

—— ——— 12 V

IND+ Non-inverting Input (op amp D)

—— ——— 13 V

IND– Inverting Input (op amp D)

—— ——— 14 V

OUTD Analog Output (op amp D)

1, 5, 8 — 1, 5, 8 — — — NC No Internal Connection

— — 9 — 9 — EP Exposed Therm al Pad (EP); mus t

be connected to VSS.

MCP6071/2/4

NOTES:

MCP6071/2/4

4.0 APPLICATION INFORMATION

The MCP6071/2/4 family of op amps is manufactured

using Microchip’s state-of-the-art CMOS process and

is specifically designed for low-power, high precision

applications.

4.1 Rail-to-Rail Input

4.1.1 PHASE REVERSAL

The MCP6071/2/4 op amps are designed to prevent

phase reversal when the input pins exceed the supply

voltages. Figure 2-34 shows the input voltage

exceeding the supply voltage without any phase

reversal.

4.1.2 INPUT VOLTAGE LIMITS

In order to prevent damage and/or improper operation

of these am plifi ers, the c ircuit mus t limit th e volt ages at

the input pins (see Section 1.1, Absolute Maximum

Ratings †).

The ESD protection on the inputs can be depicted as

shown in Figure 4-1. This structure was chosen to

protect the input transistors and to minimize input bias

current (IB).

FIGURE 4-1: Simplified Analog Input ESD

Structures.

The input ESD diodes clamp the inputs when they try

to go more than one diode drop below VSS. They also

clamp any voltages that go well above VDD; their break-

down vo ltage is high enough to all ow normal opera tion,

but not lo w enough to p rotect against s low over-volt age

(beyond VDD) events. Very fast ESD events (that meet

the spec) are limited so that damage does not occur.

In some applications, it may be necessary to prevent

excessive voltages from reaching the op amp inputs.

Figure 4-2 shows one approach to protecting these

inputs.

FIGURE 4-2: Protecting the Analog

Inputs.

A significant amount of current can flow out of the

input s when t he Common M ode volt age (VCM) is below

ground (VSS). See Figure 2-36.

4.1.3 INPUT CURRENT LIMITS

In order to prevent damage and/or improper operation

of these am plifie rs, the circu it mus t limit th e volt ages at

the input pins (see Section 1.1, Absolute Maximum

Ratings †).

Figure 4-3 shows one approach to protecting these

inputs. The resistors R1 and R2 limit the possible cur-

rents in or out of the input pins (a nd the ESD diode s, D1

and D2). The diode currents will go through either VDD

or VSS.

FIGURE 4-3: Protecting the Analog

Inputs.

4.1.4 NORMAL OPERATION

The input stage of the MCP6071/2/4 op amps use two

differential input stages in parallel. One operates at a

low co mmon mode input v olt ag e (VCM), while the other

operates at a high VCM. With this topology, the device

operates with a VCM up to 300 mV above VDD and

300 mV below VSS. (See Figure 2-13). The input offset

voltage is measured at VCM = VSS –0.3V and

VDD + 0.3V to ensure proper operation.

The transition between the input stages occurs when

VCM is near VDD –1.1V (See Figures 2-4,2-5 and

Figure 2-6). For the best distortion performance and

gain li nearity, wi th non-invert ing gains, avoid this re gion

of operation.

Bond

Pad

Bond

Pad

Bond

Pad

VDD

VIN+

VSS

Input

Stage Bond

Pad VIN–

VDD

MCP607X VOUT

V1R1

VDD

min(R1,R2)>VSS –min (V

1,V2)

2mA

min(R1,R2)>max(V1,V2)–V

2mA

V2R2

MCP607X VOUT

MCP6071/2/4

4.2 Rail-to-Rail Output

The output vo ltage rang e of the MCP6071 /2/4 op amps

is VSS + 15 mV (minimum) and VDD – 15 mV

(maximum) when RL=10kΩ is connected to VDD/2

and VDD = 6.0V. Refer to Figures 2-27 and 2-28 for

more information.

4.3 Capacitive Loads

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the feedback loop’s phase

margin decreases and the closed-loop bandwidth is

reduced. This produces gain peaking in the frequency

response, with overshoot and ringing in the step

respons e. While a uni ty-gain buf fer (G = +1) is the most

sensitive to capacitive loads, all gains show the same

general behavior.

When driving large capacitive loads with these op

amps (e.g., > 100 pF when G = +1), a small series

resistor at t he output (RISO in Figure 4-4) improves the

feedback loop’s phase margin (stability) by making the

output load resistive at higher frequencies. The

bandwidth will be generally lower than the bandwidth

with no capacitance load.

FIGURE 4-4: Output Resistor, RISO

Stabilizes Large Capacitive Loads.

Figure 4-5 gives recommended RISO values for

different capacitive loads and gains. The x-axis is the

norma l iz ed lo ad ca paci tan c e (C L/GN), where GN is the

circuit 's noise gain. For non-inverti ng gains, GN a nd the

Signal Gain are equal. For inverting gains, GN is

1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).

FIGURE 4-5: Recommended RISO Values

for Capacitive Loads.

After selecting RISO for your circuit, double-check the

resulting frequency response peaking and step

response overshoot. Modify RISO’s value until the

response is reasonable. Bench evaluation and

simulations with the MCP6071/2/4 SPICE macro

model are very helpful.

4.4 Supply Bypass

With this family of operational amplifiers, the power

supply pin (VDD for single-supply) should have a local

bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm

for good hi gh freque ncy p erfor mance. It can use a bul k

capa citor (i.e., 1 µF or large r) within 100 mm to provid e

large, s low curr ents. This b ulk c ap a ci tor can be share d

with other analog parts.

4.5 Unused Op Amps

An unused op amp in a quad package (MCP6074)

should be configured as shown in Figure 4-6. These

circuits prevent the output from toggling and causing

crosstalk. Circuit A sets the op amp at its minimum

noise gain. The resistor divider produces any desired

reference volt age wit hin the outp ut volt age rang e of the

op amp; the op amp buffers that reference voltage.

Circuit B uses the minimum number of components

and operates as a comparator, but it may draw more

current.

FIGURE 4-6: Unused Op Amps.

VIN

RISO VOUT

MCP607X

–

100

1000

1.E-11 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06

Normalized Load Capacitance; CL/GN (F)

Recommended R ISO (Ω)

GN:

1 V/V

2 V/V

≥ 5 V/V

VDD = 6.0 V

RL = 10 kΩ

10p 100p 1n 10n 0.1µ 1µ

VDD

¼ MCP6074 (A) ¼ MCP6074 (B)

VDD

VREF

VREF VDD

R1R2

--------------------

MCP6071/2/4

4.6 PCB Surface Leakage

In applications where low input bias current is critical,

Printed Circuit Board (PCB) surface leakage effects

need to be considered. Surface leakage is caused by

humidity, dust or other contamination on the board.

Under low humidity conditions, a typical resistance

betwee n nearby traces is 1012Ω. A 5 V diffe rence w ould

cause 5 pA of current to flow; wh ic h is grea ter than the

MCP6071/2/4 family’s bias current at +25°C (±1.0 pA,

typical).

The easiest way to reduce surface leakage is to use a

guard ring around sensi t ive pins (or trac es). The gua rd

ring is biased at the same voltage as the sensitive pin.

An example of this type of layout is shown in

Figure 4-7.

FIGURE 4-7: Example Guard Ring Layout

for Inverting Gain.

1. Non-inverting Gain and Unity-Gain Buffer:

a.Connect the non-inverting pin (VIN+) to the

input with a wire that does not touch the

PCB surface.

b.Connect the guard ring to the inverting input

pin (VIN–). This bias es th e g uard ri ng t o th e

common mode input voltage.

2. Inverting Gain and Transimpedance Gain

Amplifiers (convert current to voltage, such as

photo detectors):

a.Connect the guard ring to the non-inverting

input pin (VIN+). This biases the guard ring

to the same reference voltage as the op

amp (e.g., VDD/2 or ground).

b.Connect the inverting pin (VIN–) to the input

with a wire that does not touch the PCB

surface.

Guard Ring VIN–V

IN+ VSS

MCP6071/2/4

4.7 Application Circuits

4.7.1 GYRATOR

The MCP6071/2/4 op amps can be used in gyrator

applic ations. The gyrat or is an electric circu it which can

make a capacitive circuit behave inductively.

Figure 4-8 shows an example of a gyrator simulating

inductance, with an approximately equivalent circuit

below. The two ZIN have similar values in typical

applications. The primary application for a gyrator is to

reduce the size and cost of a system by removing the

need for bulky, heavy and expensive inductors. For

example, RLC bandpass filter characteristics can be

realized with capacitors, resistors and operational

amplifiers without using inductors. Moreover, gyrators

will typically have higher accuracy than real inductors,

due to the lower cost of precision capacitors than

inductors.

FIGURE 4-8: Gyrator.

4.7.2 INSTRUMEN TATION AMPLIFIER

The MCP6071/2/4 op amps are well suited for

conditioning sensor signals in battery-powered

applications. Figure 4-9 shows a two op amp

instrumentation amplifier, using the MCP6072, that

works well for applications requiring rejection of

common mode noise at higher gains. The reference

voltage (VREF) is sup pli ed by a lo w imp eda nc e so urc e.

In single supply applications, VREF is typically VDD/2.

FIGURE 4-9: Two Op Amp

Instrumentation Amplifier.

To obtain the best CMRR possible, and not limit the

perfor man ce by the res ist or to lera nc es , se t a h igh gai n

with the RG resisto r.

4.7.3 PRECISION COMPARATOR

Use high gain before a comparator to improve the

latter’s input offset performance. Figure 4-10 shows a

gain of 11 V/V placed before a comparator. The

refe renc e vol tage V REF can be any value between the

supply rails.

FIGURE 4-10: Precision, Non-inverting

Comparator.

MCP6071

VOUT

Gyrator

ZIN

ZIN RLjωL+=

LRC=

ZIN

Equivalent Circuit

VOUT V1V2

–()1R1

------2R1

---------++

⎝⎠

⎛⎞

VREF

VREF R1R2R2R1VOUT

MCP6072

VIN

1MΩVOUT

MCP6071

100 kΩMCP6541

VREF

MCP6071/2/4

5.0 DESIGN AIDS

Microchip provides the basic design tools needed for

the MCP6071/2/4 family of op amps.

5.1 SPICE Macro Model

The latest SPICE macro model for the MCP6071/2/4

op amps is available on the Microchip web site at

www.microchip.com. The mo del was writte n and tested

in official Orcad (Cadence) owned PSPICE. For the

other simulators, it may require translation.

The model covers a wide aspect of the op amp's

electric al speci fication s. Not onl y does the mod el cover

voltage, current, and resistance of the op amp, but it

also covers the temperature and noise effects on the

behavior of the op amp. The model has not been

verified outside of the specification range listed in the

op amp data sheet. The model behaviors under these

conditions can not be guaranteed that it will match the

actual op amp performance.

Moreover, the model is intended to be an initial design

tool. Bench testing is a very important part of any

design and cannot be replaced with simulations. Also,

simulation results using this macro model need to be

validated by comparing them to the data sheet

specifications and characteristic curves.

5.2 FilterLab® Software

Microchip’s FilterLab® software is an innovative

software tool that simplifies analog active filter (using

op amps) design. Available at no cost from the

Micro chi p web s ite at www.microchip.com/filterlab, the

FilterLab design tool provides full schematic diagrams

of the filter circuit with component values. It also

outputs the filter circuit in SPICE format, which can be

used with the macro model to simulate actual filter

performance.

5.3 MAPS (Microchip Advanced Part

Selector)

MAPS is a software tool that helps semiconductor

professionals efficiently identify Microchip devices that

fit a particular design requirement. Available at no cost

from the Microchip website at www.microchip.com/

maps, the MAPS is an overall selection tool for

Microchip’s product portfolio that includes Analog,

Memory, MCUs and DSCs. Using this tool you can

define a filte r to sort fea tures for a p aram etric searc h of

devices and export side-by-side technical comparison

report s. Help ful links are als o provided f or Data She ets,

purchase, and sampling of Microchip parts.

5.4 Analog Demonstration and

Evaluation Boards

Microchip offers a broad spectrum of Analog

Demonstration and Evaluation Boards that are

designe d to h elp you a chieve f aster tim e to market. F or

a complete listing of these boards and their

correspo nding user’s guides and tech nical info rmatio n,

visit the Microchip web site at www.microchip.com/

analogtools.

Some boards that are especially useful are:

• MCP6XXX Amplifier Evaluation Board 1

• MCP6XXX Amplifier Evaluation Board 2

• MCP6XXX Amplifier Evaluation Board 3

• MCP6XXX Amplifier Evaluation Board 4

• Active Filter Demo Board Kit

• 5/6-Pin SOT-23 Evaluation Board, P/N VSUPEV2

• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,

P/N SOIC8EV

• 14-Pin SOIC/TSSOP/DIP Evaluation Board, P/N

SOIC14EV

5.5 Application Notes

The following Microchip Analog Design Note and

Application Notes are available on the Microchip web

site at www.microchip. com/appnotes and are

recomm end ed as suppl em ental referenc e resources.

•ADN003: “Select the Right Operational Amplifier

for your Filtering Circuits”, DS21821

•AN722: “Operational Amplifier Topologies and DC

Specifications”, DS00722

•AN723: “Operational Amplifier AC Specifications

and Applications”, DS00723

•AN884: “Drivin g Capac itive Loads With Op

Amps”, DS00884

•AN990: “Analog Sensor Conditioning Circuits –

An Overview”, DS00990

•AN1177: “Op Amp Precision Design: DC Errors”,

DS01177

•AN1228: “Op Amp Precision Design: Random

Noise”, DS01228

•AN1332: “Current Sensing Circuit Concepts and

Fundamentals”, DS01332

These application notes and others are listed in the

design guide:

•“Signal Chain Design Guide”, DS21825

MCP6071/2/4

NOTES:

MCP6071/2/4

6.0 PACKAGING INFORMATION

6.1 Package Marking Information

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanu meric traceabil ity code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free J EDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the fu ll Mic rochip part nu mber ca nnot be m arked o n one lin e, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

8-Lead SOIC (150 mil) (MCP6071, MCP6072) Example:

XXXXXXXX

XXXXYYWW

NNN

MCP6071E

SN^^ 1044

256

Example:

AHE

044

8-Lead 2x3 TDFN (MCP6071, MCP6072)

XXX

YWW

5-Lead SOT-23 (MCP6071)

XXNN

Example:

YH25

MCP6071/2/4

Package Marking Information (Continuation)

14-Lead TSSOP (MCP6074)Example:

14-Lead SOIC (150 mil) (MCP6074)Example:

XXXXXXXXXXX

YYWWNNN

XXXXXXXX

YYWW

NNN

MCP6074E

1044

256

XXXXXXXXXXX MCP6074

1044256

E/SL

MCP6071/2/4

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    

    

   

    

    

123

A2 c

   

MCP6071/2/4

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP6071/2/4

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP6071/2/4

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP6071/2/4

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP6071/2/4

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP6071/2/4

 !"#$%&''()*+, !



MCP6071/2/4

-.&/")0(+,12



 

 

 

 

 



 

   

  

  

    

    

    

  

  

  

    

    

  

   

    

    

   

   

NOTE 1

123

hα

   

MCP6071/2/4



MCP6071/2/4

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP6071/2/4

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP6071/2/4

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP6071/2/4

APPENDIX A: REVISION HISTORY

Revision B (December 2010)

The following is the list of modifications:

1. Added new SOT-23-5 package type for

MCP607 1 device.

2. Corrected Figures 2-13,2-22,2-23,2-24,2-28,

2-29 and 2-34 in Section 2.0 “Typical

Performance Curves”.

3. Modified Table 3-1 to show the pin column for

MCP60 71, SOT-23-5 pa ck ag e.

4. Updated Section 4.1.2 “Input Voltage Limits”.

5. Added Section 4.1.3 “Input Current Limits”.

6. Added new document item in Section 5.5

“Application Notes”.

7. Updated the Product Identification System

page.

Revision A (March 2009)

• Original Release of this D ocument.

MCP6071/2/4

NOTES:

MCP6071/2/4

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Device: MCP6071: Single Op Amp

MCP6071T: Single Op Amp (Tape and Reel)

(SOIC, SOT-23 and 2x3 TDFN)

MCP6072: Dual Op Amp

MCP6072T: Dual Op Amp (Tape and Reel)

(SOIC and 2x3 TDFN)

MCP6074 : Qua d Op Amp

MCP6074T: Quad Op Amp (Tape and Reel)

(SOIC and TSSOP)

Temperature Range: E = -40°C to +125°C

Package: MNY * = Plastic Dual Flat, No Lead, (2x3 TDFN ) 8-leadd

OT = Plastic Small Outline Transistor (SOT-23), 5-lead

SL = Plastic SOIC (150 mil Body), 14-lead

SN = Plastic SOIC, (150 mil Body), 8-lead

ST = Plastic TSSOP (4 .4mm Body), 14-lead

* Y = Nickel palladium gold manufacturing designator. Only

available on the TDFN package.

PART NO. -X /XX

PackageTemperature

Range

Device

Examples:

a) M CP 6071T-E/OT: Tape and Reel,

5LD SOT-23 pkg

b) MCP6071-E/SN: 8LD SOIC pkg

c) MCP 6071T-E/SN: Tape and Reel,

8LD SOIC pkg

d) M C P 6071T-E/MNY: Tape and Reel,

8LD 2x3 TDFN pkg

a) MCP6072-E/SN: 8LD SOIC pkg

b) M CP 6072T-E/SN: Tape and Reel,

8LD SOIC pkg

c) MCP 6072T-E/MNY: Tape and Reel

8LD 2x3 TDFN pkg

a) MCP6074-E/SL: 14LD SOIC pkg

b) M CP 6074T-E/SL: Tape and Reel,

14LD SOIC pkg

c) MCP6074-E/ST: 14LD TSSO P pkg

d) M CP 6074T-E/ST: Tape and Reel,

14LD TSSOP pkg

MCP6071/2/4

NOTES:

Information contained in this publication regarding device

applications and the like is p ro vid ed only for yo ur con ve nience

and may be supers eded by updat es . It is y our res po ns i bil it y to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPL AB, PIC , PIC micro, PI C START,

PIC32 logo, rfPIC and UNI/O are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SE EVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONIT OR, FanSense, HI-TIDE, In -Circuit Seria l

Programming, ICSP, Mindi, MiWi, MPASM, MPLA B Cert ified

logo, MPLIB, MPLINK, mTouch, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,

PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,

TSHARC, UniWinDriver, WiperLock and ZENA are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-60932-732-3

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in t he

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our

products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

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08/04/10