General Description
The MAX6730–MAX6735 single/dual/triple-voltage micro-
processor (μP) supervisors feature a watchdog timer and
manual reset capability. The MAX6730–MAX6735 offer
factory-set reset thresholds for monitoring voltages from
+0.9V to +5V and an adjustable reset input for monitoring
voltages down to +0.63V. The combination of these features
significantly improves system reliability and accuracy when
compared to separate ICs or discrete components.
The active-low reset output asserts and remains asserted
for the reset timeout period after all the monitored voltages
exceed their respective thresholds. Multiple factory-set reset
threshold combinations reduce the number of external
components required. The MAX6730/MAX6731 monitor a
single fixed voltage, the MAX6732/MAX6733 monitor two
fixed voltages, and the MAX6734/MAX6735 monitor two
fixed voltages and one adjustable voltage. All devices are
offered with six minimum reset timeout periods ranging from
1.1ms to 1120ms.
The MAX6730–MAX6735 feature a watchdog timer with
an independent watchdog output. The watchdog timer
prevents system lockup during code execution errors. A
watchdog startup delay of 54s after reset asserts allows
system initialization during power-up. The watchdog operates
in normal mode with a 1.68s delay after initialization. The
MAX6730/MAX6732/MAX6734 provide an active-low,
open-drain watchdog output. The MAX6731/MAX6733/
MAX6735 provide an active-low, push-pull watchdog
output.
Other features include a manual reset input (MAX6730/
MAX6731/MAX6734/MAX6735) and push-pull reset output
(MAX6731/MAX6733/MAX6735) or open-drain reset
output (MAX6730/MAX6732/MAX6734). The MAX6730–
MAX6733 are offered in a tiny SOT23-6 package. The
MAX6734/MAX6735 are offered in a space-saving
SOT23-8 package. All devices are fully specified over the
extended -40°C to +85°C temperature range.
Applications
● Multivoltage Systems
● Telecom/Networking Equipment
● Computers/Servers
● Portable/Battery-Operated Equipment
● Industrial Equipment
● Printer/Fax
● Set-Top Boxes
Benets and Features
●VCC1 (Primary Supply) Reset Threshold Voltages
from +1.575V to +4.63V
●VCC2 (Secondary Supply) Reset Threshold Voltages
from +0.79V to +3.08V
● Adjustable RSTIN Threshold for Monitoring Voltages
Down to +0.63V (MAX6734/MAX6735 Only)
● Six Reset Timeout Options
● Watchdog Timer with Independent Watchdog Output
• 35s (min) Initial Watchdog Startup Period
• 1.12s (min) Normal Watchdog Timeout Period
● Manual Reset Input
(MAX6730/MAX6731/MAX6734/MAX6735)
● Guaranteed Reset Valid down to
VCC1 or VCC2 = +0.8V
● Push-Pull RESET or Open-Drain RESET Output
● Immune to Short VCC Transients
● Low Supply Current: 14μA (typ) at +3.6V
● Small 6-Pin and 8-Pin SOT23 Packages
● AEC-Q100 Qualified: MAX6734KATGD3/V+T,
MAX6734KALTD3/V+T
Pin Configurations appear at end of data sheet.
19-2629; Rev 9; 10/17
MAX6734
MAX6735
+0.9V
VCORE +3.3V
+1.8V
MR
GND
RSTIN RST
WDI
WDO
PUSHBUTTON
SWITCH
RESET
µ
P
NMI
I/O
VCC
(I/O)
VDD
(MEMORY)
VCC1VCC2
GND
Typical Operating Circuit
MAX6730–MAX6735 Single/Dual/Triple-Voltage μP Supervisory
Circuits with Independent Watchdog Output
VCC1, VCC2, RSTIN, MR, WDI to GND ..................-0.3V to +6V
RST, WDO to GND (open drain) ............................. -0.3V to +6V
RST, WDO to GND (push-pull) .............. -0.3V to (VCC1 + 0.3V)
Input Current/Output Current (all pins) ...............................20mA
Continuous Power Dissipation (TA = +70°C)
6-Pin SOT23-6 (derate 4.3mW/°C above +70°C) ....347.8mW
8-Pin SOT23-8 (derate 5.6mW/°C above +70°C) ....444.4mW
Operating Temperature Range ........................... -40°C to +85°C
Storage Temperature Range ............................ -65°C to +150°C
Junction Temperature ...................................................... +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow)
Lead (Pb)-free packages.............................................+260°C
Package containing lead (Pb) .....................................+240°C
6 SOT23
Junction-to-Ambient Thermal Resistance (θJA) ........230°C/W
Junction-to-Case Thermal Resistance (θJC) ...............76°C/W
8 SOT23
Junction-to-Ambient Thermal Resistance (θJA) ........180°C/W
Junction-to-Case Thermal Resistance (θJC) ...............60°C/W
(Note 1)
(VCC1 = VCC2 = +0.8V to +5.5V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics
Electrical Characteristics
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage VCC1,
VCC20.8 5.5 V
Supply Current
ICC1
VCC1 < +5.5V, all I/O connections
open, outputs not asserted 15 39
µA
VCC1 < +3.6V, all I/O connections
open, outputs not asserted 10 28
ICC2
VCC2 < +3.6V, all I/O connections
open, outputs not asserted 411
VCC2 < +2.75V, all I/O connections
open, outputs not asserted 3 9
VCC1 Reset Threshold VTH1
L (falling) 4.500 4.625 4.750
V
M (falling) 4.250 4.375 4.500
T (falling) 3.000 3.075 3.150
S (falling) 2.850 2.925 3.000
R (falling) 2.550 2.625 2.700
Z (falling) 2.250 2.313 2.375
Y (falling) 2.125 2.188 2.250
W (falling) 1.620 1.665 1.710
V (falling) 1.530 1.575 1.620
MAX6730–MAX6735 Single/Dual/Triple-Voltage μP Supervisory
Circuits with Independent Watchdog Output
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(VCC1 = VCC2 = +0.8V to +5.5V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
Electrical Characteristics (continued)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VCC2 Reset Threshold VTH2
T (falling) 3.000 3.075 3.150
V
S (falling) 2.850 2.925 3.000
R (falling) 2.550 2.625 2.700
Z (falling) 2.250 2.313 2.375
Y (falling) 2.125 2.188 2.250
W (falling) 1.620 1.665 1.710
V (falling) 1.530 1.575 1.620
I (falling) 1.350 1.388 1.425
H (falling) 1.275 1.313 1.350
G (falling) 1.080 1.110 1.140
F (falling) 1.020 1.050 1.080
E (falling) 0.810 0.833 0.855
D (falling) 0.765 0.788 0.810
Reset Threshold Tempco 20 ppm/°C
Reset Threshold Hysteresis VHYST Referenced to VTH typical 0.5 %
VCC_ to RST Output Delay tRD
VCC1 = (VTH1 + 100mV) to
(VTH1 - 100mV) or
VCC2 = (VTH2 + 75mV) to
(VTH2 - 75mV)
45 µs
Reset Timeout Period tRP
D1 1.1 1.65 2.2
ms
D2 8.8 13.2 17.6
D3 140 210 280
D5 280 420 560
D6 560 840 1120
D4 1120 1680 2240
ADJUSTABLE RESET COMPARATOR INPUT (MAX6734/MAX6735)
RSTIN Input Threshold VRSTIN 611 626.5 642 mV
RSTIN Input Current IRSTIN -25 +25 nA
RSTIN Hysteresis 3 mV
RSTIN to Reset Output Delay tRSTIND VRSTIN to (VRSTIN - 30mV) 22 µs
MANUAL RESET INPUT (MAX6730/MAX6731/MAX6734/MAX6735)
MR Input Threshold VIL 0.3 x VCC1V
VIH 0.7 x VCC1
MR Minimum Pulse Width 1 µs
MR Glitch Rejection 100 ns
MR to Reset Output Delay tMR 200 ns
MR Pullup Resistance 25 50 80 kΩ
MAX6730–MAX6735 Single/Dual/Triple-Voltage μP Supervisory
Circuits with Independent Watchdog Output
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(VCC1 = VCC2 = +0.8V to +5.5V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
Note 2: Devices tested at TA = +25°C. Overtemperature limits are guaranteed by design and not production tested.
Note 3: Parameter guaranteed by design.
Electrical Characteristics (continued)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
WATCHDOG INPUT
Watchdog Timeout Period tWD-L First watchdog period after reset
timeout period 35 54 72 s
tWD-S Normal mode 1.12 1.68 2.24
WDI Pulse Width tWDI (Note 3) 50 ns
WDI Input Voltage VIL 0.3 x VCC1V
VIH 0.7 x VCC1
WDI Input Current IWDI WDI = 0 or VCC1 -1 +1 µA
RESET/WATCHDOG OUTPUT
RST/WDO Output Low Voltage
(Push-Pull or Open Drain) VOL
VCC1 or VCC2 ≥ +0.8V,
ISINK = 1µA, output asserted 0.3
V
VCC1 or VCC2 ≥ +1.0V,
ISINK = 50µA, output asserted 0.3
VCC1 or VCC2 ≥ +1.2V,
ISINK = 100µA, output asserted 0.3
VCC1 or VCC2 ≥ +2.7V,
ISINK = 1.2mA, output asserted 0.3
VCC1 or VCC2 ≥ +4.5V,
ISINK = 3.2mA, output asserted 0.4
RST/WDO Output High Voltage
(Push-Pull Only) VOH
VCC1 ≥ +1.8V, ISOURCE = 200µA,
output not asserted 0.8 x VCC1
V
VCC1 ≥ +2.7V, ISOURCE = 500µA,
output not asserted 0.8 x VCC1
VCC1 ≥ +4.5V, ISOURCE = 800µA,
output not asserted 0.8 x VCC1
RST/WDO Output Open-Drain
Leakage Current Output not asserted 0.5 µA
MAX6730–MAX6735 Single/Dual/Triple-Voltage μP Supervisory
Circuits with Independent Watchdog Output
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(VCC1 = +5V, VCC2 = +3.3V, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics
0
4
2
10
8
6
16
14
12
18
-40 10-15 35 60 85
SUPPLY CURRENT vs. TEMPERATURE
(VCC1 = +3.3V, VCC2 = +2.5V)
MAX6730-35 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
TOTAL
ICC1
ICC2
0
4
2
10
8
6
16
14
12
18
-40 10-15 35 60 85
SUPPLY CURRENT vs. TEMPERATURE
(VCC1 = +2.5V, VCC2 = +1.8V)
MAX6730-35 toc03
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
TOTAL
ICC1
ICC2
0
4
2
10
8
6
16
14
12
18
-40 10-15 35 60 85
SUPPLY CURRENT vs. TEMPERATURE
(VCC1 = +1.8V, VCC2 = +1.2V)
MAX6730-35 toc04
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
TOTAL
ICC1
ICC2
NORMALIZED THRESHOLD VOLTAGE
vs. TEMPERATURE
MAX6730-35 toc05
TEMPERATURE (°C)
NORMALIZED THRESHOLD VOLTAGE
603510-15
0.992
0.994
0.996
0.998
1.000
1.002
1.004
1.006
1.008
1.010
0.990
-40 85
0
4
2
10
8
6
16
14
12
18
-40 10-15 35 60 85
SUPPLY CURRENT vs. TEMPERATURE
(VCC1 = +5V, VCC2 = +3.3V)
MAX6730-35 toc01
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
TOTAL
ICC1
ICC2
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MAX6730–MAX6735 Single/Dual/Triple-Voltage μP Supervisory
Circuits with Independent Watchdog Output
(VCC1 = +5V, VCC2 = +3.3V, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
NORMALIZED TIMEOUT PERIOD
vs. TEMPERATURE
MAX6730-35 toc06
TEMPERATURE (°C)
NORMALIZED TIMEOUT PERIOD
603510-15
0.9995
1.0000
1.0005
1.0010
1.0015
1.0020
1.0025
1.0030
1.0035
1.0040
0.9990
-40 85
MAXIMUM VCC_ TRANSIENT DURATION
vs. RESET THRESHOLD OVERDRIVE
MAX6730-35 toc07
RESET THRESHOLD OVERDRIVE (mV)
MAXIMUM VCC_
TRANSIENT DURATION (ms)
10 100
100
1000
10,000
10
1 1000
RST ASSERTS
ABOVE THIS LINE
MR TO RESET OUTPUT DELAY
MAX6730-35 toc08
40ns/div
MR
2V/div
RST
2V/div
VCC_ TO RESET OUTPUT DELAY
vs. TEMPERATURE (100mV OVERDRIVE)
MAX6730-35 toc09
TEMPERATURE (°C)
VCC_
TO RESET OUTPUT DELAY (µs)
6035-15 10
45
50
55
60
65
70
75
80
40
-45 85
12
14
16
18
20
22
24
26
28
30
10
RSTIN TO RESET OUTPUT DELAY
vs. TEMPERATURE
MAX6730-35 toc10
TEMPERATURE (°C)
RSTIN TO RESET OUTPUT DELAY (µs)
6035-15 10-45 85
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MAX6730–MAX6735 Single/Dual/Triple-Voltage μP Supervisory
Circuits with Independent Watchdog Output
Pin Description
GND
MRWDO
1
+
6 VCC1
5 WDI
RST
MAX6730
MAX6731
SOT23-6
TOP VIEW
2
3 4
GND
VCC2WDO
1 6 VCC1
5 WDI
RST
MAX6732
MAX6733
SOT23-6 SOT23-8
2
3 4
VCC2
MRWDO
1
2
8
7
VCC1
RSTINGND
WDI
RST
3
4
6
5
MAX6734
MAX6735
++
PIN
NAME FUNCTION
MAX6730
MAX6731
MAX6732
MAX6733
MAX6734
MAX6735
111RST
Active-Low Reset Output. The MAX6730/MAX6732/MAX6734 provide an open-drain
output. The MAX6731/MAX6733/MAX6735 provide a push-pull output. RST asserts
low when any of the following conditions occur: VCC1 or VCC2 drops below its
preset threshold, RSTIN drops below its reset threshold, or MR is driven low. Open-
drain versions require an external pullup resistor.
222GND Ground
334WDO
Active-Low Watchdog Output. The MAX6730/MAX6732/MAX6734 provide an
open-drain WDO output. The MAX6731/MAX6733/MAX6735 provide a push-pull
WDO output. WDO asserts low when no low-to-high or high-to-low transition occurs
on WDI within the watchdog timeout period (tWD) or if an undervoltage lockout
condition exists for VCC1, VCC2, or RSTIN. WDO deasserts without a timeout period
when VCC1, VCC2, and RSTIN exceed their reset thresholds, or when the manual
reset input is asserted. Open-drain versions require an external pullup resistor.
4— 5 MR
Active-Low Manual Reset Input. Drive MR low to force a reset. RST remains
asserted as long as MR is low and for the reset timeout period after MR releases
high. MR has a 50kΩ pullup resistor to VCC1; leave MR open or connect to VCC1 if
unused.
5 5 3 WDI
Watchdog Input. If WDI remains high or low for longer than the watchdog timeout
period, the internal watchdog timer expires and the watchdog output asserts low.
The internal watchdog timer clears whenever RST asserts or a rising or falling edge
on WDI is detected. The watchdog has an initial watchdog timeout period (35s min)
after each reset event and a short timeout period (1.12s min) after the rst valid WDI
transition. Leaving WDI unconnected does not disable the watchdog timer function.
668VCC1Primary Supply-Voltage Input. VCC1 provides power to the device when it is greater
than VCC2. VCC1 is the input to the primary reset threshold monitor.
—46 VCC2Secondary Supply-Voltage Input. VCC2 provides power to the device when it is
greater than VCC1. VCC2 is the input to the secondary reset threshold monitor.
— — 7 RSTIN
Undervoltage Reset Comparator Input. RSTIN provides a high-impedance
comparator input for the adjustable reset monitor. RST asserts low if the voltage
at RSTIN drops below the 626mV internal reference voltage. Connect a resistive
voltage-divider to RSTIN to monitor voltages higher than 626mV. Connect RSTIN to
VCC1 or VCC2 if unused.
Pin Congurations
MAX6730–MAX6735 Single/Dual/Triple-Voltage μP Supervisory
Circuits with Independent Watchdog Output
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Detailed Description
Supply Voltages
The MAX6730–MAX6735 microprocessor (μP) supervisors
maintain system integrity by alerting the μP to fault conditions.
The MAX6730–MAX6735 monitor one to three supply
voltages in μP-based systems and assert an active-low
reset output when any monitored supply voltage drops
below its preset threshold. The output state remains valid
for VCC1 or VCC2 greater than +0.8V.
Threshold Levels
The two-letter code in the Reset Voltage Threshold Suffix
Guide (Table 1) indicates the threshold level combinations
for VCC1 and VCC2.
Reset Output
The MAX6730–MAX6735 feature an active-low reset out-
put (RST). RST asserts when the voltage at either VCC1
or VCC2 falls below the voltage threshold level, VRSTIN
drops below its threshold, or MR is driven low (Figure 1).
RST remains low for the reset timeout period (Table 2) after
VCC1, VCC2, and RSTIN increase above their respective
thresholds and after MR releases high. Whenever VCC1,
VCC2, or RSTIN go below the reset threshold before the
end of the reset timeout period, the internal timer restarts.
The MAX6730/MAX6732/ MAX6734 provide an open-
drain RST output, and the MAX6731/MAX6733/MAX6735
provide a push-pull RST output.
Table 1. Reset Voltage Threshold Suffix
Guide**
Table 2. Reset Timeout Period Suffix
Guide
**Standard versions are shown in bold and are available in a D3
timeout option only. Standard versions require 2500-piece order
increments and are typically held in sample stock. There is a
10,000-piece order increment on nonstandard versions.
Other threshold voltages may be available; contact factory
for availability.
PART NO. SUFFIX
VCC1 NOMINAL
VOLTAGE
THRESHOLD(V)
VCC2 NOMINAL
VOLTAGE
THRESHOLD (V)
LT 4.625 3.075
MS 4.375 2.925
MR 4.375 2.625
TZ 3.075 2.313
SY 2.925 2.188
RY 2.625 2.188
TW 3.075 1.665
SV 2.925 1.575
RV 2.625 1.575
TI 3.075 1.388
SH 2.925 1.313
RH 2.625 1.313
TG 3.075 1.110
SF 2.925 1.050
RF 2.625 1.050
TE 3.075 0.833
SD 2.925 0.788
RD 2.625 0.788
ZW 2.313 1.665
YV 2.188 1.575
ZI 2.313 1.388
YH 2.188 1.313
ZG 2.313 1.110
YF 2.188 1.050
ZE 2.313 0.833
YD 2.188 0.788
WI 1.665 1.388
VH 1.575 1.313
WG 1.665 1.110
VF 1.575 1.050
WE 1.665 0.833
VD 1.575 0.788
TIMEOUT PERIOD
SUFFIX
ACTIVE TIMEOUT PERIOD
MIN (ms) MAX (ms)
D1 1.1 2.2
D2 8.8 17.6
D3 140 280
D5 280 560
D6 560 1120
D4 1120 2240
MAX6730–MAX6735 Single/Dual/Triple-Voltage μP Supervisory
Circuits with Independent Watchdog Output
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Manual Reset Input
Many μP-based products require manual reset capability,
allowing the operator, a test technician, or external logic
circuitry to initiate a reset. A logic low on MR asserts the
reset output, clears the watchdog timer, and deasserts
the watchdog output. Reset remains asserted while MR is
low and for the reset timeout period (tRP) after MR returns
high. An internal 50kΩ pullup resistor allows MR to be left
open if unused. Drive MR with TTL or CMOS-logic levels
or with open-drain/collector outputs. Connect a normally
open momentary switch from MR to GND to create a
manual reset function; external debounce circuitry is not
required. Connect a 0.1μF capacitor from MR to GND to
provide additional noise immunity when driving MR over
long cables or if the device is used in a noisy environment.
Adjustable Input Voltage (RSTIN)
The MAX6734/MAX6735 provide an additional high-
impedance comparator input with a 626mV threshold to
monitor a third supply voltage. To monitor a voltage higher
than 626mV, connect a resistive-divider to the circuit as
shown in Figure 2 to establish an externally controlled
threshold voltage, VEXT_TH.
EXT_TH
(R1 R2)
V = 626mV
R2
+
×
Figure 1. RST, WDO, and MR Timing Diagram
Figure 2. Monitoring a Third Voltage
tRP
tRP
VTH
VCC
(MIN)
VCC1,
VCC2
RSTIN
RST
WDO
MR
MAX6734
MAX6735
VEXT_TH
GND
RSTIN
R1
R2
MAX6730–MAX6735 Single/Dual/Triple-Voltage μP Supervisory
Circuits with Independent Watchdog Output
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The RSTIN comparator derives power from VCC1, and
the input voltage must remain less than or equal to VCC1.
Low leakage current at RSTIN allows the use of large-
valued resistors, resulting in reduced power consumption
of the system.
Watchdog
The watchdog feature monitors μP activity through the
watchdog input (WDI). A rising or falling edge on WDI
within the watchdog timeout period (tWD) indicates normal
μP operation. WDO asserts low if WDI remains high or
low for longer than the watchdog timeout period. Leaving
WDI unconnected does not disable the watchdog timer.
The devices include a dual-mode watchdog timer to monitor
μP activity. The flexible timeout architecture provides a
long-period initial watchdog mode, allowing complicated
systems to complete lengthy boots, and a short-period
normal watchdog mode, allowing the supervisor to provide
quick alerts when processor activity fails. After each reset
event (VCC power-up, brownout, or manual reset), there
is a long initial watchdog period of 35s (min). The long
watchdog period mode provides an extended time for the
system to power up and fully initialize all μP and system
components before assuming responsibility for routine
watchdog updates.
The usual watchdog timeout period (1.12s min) begins
after the initial watchdog timeout period (tWD-L) expires or
after the first transition on WDI (Figure 3). During normal
operating mode, the supervisor asserts the WDO output
if the μP does not update the WDI with a valid transition
(high to low or low to high) within the standard timeout
period (tWD-S) (1.12s min).
Connect MR to WDO to force a system reset in the event
that no rising or falling edge is detected at WDI within
the watchdog timeout period. WDO asserts low when no
edge is detected by WDI, the RST output asserts low, the
watchdog counter immediately clears, and WDO returns
high. The watchdog counter restarts, using the long
watchdog period, when the reset timeout period ends
(Figure 4).
Ensuring a Valid RESET
Output Down to VCC = 0V
The MAX6730–MAX6735 guarantee proper operation
down to VCC = +0.8V. In applications that require valid
reset levels down to VCC = 0V, use a 100kΩ pulldown
resistor from RST to GND. The resistor value used is
not critical, but it must be large enough not to load the
reset output when VCC is above the reset threshold.
For most applications, 100kΩ is adequate. Note that this
configuration does not work for the open-drain outputs of
MAX6730/MAX6732/MAX6734.
Figure 3. Watchdog Input/Output Timing Diagram (MR and WDO Not Connected)
tRP
VTH
VCC
(MIN)
VCC1,
VCC2
RSTIN
RST
WDO
WDI < tWD-S
< tWD-S
> tWD-S
tWD-S
< tWD-S
< tWD-S
< tWD-L
MAX6730–MAX6735 Single/Dual/Triple-Voltage μP Supervisory
Circuits with Independent Watchdog Output
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Applications Information
Interfacing to μPs with Bidirectional
Reset Pins
Microprocessors with bidirectional reset pins can interface
directly with the open-drain RST output options. However,
conditions might occur in which the push-pull output ver-
sions experience logic contention with the bidirectional
reset pin of the μP. Connect a 10kΩ resistor between
RST and the μP’s reset I/O port to prevent logic conten-
tion (Figure 5).
Falling VCC Transients
The devices μP supervisors are relatively immune to
short-duration falling VCC_ transients (glitches). Small
glitches on VCC_ are ignored by the MAX6730–MAX6735,
preventing undesirable reset pulses to the μP. The Typical
Operating Characteristics show Maximum Transient
Duration vs. Reset Threshold Overdrive, for which reset
Figure 4. Watchdog Input/Output Timing Diagram (MR and WDO Connected)
Figure 5. Interfacing to μPs with Bidirectional Reset I/O
tRP
> tWD-S
tMR
< tWD-S < tWD-L
< tWD-L
tRP
VTH
VCC
(MIN)
VCC1,
VCC2
RSTIN
RST
WDO
WDI
MR
MAX6731
MAX6733
MAX6735
VCC1
VCC1
VCC2
VCC2
RESET TO
OTHER
SYSTEM
COMPONENTS
GND
µ
P
RST
GND
10kΩ
RESET
MAX6730–MAX6735 Single/Dual/Triple-Voltage μP Supervisory
Circuits with Independent Watchdog Output
www.maximintegrated.com Maxim Integrated
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11
pulses are not generated. The graph was produced using
falling VCC_ pulses, starting above VTH and ending below
the reset threshold by the magnitude indicated (reset
threshold overdrive). The graph shows the maximum
pulse width that a falling VCC transient typically might
have without causing a reset pulse to be issued. As the
amplitude of the transient increases (i.e., goes further
below the reset threshold), the maximum allowable pulse
width decreases. A 0.1μF bypass capacitor mounted
close to VCC_ provides additional transient immunity.
Watchdog Software Considerations
Setting and resetting the watchdog input at different
points in the program rather than “pulsing” the watchdog
input high-low-high or low-high-low helps the watchdog
timer closely monitor software execution. This technique
avoids a “stuck” loop, in which the watchdog timer continues
to be reset within the loop, preventing the watchdog from
timing out. Figure 6 shows an example flow diagram in
which the I/O driving the watchdog input is set high at
the beginning of the program, set low at the beginning of
every subroutine or loop, and then set high again when
the program returns to the beginning. If the program
“hangs” in any subroutine, the I/O continually asserts low
(or high), and the watchdog timer expires, issuing a reset
or interrupt.
Figure 6. Watchdog Flow Diagram
Functional Diagram
START
SET WDI
HIGH
PROGRAM
CODE
RETURN
SUBROUTINE
COMPLETED
HANG IN
SUBROUTINE
SUBROUTINE OR
PROGRAM LOOP
SET WDI LOW
MAX6730–
MAX6735
VREF
RESET
TIMEOUT
PERIOD
RESET
OUTPUT
DRIVER
WATCHDOG
TIMER
REF
VCC1
VREF / 2
GND
VCC1MR
VCC1VCC1
VCC1
VCC2
MR
PULLUP
VCC1
VCC2
RSTIN
RST
WDO
WDI
MAX6730–MAX6735 Single/Dual/Triple-Voltage μP Supervisory
Circuits with Independent Watchdog Output
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*Insert the threshold level suffixes for VCC1 and VCC2 (Table 1)
after “UT” or “KA.” For the MAX6730/MAX6731, insert only the
VCC1 threshold suffix after the “UT.” Insert the reset timeout delay
(Table 2) after “D” to complete the part number. For example, the
MAX6732UTLTD3+T provides a VCC1 threshold of +4.625V, a
VCC2 threshold of +3.075V, and a 210ms reset timeout period.
Sample stock is generally held on standard versions only.
Standard versions have an order increment requirement of 2500
pieces. Nonstandard versions have an order increment requirement
of 10,000 pieces. Contact factory for availability.
+Denotes Lead(Pb)-free packages and - denotes leaded packages.
Not all MAX6734KA_ _D_ options are available with leaded (-T)
packages. See
https://www.maximintegrated.com
for available
leaded options.
Some devices are available in both leaded and lead(Pb)-free/
RoHS compliant packaging.
For top mark information, please go to
https://www.maximinte-
grated.com/en/design/packaging/topmark/
/V denotes an automotive qualified part.
PART NUMBER VOLTAGE
MONITORS RST OUTPUT MANUAL RESET WATCHDOG
INPUT
WATCHDOG
OUTPUT
MAX6730 1 Open Drain √ √ Open Drain
MAX6731 1 Push-Pull √ √ Push-Pull
MAX6732 2 Open Drain — √Open Drain
MAX6733 2 Push-Pull —√ Push-Pull
MAX6734 3 Open Drain √ √ Open Drain
MAX6735 3 Push-Pull √ √ Push-Pull
Selector Guide
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PART* TEMP RANGE PIN-PACKAGE
MAX6730UT_D_ +T -40°C to +85°C 6 SOT23
MAX6731UT_D_ +T -40°C to +85°C 6 SOT23
MAX6732UT_ _D_ +T -40°C to +85°C 6 SOT23
MAX6733UT_ _D_ -T -40°C to +85°C 6 SOT23
MAX6734KA_ _D_ -T -40°C to +85°C 8 SOT23
MAX6734KA_ _ D_+T -40°C to +85°C 8 SOT23
MAX6734KA_ _D_ /V+T -40°C to +85°C 8 SOT23
MAX6734KATGD3/V+T -40°C to +85°C 8 SOT23
MAX6734KALTD3/V+T -40°C to +85°C 8 SOT23
MAX6735KA_ _D_ +T -40°C to +85°C 8 SOT23
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
6 SOT23 U6+1, U6-1
(MAX6733 only) 21-0058 90-0175
8 SOT23 K8SN-1 (MAX6734
only), K8SN+1 21-0078 90-0176
Ordering Information
MAX6730–MAX6735 Single/Dual/Triple-Voltage μP Supervisory
Circuits with Independent Watchdog Output
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Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
010/02 Initial release. —
112/02 Released MAX6730/MAX6731. 1
21/03 Released MAX6733. 1
33/04 Updated Typical Operating Circuit.14
4 12/05 Added lead-free notation to Ordering Information. 1
5 3/09 Updated Pin Description and added Package Table.7, 14
611/11 Added automotive-qualied part information 1
74/13 Added Package Thermal Characteristics and corrected power dissipation errors
and package code for 8 SOT23 2–4, 14
8 12/15 Added lead-free part numbers to Ordering Information table, updated Package
Information table, and removed Standard Versions table. 1, 13, 14
9 10/17 Added AEC qualcation statement to Benets and Features section and updated
Ordering Information table 1, 13
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2017 Maxim Integrated Products, Inc.
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MAX6730–MAX6735 Single/Dual/Triple-Voltage μP Supervisory
Circuits with Independent Watchdog Output
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
