AT91R40807 Electrical Characteristics - Atmel Corporation

Features

•Incorporates the ARM7TDMI™ ARM® Thumb® Processor Core

– High-performance 32-bit RISC Architecture

– High-density 16-bit Instruction Set

– Leader in MIPS/Watt

– Embedded ICE (In-Circuit Emulation)

•136K Bytes of On-chip SRAM

– 32-bit Data Bus

– Single-clock Cycle Access

•Fully-programmable External Bus Interface (EBI)

– Maximum External Address Space of 64M Bytes

– Up to Eight Chip Selects

– Software Programmable 8-/16-bit External Data Bus

•8-level Priority, Individually Maskable, Vectored Interrupt Controller

– Four External Interrupts, Including a High-priority Low-latency Interrupt Request

•32 Programmable I/O Lines

•Three-channel 16-bit Timer/Counter

– Three External Clock Inputs

– Two Multi-purpose I/O Pins per Channel

•Two USARTs

– Two Dedicated Peripheral Data Controller (PDC) Channels per USART

•Programmable Watchdog Timer

•Advanced Power-saving Features

– CPU and Peripherals Can be Deactivated Individually

•Fully Static Operation: 0 Hz to 33 MHz Internal Frequency Range at 3.0 V, 85°C

•1.8V to 3.6V Operating Range

•Available in a 100-lead TQFP Package

Description

The AT91R40807 microcontroller is a member of the Atmel AT91 16-/32-bit microcon-

troller family, which is based on the ARM7TDMI processor core. This processor has a

high-performance 32-bit RISC architecture with a high-density 16-bit instruction set

and very low power consumption. In addition, a large number of internally banked reg-

isters result in very fast exception handling, making the device ideal for real-time

control applications.

The AT91R40807 microcontroller features a direct connection to off-chip memory,

including Flash, through the fully-programmable External Bus Interface (EBI). An

eight-level priority vectored interrupt controller, in conjunction with the Peripheral Data

Controller, significantly improves the real-time performance of the device.

The device is manufactured using Atmel’s high-density CMOS technology. By combin-

ing the ARM7TDMI processor core with a large on-chip high-speed SRAM and a wide

range of peripheral functions on a monolithic chip, the AT91R40807 is a powerful

microcontroller that offers a flexible and high-performance solution to many compute-

intensive embedded control applications.

AT91

ARM® Thumb®

Microcontroller

AT91R40807

Electrical

Characteristics

Rev. 1367C–01/02

2AT91R40807

1367C–01/02

Absolute Maximum Ratings*

DC Characteristics

The following characteristics are applicable to the Operating Temperature range: TA = -40°C to +85°C, unless otherwise

specified and are certified for a Junction Temperature up to TJ = 100°C.

Operating Temperature (Industrial) ....-40°C to + 85°C*NOTICE: Stresses beyond those listed under “Absolute Maxi-

mum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional

operation of the device at these or other conditions

beyond those indicated in the operational sections of

this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may

affect device reliability.

Storage Temperature........................-60°C to + 150°C

Voltage on Any Input Pin

with Respect to Ground......................-0.5V to + 3.9V

Maximum Operating Voltage ................................4.6V

DC Output Current ..............................................6 mA

Table 1. DC Characteristics

Symbol Parameter Conditions Min Typ Max Units

VDD DC Supply 1.8 3.6 V

VIL Input Low Voltage VDD = 3.0V to 3.6V -0.3 0.3 x VDD V

VIH Input High Voltage VDD= 3.0V to 3.6V 0.7 x VDD VDD + 0.3 V

VOL Output Low Voltage IOL = 0.3 mA, VDD = 3.0V 0.1 V

VOH Output High Voltage IOH = 0.3 mA, VDD = 3.0V VDD - 0.1 V

ILEAK Input Leakage Current 390 nA

IPULL Input Pull-up Current VDD = 3.6V, VIN = 0V 350 µA

CIN Input Capacitance 6.8 pF

ISC Static Current

VDD = 3.6V;

MCKI = 0 Hz TA = 25°C 45

µA

All inputs driven TMS, TDI,

TCK, NRST = 1 TA = 85°C 900

AT91R40807

1367C–01/02

Power

Consumption

The values in the following tables are measured values in the operating conditions indicated

(i.e., VDD = 3.3V or 2.0V, TA = 25°C) on the AT91EB40 Evaluation Board.

Table 2. Power Consumption

Mode Conditions

VDD

Units2.0V 3.3V

Reset 0.08 0.20

mW/MHz

Normal

Fetch in ARM mode out of internal SRAM

All peripheral clocks activated

1.56 5.34

Fetch in ARM mode out of internal SRAM

All peripheral clocks deactivated

1.39 4.64

Idle All peripheral clocks activated 0.41 1.34

All peripheral clocks deactivated 0.14 1.00

Table 3. Power Consumption per Peripheral

Peripheral

VDD

Units2.0V 3.3V

PIO Controller 0.03 0.12

mW/MHz

Timer/Counter Channel 0.02 0.10

Timer/Counter Block (3 Channels) 0.06 0.31

USART 0.04 0.18

4AT91R40807

1367C–01/02

Thermal and

Reliability

Considerations

Thermal Data In Table 4, the device lifetime is estimated with the MIL-217 standard in the “moderately con-

trolled” environmental model (this model is described as corresponding to an installation in a

permanent rack with adequate cooling air), depending on the device Junction Temperature.

(For details see the section “Junction Temperature” on page 5.)

Note that the user must be extremely cautious with this MTBF calculation: as the MIL-217

model is pessimistic with respect to observed values due to the way the data/models are

obtained (test under severe conditions). The life test results that have been measured are

always better than the predicted ones.

Table 5 summarizes the thermal resistance data related to the package of interest

Reliability Data The number of gates and the device die size are provided for the user to calculate reliability

data with another standard and/or in another environmental model.

Table 4. MTBF Versus Junction Temperature

Junction Temperature (TJ) (°C) Estimated Lifetime (MTBF) (Year)

100 13

125 7

150 4

175 2

Table 5. Thermal Resistance Data

Symbol Parameter Condition Package Typ Units

θJA=Junction-to-ambient thermal resistance Still Air TQFP100 40 °C/W

θJC Junction-to-case thermal resistance TQFP100 6.4

Table 6. Reliability Data

Parameter Data Unit

Number of Logic Gates 272 K gates

Number of Memory Gates 7,006 K gates

Device Die Size 59.8 mm2

AT91R40807

1367C–01/02

Junction

Temperature

The average chip-junction temperature TJ in °C can be obtained from the following:

Where:

•θJA = package thermal resistance, Junction-to-ambient (°C/W), provided in Table 5 on

page 4.

•θJC = package thermal resistance, Junction-to-case thermal resistance (°C/W), provided in

Table 5 on page 4.

•θHEAT SINK = cooling device thermal resistance (°C/W), provided in the device datasheet.

•P

D = device power consumption (W) estimated from data provided in the section “Power

Consumption” on page 3.

•T

A = ambient temperature (°C).

From the first equation, the user can derive the estimated lifetime of the chip and thereby

decide if a cooling device is necessary or not. If a cooling device is to be fitted on the chip, the

second equation should be used to compute the resulting average chip-junction temperature

TJ in °C.

TJTAPDθJA

×()+=

TJTAP(Dθ( HEATSINK

×θ

JC ))++=

6AT91R40807

1367C–01/02

Conditions

Timing Results The delays are given as typical values in the following conditions:

•VDD = 3.3V

• Ambient Temperature = 25°C

• Load Capacitance is 0 pF

• The output level change detection is (0.5 x VDD).

• The input level is (0.3 x VDD) for a low-level detection and is (0.7 x VDD) for a high level

detection.

The minimum and maximum values given in the AC characteristics tables of this datasheet

take into account the process variation and the design.

In order to obtain the timing for other conditions, the following equation should be used:

where

•δT° is the derating factor in temperature given in the Figure 1 on page 7.

•δVDD is the derating factor for the Power Supply given in Figure 2 on page 7.

•t

datasheet is the minimum or maximum timing value given in this datasheet for a load

capacitance of 0 pF.

•C

Signal is the capacitance load on the considered output pin.(1)

•δCSignal is the load derating factor depending on the capacitance load on the related output

pins given in Min and Max in this datasheet.

The input delays are given as typical value.

Note: 1. The user must take into account the package capacitance load contribution (CIN) described

in Table 1 on page 2.

tδT°δVDD

×t(DATASHEET

×CSIGNAL δCSIGNAL

×())+=

AT91R40807

1367C–01/02

Temperature

Derating Factor

Figure 1. Derating Curve for Different Operating Temperatures

Voltage Derating

Factor

Figure 2. Derating Curve for Different Supply Voltages

Note: This derating factor is applicable only to timings related to output pins.

0.8

0.9

1.1

1.2

1.3

-60 -40 -20 0 20 40 60 80 100 120 140 160 180

Operating Temperature (°C)

Derating Factor

Derating Factor for

Typ Case is 1

0.90

0.95

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

2.02.22.42.62.83.03.23.43.6

Supply Voltage (V)

Derating Factor

Derating Factor for

Typ Case is 1

8AT91R40807

1367C–01/02

Clock Waveforms

Figure 3. Clock Waveform

Table 7. Clock Waveform Parameters

Symbol Parameter Conditions Min Max Units

1/(tCP) Oscillator Frequency 42.6 MHz

tCP Oscillator Period 23.5

tCH High Half-period 0.45 x tCP 0.55 x tCP

tCL Low Half-period 0.45 x tCP 0.55 x tCP

trRising Edge TBD

tfFalling Edge TBD

Table 8. Clock Propagation Times

Symbol Parameter Conditions Min Max Units

tCDLH Rising Edge Propagation Time CMCKO = 0 pF 4.6 7.2 ns

CMCKO derating 0.032 0.05 ns/pF

tCDHL Falling Edge Propagation Time CMCKO = 0 pF 5.8 9.0 ns

CMCKO derating 0.032 0.05 ns/pF

tCH

tCL

tCP

MCKI

MCKO

tCDLH tCDHL

0.7 VDD

trtf

0.3 VDD

0.5 VDD 0.5 VDD

AT91R40807

1367C–01/02

Figure 4. MCKO Relative to NRST

Table 9. NRST to MCKO

Symbol Parameter Min Max Units

tDNRST Rising Edge to MCKO Valid Time 3(tCP/2) 7(tCP/2) ns

NRST

MCKO

10 AT91R40807

1367C–01/02

AC Characteristics

EBI Signals Relative to MCKI

The following tables show timings relative to operating condition limits defined in in the section “Conditions” on page 6.

See Figure 5 on page 14.

Table 10. General-purpose EBI Signals

Symbol Parameter Conditions Min Max Units

EBI1MCKI Falling to NUB Valid CNUB = 0 pF 5.9 11.6 ns

CNUB derating 0.032 0.05 ns/pF

EBI2MCKI Falling to NLB/A0 Valid CNLB = 0 pF 5.2 8.8 ns

CNLB derating 0.032 0.05 ns/pF

EBI3MCKI Falling to A1 - A23 Valid CADD = 0 pF 4.7 9.9 ns

CADD derating 0.032 0.05 ns/pF

EBI4MCKI Falling to Chip Select Change CNCS = 0 pF 5.3 10.8 ns

CNCS derating 0.032 0.05 ns/pF

EBI5NWAIT Setup before MCKI Rising 0.5 ns

EBI6NWAIT Hold after MCKI Rising 3.0 ns

AT91R40807

1367C–01/02

Notes: 1. The derating factor is not to be applied to tCH or tCP

2. n = number of wait states inserted.

Table 11. EBI Write Signals

Symbol Parameter Conditions Min Max Units

EBI7MCKI Rising to NWR Active (No Wait States) CNWR = 0 pF 4.3 7.5 ns

CNWR derating 0.032 0.05 ns/pF

EBI8MCKI Rising to NWR Active (Wait States) CNWR = 0 pF 4.9 8.5 ns

CNWR derating 0.032 0.05 ns/pF

EBI9MCKI Falling to NWR Inactive (No Wait States) CNWR = 0 pF 5.1 8.8 ns

CNWR derating 0.032 0.049 ns/pF

EBI10 MCKI Rising to NWR Inactive (Wait States) CNWR = 0 pF 4.6 8.0 ns

CNWR derating 0.032 0.049 ns/pF

EBI11 MCKI Rising to D0 - D15 Out Valid CDATA = 0 pF 4.0 9.1 ns

CDATA derating 0 0.051 ns/pF

EBI12 NWR High to NUB Change CNUB = 0 pF 3.3 7.2 ns

CNUB derating 0.031 0.05 ns/pF

EBI13 NWR High to NLB/A0 Change CNLB = 0 pF 3.2 5.6 ns

CNLB derating 0.032 0.05 ns/pF

EBI14 NWR High to A1 - A23 Change CADD = 0 pF 2.7 7.1 ns

CADD derating 0.032 0.05 ns/pF

EBI15 NWR High to Chip Select Inactive CNCS = 0 pF 3.0 6.8 ns

CNCS derating 0.031 0.05 ns/pF

EBI16

Data Out Valid before NWR High (No Wait

States) (1)

C = 0 pF tCH - 1.1 ns

CDATA derating -0.051 ns/pF

CNWR derating 0.049 ns/pF

EBI17

Data Out Valid before NWR High

(Wait States) (1)

C = 0 pF n x tCP - 1.9 (2) ns

CDATA derating -0.051 ns/pF

CNWR derating 0.049 ns/pF

EBI18 Data Out Valid after NWR High 2.1 ns

EBI19

NWR Minimum Pulse Width

(No Wait States) (1)

tCH + 0.4 ns

EBI20 NWR Minimum Pulse Width (Wait States) (1) n x tCP - 1.2 (2) ns

12 AT91R40807

1367C–01/02

Notes: 1. Early Read Protocol.

2. Standard Read Protocol.

3. The derating factor is not to be applied to tCH or tCP

4. n = number of standard wait states.

5. Only one of these two timings needs to be met.

Table 12. EBI Read Signals

Symbol Parameter Conditions Min Max Units

EBI21 MCKI Falling to NRD Active (1) CNRD = 0 pF 5.5 9.6 ns

CNRD derating 0.032 0.05 ns/pF

EBI22 MCKI Rising to NRD Active (2) CNRD = 0 pF 4.1 8.5 ns

CNRD derating 0.032 0.05 ns/pF

EBI23 MCKI Falling to NRD Inactive (1) CNRD = 0 pF 5.5 8.8 ns

CNRD derating 0.031 0.049 ns/pF

EBI24 MCKI Falling to NRD Inactive (2) CNRD = 0 pF 5.1 8.0 ns

CNRD derating 0.031 0.049 ns/pF

EBI25 D0 - D15 in Setup Before MCKI Falling (5) -1.2 ns

EBI26 D0 - D15 in Hold After MCKI Falling (5) 3.5 ns

EBI27 NRD High to NUB Change CNUB = 0 pF 3.6 7.3 ns

CNUB derating 0.031 0.05 ns/pF

EBI28 NRD High to NLB/A0 Change CNLB = 0 pF 3.2 5.1 ns

CNLB derating 0.032 0.05 ns/pF

EBI29 NRD High to A1 - A23 Change CADD = 0 pF 2.8 6.5 ns

CADD derating 0.032 0.049 ns/pF

EBI30 NRD High to Chip Select Inactive CNCS = 0 pF 3.0 6.2 ns

CNCS derating 0.031 0.049 ns/pF

EBI31 Data Setup Before NRD High (5) CNRD = 0 pF 6.9 ns

CNRD derating 0.048 ns/pF

EBI32 Data Hold After NRD High (5) CNRD = 0 pF -2.9 ns

CNRD derating -0.031 ns/pF

EBI33 NRD Minimum Pulse Width (1, 3)

CNRD = 0 pF (n + 1) x

tCP - 1.1(4)

CNRD derating -0.001 ns/pF

EBI34 NRD Minimum Pulse Width (2, 3)

CNRD = 0 pF n x tCP +

(tCH - 0.5)(4)

CNRD derating -0.001 ns/pF

AT91R40807

1367C–01/02

Notes: 1. If this condition is not met, the action depends on the read protocol intended for use.

• Early Read Protocol: Programing an additional tDF (Data Float Output Time) cycle.

• Standard Read Protocol: Programming an additional tDF Cycle and an additional wait state.

2. Applicable only for chip select programmed with 0 wait state. If this condition is not met, at least one wait state must be

programmed.

Table 13. EBI Read and Write Control Signals. Capacitance Limitation

Symbol Parameter Conditions Min Max Units

TCPLNRD(1) Master Clock Low Due to NRD Capacitance CNRD = 0 pF 9.2 ns

CNRD derating 0.048 ns/pF

TCPLNWR(2) Master CLock Low Due to NWR Capacitance CNWR = 0 pF 9.6 ns

CNWR derating 0.049 ns/pF

14 AT91R40807

1367C–01/02

Figure 5. EBI Signals Relative to MCKI

Notes: 1. Early Read Protocol.

2. Standard Read Protocol.

NCS

A1 - A23

NRD(1)

D0 - D15 Read

MCKI

NUB/NLB/A0

NRD(2)

NWAIT

NWR (No Wait States)

D0 - D15 to Write

NWR (Wait States)

No Wait Wait

EBI1/EBI2

EBI3

EBI4

EBI5EBI6

EBI7EBI9

EBI8EBI10

EBI11

EBI21

EBI22

EBI25 EBI26

EBI23

EBI4

EBI27-30

EBI12-15

EBI16 EBI18 EBI18

EBI33

EBI24

EBI34

EBI31 EBI32

EBI19

EBI20

EBI17

AT91R40807

1367C–01/02

Peripheral Signals

USART Signals The inputs must meet the minimum pulse width and period constraints shown in Table 14 and

Table 15, and represented in Figure 6.

Figure 6. USART Signals

Table 14. USART Asynchronous Mode Input Minimum Pulse Width

Symbol Parameter Min Pulse Width Units

US1SCK/RXD Minimum Pulse Width 5(tCP/2) ns

Table 15. USART Minimum Input Period

Symbol Parameter Min Input Period Units

US2SCK Minimum Input Period 9(tCP/2) ns

SCK

RXD

US1

US2

16 AT91R40807

1367C–01/02

Timer/Counter Signals Due to internal synchronization of input signals, there is a delay between an input event and a

corresponding output event. This delay is 3(tCP) in Waveform Event Detection mode and 4(tCP)

in Waveform Total-count Detection mode. The inputs have to meet the minimum pulse width

and minimum input period shown in Tables 16 and 17 and as represented in Figure 7.

Figure 7. Timer Input

Reset Signals A minimum pulse width is necessary as shown in Table 18 and as represented in Figure 8.

Figure 8. Reset Signal

Only the NRST rising edge is synchronized with MCKI. The falling edge is asynchronous.

Table 16. Timer Input Minimum Pulse Width

Symbol Parameter Min Pulse Width Units

TC1TCLK/TIOA/TIOB Minimum Pulse Width 3(tCP/2) ns

Table 17. Timer Input Minimum Period

Symbol Parameter Min Input Period Units

TC2 TCLK/TIOA/TIOB Minimum Input Period 5(tCP/2) ns

MCKI

TIOA/TIOB/TCLK

TC1

3(tCP/2) 3(tCP/2)

TC2

Table 18. Reset Minimum Pulse Width

Symbol Parameter Min Pulse Width Units

RST1NRST Minimum Pulse Width 10(tCP)ns

NRST

RST1

AT91R40807

1367C–01/02

Advanced Interrupt

Controller Signals

Inputs must meet the minimum pulse width and mimimum input period shown in Table 19 and

Table 20 and represented in Figure 9.

Figure 9. AIC Signals

Parallel I/O Signals The inputs must meet the minimum pulse width shown in Table 21 and as represented in Fig-

ure 10.

Figure 10. PIO Signal

Table 19. AIC Input Minimum Pulse Width

Symbol Parameter Min Pulse Width Unit

AIC1FIQ/IRQ0/IRQ1/IRQ2/IRQ3 Minimum

Pulse Width

3(tCP/2) ns

Table 20. AIC Input Minimum Period

Symbol Parameter Min Input Period Unit

AIC2AIC Minimum Input Period 5(tCP/2) ns

MCKI

FIQ/IRQ0/IRQ1/IRQ2/IRQ3

Input

AIC1

AIC2

Table 21. PIO Input Minimum Pulse Width

Symbol Parameter Min Pulse Width Units

PIO1PIO Input Minimum Pulse Width 3(tCP/2) ns

PIO

Inputs

PIO1

18 AT91R40807

1367C–01/02

ICE Interface Signals

Figure 11. ICE Interface Signals

Table 22. ICE Interface Timing Specifications

Symbol Parameter Conditions Min Max Units

ICE0NTRST Minimum Pulse width 18.8

ICE1NTRST High Recovery to TCK High 1.3

ICE2NTRST High Removal from TCK High -0.3

ICE3TCK Low Half-period 41.7

ICE4TCK High Half-period 40.9

ICE5TCK Period 82.5

ICE6TDI, TMS Setup Before TCK High 0.5

ICE7TDI, TMS Hold After TCK High 0.6

ICE8TDO Hold Time 5.0

ICE9TCK Low to TDO Valid CTDO = 0 pF 10.0

CTDO derating 0.05 ns/pF

TCK

ICE3ICE4

ICE7

ICE6

ICE9

ICE8

MS/TDI

TDO

ICE0

ICE5

NTRST

ICE1ICE2

AT91R40807

1367C–01/02

Document Details

Title AT91R40807 Electrical Characteristics

Literature Number Lit# 1367C

Revision History

Version A Publication Date: Apr, 2000

Version B Publication Date: Nov, 2000

Version C Publication Date: 10, Dec, 2001

Revisions Since Previous Version published on Intranet

Page: 1 “Features” “Fully Static Operation: 0 Hz to 33 MHz Internal Frequency Range at 3.0 V, 85°C”

..... frequency and range modified

Page: 4 “Reliability Data” paragraph modified and new table inserted. “Table 6 Reliability Data”

Page: 6 “Timing Results” Cross reference added to CSIGNAL part of equation.

Page: 8 Table 7. Master Clock Waveform Parameters. Values have been changed for Oscillator Fre-

quency and Oscillator Period. Some master clock parameters deleted.

Page: 10 Table 10. General-purpose EBI Signals. EBI4, Conditions are changed.

Page: 13 New table inserted. Table 13. Read and Write Control Signals. Capacitance Limitation. This

table adds understanding to EBI Signals Relative to MCK.

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty

which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors

which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does

not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted

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1367C–01/02/0M