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FEATURES
D24-Bit Resolution
DAnalog Performance (VCC = 5 V):
− Dynamic Range: 117 dB (Typically)
− SNR: 117 dB (Typically)
− THD+N: 0.0004% (Typically)
− Full-Scale Output (At Post Amp): 2.2-Vrms
DDifferential Current Output: ±2.48 mA
D8× Oversampling Digital Filter:
− Stop-Band Attenuation: −82 dB
− Pass-Band Ripple: ±0.002 dB
DSampling Frequency of 10 kHz to 200 kHz
DSystem Clock: 128, 192, 256, 384, 512, or
768 fS With Auto Detect
DAccepts 16-, 20-, and 24-Bit Audio Data
DData Formats: Standard, I2S, and
Left-Justified
DDigital De-Emphasis
DSoft Mute
DZero Flags for Each Output
DDual Supply Operation:
− 5 V for Analog
− 3.3 V for Digital
D5-V Tolerant Digital Inputs
DSmall 28-Lead SSOP Package
APPLICATIONS
DA/V Receivers
DDVD Movie Players
DSACD Player
DHDTV Receivers
DCar Audio Systems
DDigital Multi-Track Recorders
DOther Applications Requiring 24-Bit Audio
DESCRIPTION
The PCM1730 is a CMOS, monolithic integrated circuit
that includes stereo digital-to-analog converters and
support circuitry in a small 28-lead SSOP package. The
data converters utilize Texas Instruments’ advanced
segment DAC architecture to achieve excellent
dynamic performance and improved tolerance to clock
jitter. The PCM1730 provides balanced current outputs,
allowing the user to optimize analog performance
externally. Sampling rates up to 200 kHz are supported.
PACKAGE/ORDERING INFORMATION
PRODUCT PACKAGE PACKAGE
DRAWING
NUMBER
OPERATING
TEMPERATURE RANGE PACKAGE
MARKING ORDERING NUMBER†
PCM1730E
28-Lead SSOP
28DB
–25°C to 85°C
PCM1730E
PCM1730E
PCM1730E 28-Lead SSOP 28DB –25°C to 85°C PCM1730E PCM1730E/2K
†Models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /2K indicates 2000
devices per reel). Ordering 2000 pieces of PCM1730E/2K will get a single 2000-piece tape and reel.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Copyright 2001, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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pin assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RST
ZEROL
ZEROR
LRCK
DATA
BCK
SCKI
DGND
VDD
DEMP0
DEMP1
FMT0
FMT1
FMT2
VCC3
AGND2
IOUTL−
IOUTL+
VCC2
VCC1
VCOM3
IREF
VCOM2
VCOM1
AGND1
IOUTR+
IOUTR−
MUTE
SSOP PACKAGE
(TOP VIEW)
functional block diagram
System Clock
Manager
Serial
Input
I/F
Function
Control
I/F
System Clock
Zero Detect Power Supply
ZEROL
LRCK
DATA
BCK
RST
MUTE
FMT0
FMT2
FMT1
DEMP0
DEMP1
SCKI
Digital
Filter
Advanced
Segment
DAC
Modulator
IOUTL+
Current
Segment
DAC IOUTL−
IOUTR−
Current
Segment
DAC IOUTR+
IREF
Bias
and
Vref VCOM1
VCOM3
VCOM2
AGND2
VDD
DGND
VCC1
VCC2
VCC3
AGND1
I/V and Filter
I/V and Filter
ZEROR
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Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME PIN
I/O
DESCRIPTION
AGND1 18 − Analog ground
AGND2 27 − Analog ground
BCK 6 I Bit clock input†
DATA 5 I Serial audio data input†
DEMP0 10 I De-emphasis control‡
DEMP1 11 IDe-emphasis control‡
DGND 8 − Digital ground
FMT0 12 I Audio data format select†
FMT1 13 I Audio data format select†
FMT2 14 I Audio data format select†
IOUTL–26 O L-channel analog current output –
IOUTL+ 25 O L-channel analog current output +
IOUTR–16 O R-channel analog current output –
IOUTR+ 17 O R-channel analog current output +
IREF 21 − Output current reference bias pin. Connect a 16-kΩ resistor to GND.
LRCK 4 I Left and right clock (fS)†
MUTE 15 I Analog output mute control†
RST 1 I Reset†
SCKI 7 I System clock input†
VCC1 23 − Analog supply, 5 V
VCC2 24 − Analog supply, 5 V
VCC3 28 − Analog power supply, 5 V
VCOM1 19 − Internal bias decoupling pin
VCOM2 20 − Common voltage for I/V
VCOM3 22 − Internal bias decoupling pin
VDD 9 − Digital supply, 3.3 V
ZEROL 2 O Zero flag for L-channel
ZEROR 3 O Zero flag for R-channel
†Schmitt-trigger input, 5-V tolerant
‡Schmitt-trigger input with internal pulldown, 5-V tolerant
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absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage: VCC1, VCC2, VCC36.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage: VDD 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage differences: VCC1, VCC2, and VCC3±0.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ground voltage differences: AGND1, AGND2, and DGND ±0.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage: LRCK, DATA, BCK, SCKI, DEMP0, DEMP1, FMT0, FMT1,
FMT2, RST, and MUTE –0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage: ZEROL, ZEROR –0.3 V to (VDD + 0.3 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog input voltage: –0.3 V to (VCC + 0.3 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current (any pins except supplies) ±10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient temperature under bias, TA –40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature, Tstg –55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Junction temperature, TJ 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature (soldering) 260°C, 5 s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package temperature (IR reflow, peak) 235°C, 10 s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
electrical characteristics, all specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system
clock = 256 fS and 24-bit data (unless otherwise noted)
PARAMETER
TEST CONDITIONS
PCM1730E
UNIT
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
RESOLUTION 24 Bits
DATA FORMAT
Audio data interface format Standard, I2S, left justified
Audio data bit length 16, 20, 24-bits selectable
Audio data format MSB first, 2’s complement
fSSampling frequency 10 200 kHz
System clock frequency 128, 192, 256, 384, 512, 768 fS
DIGITAL INPUT/OUTPUT
Logic family TTL compatible
VIH High-level input logic level 2 VDC
VIL Low-level input logic level 0.8 VDC
IIH
Input logic current (see Note 1)
VIN = VDD 10
A
IIL Input logic current (see Note 1) VIN = 0 V −10 µA
IIH
Input logic current (see Note 2)
VIN = VDD 65 100
A
IIL Input logic current (see Note 2) VIN = 0 V −10 µA
VOH High-level output logic level IOH = −2 mA 2.4 VDC
VOL Low-level output logic level IOL = 2 mA 1 VDC
NOTES: 1. Pins 1, 4, 5, 6, 7, 12, 13, 14, and 15: RST, LRCK, DATA, BCK, SCKI, FMT0, FMT1, FMT2, and MUTE
2. Pins 10 and 11: DEMP0, DEMP1
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electrical characteristics, all specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system
clock = 256 fS and 24-bit data (unless otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
PCM1730E
UNIT
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
DYNAMIC PERFORMANCE (see Note 3)
Total harmonic distortion plus
fS = 44.1 kHz 0.0004% 0.008%
THD+N Total harmonic distortion plus
noise
V
OUT
= 0 dB fS = 96 kHz 0.0006%
THD+N
noise
VOUT = 0 dB
fS = 192 kHz 0.0012%
EIAJ, A-weighted, fS = 44.1 kHz 114 117
Dynamic range EIAJ, A-weighted, fS = 96 kHz
117
dB
Dynamic range
EIAJ, A-weighted, fS = 192 kHz 117
dB
EIAJ, A-weighted, fS = 44.1 kHz 114 117
Signal-to-noise ratio EIAJ, A-weighted, fS = 96 kHz
117
dB
Signal-to-noise ratio
EIAJ, A-weighted, fS = 192 kHz 117
dB
fS = 44.1 kHz 110 115
Channel separation fS = 96 kHz 113 dB
Channel separation
fS = 192 kHz 111
dB
Level linearity error VOUT = –110 dB ±1 dB
DC ACCURACY
VCOM2 voltage 2.45 V
VCOM2 output current Delta VCOM2 < 5% 100 µA
Gain error ±2 %/FSR
Gain mismatch, channel-to-
channel ±0.5 %/FSR
Bipolar zero error At BPZ ±0.5 %/FSR
ANALOG OUTPUT
Output current Full scale (−0 dB) ±2.48 mAp-p
Center current BPZ input 0 mAp-p
DIGITAL FILTER PERFORMANCE—FILTER CHARACTERISTICS
Pass band
±0.002 dB 0.454 fS
Pass band −3 dB 0.49 fS
Stop band 0.546 fS
Pass-band ripple −75 ±0.002 dB
Stop-band attenuation
Stop band = 0.546 fSdB
Stop-band attenuation Stop band = 0.567 fS−82 dB
Delay time 29/fSs
De-emphasis error ±0.1 dB
NOTE 3: Analog performance specifications are measured by audio precision II under averaging mode. At 44.1-kHz operation, measurement
bandwidth is limited to 20 kHz. At 96-kHz and 192-kHz operation, measurement bandwidth is limited to 40 kHz.
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electrical characteristics, all specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system
clock = 256 fS and 24-bit data (unless otherwise noted)(continued)
PARAMETER
TEST CONDITIONS
PCM1730E
UNIT
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
POWER SUPPLY REQUIREMENTS
VDD
Voltage range
3 3.3 3.6
VDC
VCC Voltage range 4.75 5 5.25 VDC
fS = 44.1 kHz 7 9.8
I
DD
fS = 96 kHz 15
IDD
Supply current
fS = 192 kHz 30
mA
Supply current fS = 44.1 kHz 33 46.2 mA
I
CC
fS = 96 kHz 34.5
ICC
fS = 192 kHz 36.5
fS = 44.1 kHz 188 263
P
D
Power dissipation fS = 96 kHz 222 mW
PD
Power dissipation
fS = 192 kHz 282
mW
TEMPERATURE RANGE
Operation temperature −25 85 °C
θJA Thermal resistance 28-pin SSOP 100 °C/W
functional description
system clock and reset functions
The PCM1730 requires a system clock for operating the digital interpolation filters and advanced segment DAC
modulators. The system clock is applied at the SCKI input (pin 7). The PCM1730 has a system clock detection
circuit, which automatically senses if the system clock is operating at 128 fS to 768 f S. Table 1 shows examples
of system clock frequencies for common audio sampling rates.
Figure 1 shows the timing requirements for the system clock input. For optimal performance, it is important to
use a clock source with low phase jitter and noise. Texas Instruments’ PLL1700 multi-clock generator is an
excellent choice for providing the PCM1730 system clock.
System Clock
Pulse Cycle Time
System Clock 2 V
0.8 V
tw(SCKH)
tw(SCKL)
PARAMETER MIN UNIT
System clock pulse width high, tw(SCKH) 5 ns
System clock pulse width high, tw(SCKL) 5 ns
Figure 1. System Clock Input Timing
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system clock and reset functions (continued)
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SAMPLING FREQUENCY
SYSTEM CLOCK FREQUENCY (fSCLK) (MHz)
SAMPLING FREQUENCY
128 fS192 fS256 fS384 fS512 fS768 fS
32 kHz 4.096 6.144 8.192 12.288 16.384 24.576
44.1 kHz 5.6488 8.4672 11.2896 16.9344 22.5792 33.8688
48 kHz 6.144 9.216 12.288 18.432 24.576 36.864
96 kHz 12.288 18.432 24.576 36.864 49.152 73.728
192 kHz 24.576 36.864 49.152 73.728 See Note 4 See Note 4
NOTE 4: This system clock rate is not supported for the given sampling frequency.
power-on and external reset functions
The PCM1730 includes a power-on reset function. Figure 2 shows the operation of this function. The system
clock input at SCKI should be active for at least one clock period prior to VDD = 2 V. With the system clock active
and VDD > 2 V, the power-on reset function will be enabled. The initialization sequence requires 1024 system
clocks from the time VDD > 2 V. The PCM1730 also includes an external reset capability using the RST input
(pin 1). This allows an external controller or master reset circuit to force the PCM1730 to initialize to its reset
state. Figure 3 shows the external reset operation and timing. The RST pin is set to logic 0 for a minimum of
20 ns. The RST pin is then set to a logic 1 state, which starts the initialization sequence, which requires 1024
system clock periods. The external reset is especially useful in applications where there is a delay between
PCM1730 power up and system clock activation. In this case, the RST pin should be held at a logic 0 level until
the system clock has been activated. The RST pin may then be set to logic 1 state to start the initialization
sequence.
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functional description (continued)
Reset Reset Removal
1024 System Clocks
VDD 2.4 V (Max)
2 V (Typ)
1.6 V (Min)
Internal Reset
System Clock
Figure 2. Power-On Reset Timing
Reset Reset Removal
1024 System Clocks
Internal Reset
System Clock
RST (Pin 36) 50% of VDD
t(RST)
PARAMETER MIN UNIT
Reset pulse width low, t(RST) 20 ns
Figure 3. External Reset Timing
audio data interface
audio serial interface
The audio serial interface for the PCM1730 is comprised of a 3-wire synchronous serial port. It includes LRCK
(pin 4), BCK (pin 6), and DATA (pin 5). BCK is the serial audio bit clock, and it is used to clock the serial data
present on D ATA into the audio interface’s serial shift register. Serial data is clocked into the PCM1730 on the
rising edge of BCK. LRCK is the serial audio left/right word clock. It is used to latch serial data into the serial
audio interface’s internal registers.
LRCK should be synchronous with the system clock. In the event these clocks are not synchronized, the
PCM1730 can compensate for the phase dif ference internally. If the phase difference between LRCK and SCKI
is greater than 6-bit clocks (BCK), the synchronization is performed internally. While the synchronization is
processing, the analog output is forced to bipolar zero level. The synchronization typically occurs in less than
one cycle of LRCK.
Ideally, it i s recommended that LRCK and BCK be derived from the system clock input or output, SCKI or SCKO.
The left/right clock, LRCK, is operated at the sampling frequency, fS.
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audio data formats and timing
The PCM1730 supports industry-standard audio data formats, including standard right-justified, I2S, and
left-justified. The data formats are shown in Figure 4. Data formats are selected by using the FMT2 (pin 14),
FMT1 (pin 13) and FMT0 (pin 12) as shown in Table 2. All formats require binary 2’s complement, MSB-first
audio data. Figure 5 shows a detailed timing diagram for the serial audio interface.
Table 2. Audio Data Format Select
FMT2
(PIN 14) FMT1
(PIN 13) FMT0
(PIN 12) FORMAT
Low Low Low 16-bit standard format, right-justified
Low Low High 20-bit standard format, right-justified
Low High Low 24-bit standard format, right-justified
Low High High 24-bit MSB-first, left-justified format
High Low Low 16-bit I2S format
High Low High 24-bit I2S format
High High Low Reserved
High High High Reserved
zero detect
When the PCM1730 detects that the audio input data in L-channel or R-channel is continuously zero for 1024
fS, the PCM1730 sets ZEROL (pin 2) or ZEROR (pin 3) to high.
soft mute
The PCM1730 supports mute operation. When MUTE (pin 15) is set to HIGH, both analog outputs are turned
to bipolar zero levels by −0.5-dB steps with transition speed of 1/fS per step. This system provides pop-free
muting of DAC output.
de-emphasis
The PCM1730 supports de-emphasis filter performance for sampling frequency 32 kHz, 44.1 kHz, 48 kHz.
Sampling frequency is selectable by using DEMP1 (pin 11) DEMP0 (pin 10) as shown in Table 3.
Table 3. De-Emphasis Control
DEMP1 (PIN 11) DEMP0(PIN 10) DE-EMPHASIS FUNCTION
Low Low Disabled
Low High 48 kHz
High Low 44.1 kHz
High High 32 kHz
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functional description (continued)
(1) Standard Data Format (Right Justified); L-channel = High, R-channel = Low
14 15 16 1 2 15 16
MSB LSB
1 2 15 16
18 19 20
MSB LSB
1 2 19 20 1 2 19 20
22 23 24
MSB LSB
1 232 24 1 232 24
BCK
L-Channel
DATA
R-Channel
1/fS
DATA
DATA
LRCK
Audio Data Word = 16 Bit
Audio Data Word = 20 Bit
Audio Data Word = 24 Bit
(2) Left Justified Data Format: L-channel = High, R-channel = Low
21
MSB LSB
1 2 24 1 2 24
BCK
L-Channel
DATA
R-Channel
1/fS
LRCK
Audio Data Word = 24 Bit
23 23
(3) I2S Data Format: L-channel = Low, R-channel = High
MSB LSB
1 2 24 211 2 24
21
MSB LSB
1 2 16 1 2 1615 15
23 23
BCK
L-Channel
DATA
R-Channel
1/fS
LRCK
Audio Data Word = 24 Bit
DATA
Audio Data Word = 16 Bit
Figure 4. Audio Data Input Formats
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functional description (continued)
DATA
t(BCH)
50% of VDD
BCK
LRCK
t(BCL) t(LB)
t(BCY) t(BL)
tsu th
50% of VDD
50% of VDD
PARAMETER MIN UNIT
BCK pulse cycle time, t(BCY) 70 ns
BCK pulse width low, tw(BCL) 30 ns
BCK pulse width high, tw(BCH) 30 ns
BCK rising edge to LRCK edge, t(BL) 10 ns
LRCK edge to BCK rising edge, t(LB) 10 ns
DATA set up time, tsu 10 ns
DATA hold time, th10 ns
LRCK clock duty 50% ±2 bit clock
Figure 5. Audio Interface Timing
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typical connection diagram
DATA 24
23
22
21
20
19
18
17
16
15
5
6
7
8
9
10
11
12
13
14
+
3.3 V
PCM1730E
BCK
SCKI
DGND
VDD
DEMP0
DEMP1
FMT0
FMT1
FMT2
VCC2
IOUTR+
VCC1
VCOM3
IREF
VCOM2
IOUTR−
MUTE
AGND1
VCOM1
−
+
RST
1
2
3
4
ZEROL
ZEROR
LRCK
28
27
26
25
VCC3
AGND2
IOUTL−
IOUTL+
Audio DATA
Bit Clock
System Clock
L/R Clock (fS)
+
Controller
+
−
+
−
+VOUT
L-Channe
l
5 V
−
+
+
−
−
+VOUT
R-Channe
l
+
Analog Output Stage
15 V −15 V
NOTE: Regarding R/C values for analog output stage, see Figure 9.
Figure 6. Typical Application Circuit for Standard PCM Audio Operation
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analog outputs
24
23
22
21
20
19
18
17
16
15
+
PCM1730E
VCC2
IOUTR+
VCC1
VCOM3
IREF
VCOM2
IOUTR−
MUTE
AGND1
VCOM1
R11
−
+
28
27
26
25
VCC3
AGND2
IOUTL−
IOUTL+
C13
+
−
R12
C14
R13
R14
C15
+
−
+
R16
R17
R15
C17
VOUT
L-Channel
R1
16 kΩ
10 µF
R21
−
+
C23
+
−
R22
C24
R23
R24
C25 −
+
R26
R27
R25
C27
VOUT
R-Channel
+
C16
R18
C26
R28
5 V
10 µF
0.1 µF
10 µF+
10 µF
C11
C12
C21
C22
NOTE: Example R/C values for fC 45 kHz
R11–R18, R21–R28: 620 Ω, C11, C12, C21, C22: not populated, C13, C14, C23, C24: 5600 pF, C15, C25: 8200 pF, C16, C17, C26,
C27: 1800 pF
Figure 7. Typical Application for Analog Output Stage
analog output level and I/V converter
The signal level of DAC current output pins (IOUTL+, IOUTL–, IOUTR+, IOUTR–) is ±2.48 mAp-p at 0 dB (full scale).
The voltage output of the I/V converter is given by following equation:
VOUT = ±2.48 mAp−p × Rf
Here, Rf is the feedback resistor in the I/V conversion circuit, R11, R12, R21, R22 on typical application circuit.
The common level of the I/V conversion circuit must be same as common level of DAC IOUT which is given by
VCOM2 reference voltage, which is 2.48 V dc typically. The noninverting inputs of the op amps shown in the I/V
circuits are connected to VCOM2 to provide the common bias voltage.
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op amp for I/V converter circuit
OPA627BP/BM or NE5534 type op amp is recommended for I/V conversion circuit to obtain specified audio
performance. Dynamic performance such as gain bandwidth, settling time and slew rate of op amp gives audio
dynamic performance at I/V section. Input noise specification of op amp should be considered to obtain 120 dB
S/N ratio.
analog gain by balanced amp
The I/V converters are followed by balanced amplifier stages, which sum the differential signals for each
channel, creating a single-ended voltage output. In addition, the balanced amplifiers provide a second-order
low pass filter function, which band limits the audio output signal. The cutoff frequency and gain are given by
the external R and C component values. In this case, the cutoff frequency is 45 kHz with a gain of 1. The output
voltage for each channel is 6.2 Vp-p, or 2.2 Vrms.
reference current resistor
As shown in the analog output application circuit, there is a resistor connected from IREF (pin 21) to analog
ground, designated as R1. This resistor sets the current for the internal reference circuit. The value of R1 must
be 16 kΩ ±1% in order to match the specified gain error shown in the specifications table.
theory of operation
Analog Output
Digital Input 24 Bit
8 fSMSB
and
Lower 18 Bit
Upper
6 Bit ICOB
Decoder
3rd-Order
5-Level
Sigma-Delta
Advanced
DWA
Current
Segment
DAC
0−4
Level
0−62
Level 0−66
Figure 8. Advanced Segments DAC
The PCM1730 utilizes Texas Instruments’ newly developed advanced segment DAC architecture to achieve
excellent dynamic performance and improved tolerance to clock jitter. The PCM1730 provides balanced current
outputs, allowing the user to optimize analog performance externally.
Digital input data via digital filter separates into the upper 6 bits and lower the 18 bits. The upper 6 bits are
converted to ICOB (inverted complementary offset binary) code. The lower 18 bits associated with the MSB are
processed by five level third order delta-sigma modulator operated at 64 fS. The one level of the modulator is
equivalent to the 1 LSB of the above code converter. The data groups processed in the ICOB converter and
third order delta-sigma modulator are summed together to be created over the 64 level digital code, and then
processed i n D WA (data weighted averaging) to reduce noise produced by element mismatch. The data of over
64 level via DWA is converted to analog output in the differential current segment portion.
This architecture has overcome the various drawbacks of conventional multi-bit and also achieves excellent
dynamic performance.
considerations for application circuit
PCB layout guidelines
A typical PCB floor plan for the PCM1730 is shown in Figure 9. A ground plane is recommended, with the analog
and digital sections being isolated from one another using a split or cut in the circuit board. The PCM1730 should
be oriented with the digital I/O pins facing the ground plane split/cut to allow for short, direct connections to the
digital audio interface and control signals originating from the digital section of the board.
SLES021 − NOVEMBER 2001
15
www.ti.com
PCB layout guidelines (continued)
Separate power supplies are recommended for the digital and analog sections of the board. This prevents the
switching noise present on the digital supply from contaminating the analog power supply and degrading the
dynamic performance of the D/A converters. In cases where a common 5-V supply must be used for the analog
and digital sections, an inductance (RF choke, ferrite bead) should be placed between the analog and digital
5-V supply connections to avoid coupling of the digital switching noise into the analog circuitry. Figure 10 shows
the recommended approach for single-supply applications.
bypass and decoupling capacitor requirements
Various-sized decoupling capacitors can be used, with no special tolerances being required. All capacitors
should be located as close to the appropriate pins of the PCM1730 as possible to reduce noise pickup from
surrounding circuitry. Aluminum electrolytic capacitors that are designed for hi-fi audio applications are
recommended for larger values, while metal-film or monolithic ceramic capacitors are used for smaller values.
I/V section
I/V conversion circuit by op amp IC and feedback resistor should achieve excellent performance of the
PCM1730. To obtain 0.0004% THD+N, 117-dB signal-to-noise ratio audio performance, THD+N and input noise
performance by the op amp IC should be considered, especially if the input noise of the op amp directly gives
output noise level of the application. The IOUT– pin on the PCM1730 and the inverted input on the I/V amp should
be connected as short distance.
post LPF design
Out-band noise level and attenuated sampling spectrum level are much lower than typical delta-sigma type DAC
due to the combination of a high-performance digital filter and advanced segment DAC architecture. Second-
order or third-order post LPF is recommended as post LPF of the PCM1730. Cutoff frequency of post LPF is
depends on applications to that there are many sampling rate operation such as fS = 44.1 kHz on CDDA,
fS= 96 kHz on DVD−M, fS = 192 kHz on DVD−A.
Digital
Logic
and
Audio
Processor
Digital Power
+VDDGND
Digital Section Analog Section
Return Path for Digital Signals
Analog Power
+VS
AGND −VS
+5VA
Digital
Ground
Analog
Ground
Output
Circuits
PCM1730
AGND
VCC
VDD
DGND
REG
Figure 9. Recommended PCB Layout
SLES021 − NOVEMBER 2001
16 www.ti.com
VDD
Digital Section Analog Section
RF Choke or Ferrite Bead Power Supplies
Common
Ground
Output
Circuits
AGND
VCC
+VS
5 V −VS
AGND
Digital
Ground
VDD
DGND
REG
PCM1730
Figure 10. Single-Supply PCB Layout
SLES021 − NOVEMBER 2001
17
www.ti.com
TYPICAL CHARACTERISTICS
digital filter
de-emphasis off
Figure 11
Frequency [x fs]
−160
−140
−120
−100
−80
−60
−40
−20
0
01234
VCC = 5 V
VDD = 3.3 V
TA = 25°C
Amplitude − dB
AMPLITUDE
vs
FREQUENCY
Figure 12
Frequency [x fs]
−3
−2
−1
0
1
2
3
0.0 0.1 0.2 0.3 0.4 0.5
VCC = 5 V
VDD = 3.3 V
TA = 25°C
Amplitude − dB
AMPLITUDE
vs
FREQUENCY
0.003
0.002
0
−0.001
−0.003
0.001
−0.002
†All specifications at TA = 25°C, VDD = 3.3 V, VCC = 5 V, SCKI = 256 fS (fS = 44.1 kHz), and 24-bit input data (unless otherwise noted)
SLES021 − NOVEMBER 2001
18 www.ti.com
TYPICAL CHARACTERISTICS
de-emphasis error
Figure 13
f − Frequency − kHz
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
02468101214
VCC = 5 V
VDD = 3.3 V
fS = 32 kHz
TA = 25°C
De-emphasis Level − dB
DE-EMPHASIS LEVEL
vs
FREQUENCY
Figure 14
f − Frequency − kHz
−0.5
−0.4
−0.3
−0.2
−0.1
−0.0
0.1
0.2
0.3
0.4
0.5
02468101214
VCC = 5 V
VDD = 3.3 V
fS = 32 kHz
TA = 25°C
De-emphasis Error − dB
DE-EMPHASIS ERROR
vs
FREQUENCY
Figure 15
f − Frequency − kHz
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
02468101214161820
VCC = 5 V
VDD = 3.3 V
fS = 44.1 kHz
TA = 25°C
De-emphasis Level − dB
DE-EMPHASIS LEVEL
vs
FREQUENCY
Figure 16
f − Frequency − kHz
−0.5
−0.4
−0.3
−0.2
−0.1
−0.0
0.1
0.2
0.3
0.4
0.5
02468101214161820
VCC = 5 V
VDD = 3.3 V
fS = 44.1 kHz
TA = 25°C
De-emphasis Error − dB
DE-EMPHASIS ERROR
vs
FREQUENCY
†All specifications at TA = 25°C, VDD = 3.3 V, VCC = 5 V, SCKI = 256 fS (fS = 44.1 kHz), and 24-bit input data (unless otherwise noted)
SLES021 − NOVEMBER 2001
19
www.ti.com
TYPICAL CHARACTERISTICS
de-emphasis error (continued)
Figure 17
f − Frequency − kHz
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
0 2 4 6 8 10121416182022
VCC = 5 V
VDD = 3.3 V
fs = 48 kHz
TA = 25°C
De-emphasis Level − dB
DE-EMPHASIS LEVEL
vs
FREQUENCY
Figure 18
f − Frequency − kHz
−0.5
−0.4
−0.3
−0.2
−0.1
−0.0
0.1
0.2
0.3
0.4
0.5
0 2 4 6 8 10121416182022
VCC = 5 V
VDD = 3.3 V
fS = 48 kHz
TA = 25°C
De-emphasis Error − dB
DE-EMPHASIS ERROR
vs
FREQUENCY
analog dynamic performance
Figure 19
0.00
0.05
0.10
0.15
0.20
4.50 4.75 5.00 5.25 5.50
VCC − Supply Voltage − V
VDD = 3.3 V
TA = 25°C
TOTAL HARMONIC DISTORTION + NOISE
vs
SUPPLY VOLTAGE
0.0020
0.0015
0.0010
0.0005
0.0000
fS = 44.1 kHz
fS = 96 kHz
THD+N − Total Harmonic Distortion + Noise − %
Figure 20
0.00
0.05
0.10
0.15
0.20
−50 −25 0 25 50 75 100
TA − Free-Air Temperature − °C
VCC = 5 V
VDD = 3.3 V
TOTAL HARMONIC DISTORTION + NOISE
vs
FREE-AIR TEMPERATURE
0.0020
0.0015
0.0010
0.0005
0.0000
fS = 44.1 kHz
fS = 96 kHz
THD+N − Total Harmonic Distortion + Noise − %
†All specifications at TA = 25°C, VDD = 3.3 V, VCC = 5 V, SCKI = 256 fS (fS = 44.1 kHz), and 24-bit input data (unless otherwise noted)
SLES021 − NOVEMBER 2001
20 www.ti.com
TYPICAL CHARACTERISTICS
analog dynamic performance (continued)
Figure 21
VCC − Supply Voltage − V
116
117
118
119
120
4.50 4.75 5.00 5.25 5.50
VDD = 3.3 V
TA = 25°C
Dynamic Range − dB
DYNAMIC RANGE
vs
SUPPLY VOLTAGE
fS = 44.1 kHz
fS = 96 kHz
Figure 22
TA − Free-Air Temperature − °C
116
117
118
119
120
−50 −25 0 25 50 75 100
VCC = 5 V
VDD = 3.3 V
Dynamic Range − dB
DYNAMIC RANGE
vs
FREE-AIR TEMPERATURE
fS = 96 kHz
fS = 44.1 kHz
Figure 23
VCC − Supply Voltage − V
116
117
118
119
120
4.50 4.75 5.00 5.25 5.50
VCC = 5 V
VDD = 3.3 V
TA = 25°C
SNR − dB
SNR
vs
SUPPLY VOLTAGE
fS = 44.1 kHz
fS = 96 kHz
Figure 24
TA − Free-Air Temperature − °C
116
117
118
119
120
−50 −25 0 25 50 75 100
VCC = 5 V
VDD = 3.3 V
SNR − dB
SNR
vs
FREE-AIR TEMPERATURE
fS = 44.1 kHz
fS = 96 kHz
†All specifications at TA = 25°C, VDD = 3.3 V, VCC = 5 V, SCKI = 256 fS (fS = 44.1 kHz), and 24-bit input data (unless otherwise noted)
SLES021 − NOVEMBER 2001
21
www.ti.com
TYPICAL CHARACTERISTICS
analog dynamic performance (continued)
Figure 25
VCC − Supply Voltage − V
110
111
112
113
114
115
116
117
118
4.50 4.75 5.00 5.25 5.50
VDD = 3.3 V
TA = 25°C
Channel Separation − dB
CHANNEL SEPARATION
vs
SUPPLY VOLTAGE
fS = 44.1 kHz
fS = 96 kHz
Figure 26
TA − Free-Air Temperature − °C
110
111
112
113
114
115
116
117
118
−50 −25 0 25 50 75 100
VCC = 5 V
VDD = 3.3 V
Channel Separation − dB
CHANNEL SEPARATION
vs
FREE-AIR TEMPERATURE
fS = 44.1 kHz
fS = 96 kHz
†All specifications at TA = 25°C, VDD = 3.3 V, VCC = 5 V, SCKI = 256 fS (fS = 44.1 kHz), and 24-bit input data (unless otherwise noted)
SLES021 − NOVEMBER 2001
22 www.ti.com
TYPICAL CHARACTERISTICS
Figure 27
f − Frequency − kHz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 5 10 15 20
VCC = 5 V
VDD = 3.3 V
fS = 44.1 kHz
TA = 25°C
BW = 20 kHz
Amplitude − dB
−60-dB OUTPUT SPECTRUM
Figure 28
f − Frequency − kHz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 20406080100
VCC = 5 V
VDD = 3.3 V
fS = 44.1 kHz
TA = 25°C
BW = 100 kHz
Amplitude − dB
−60-dB OUTPUT SPECTRUM
Figure 29
−100 −80 −60 −40 −20 0
Input Level − dBFS
VCC = 5 V
VDD = 3.3 V
TA = 25°C
TOTAL HARMONIC DISTORTION + NOISE
vs
INPUT LEVEL
100
0.1
0.010
0.001
0.0001
fS = 44.1 kHz
fS = 96 kHz
THD+N − Total Harmonic Distortion + Noise − %
1
10
†All specifications at TA = 25°C, VDD = 3.3 V, VCC = 5 V, SCKI = 256 fS (fS = 44.1 kHz), and 24-bit input data (unless otherwise noted)
PACKAGE OPTION ADDENDUM
www.ti.com 27-Aug-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
PCM1730E NRND SSOP DB 28 47 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1730EG4 NRND SSOP DB 28 47 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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