LM118-N, LM218-N, LM318-N
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SNOSBS8C –MARCH 1998–REVISED MARCH 2013
LM118-N/lm218-N/LM318-N Operational Amplifiers
Check for Samples: LM118-N,LM218-N,LM318-N
1FEATURES DESCRIPTION
The LM118 series are precision high speed
2• 15 MHz Small Signal Bandwidth operational amplifiers designed for applications
• Ensured 50V/μs Slew Rate requiring wide bandwidth and high slew rate. They
• Maximum Bias Current of 250 nA feature a factor of ten increase in speed over general
purpose devices without sacrificing DC performance.
• Operates from Supplies of ±5V to ±20V
• Internal Frequency Compensation The LM118 series has internal unity gain frequency
compensation. This considerably simplifies its
• Input and Output Overload Protected application since no external components are
• Pin Compatible with General Purpose Op necessary for operation. However, unlike most
Amps internally compensated amplifiers, external frequency
compensation may be added for optimum
performance. For inverting applications, feedforward
compensation will boost the slew rate to over
150V/μs and almost double the bandwidth.
Overcompensation can be used with the amplifier for
greater stability when maximum bandwidth is not
needed. Further, a single capacitor can be added to
reduce the 0.1% settling time to under 1 μs.
The high speed and fast settling time of these op
amps make them useful in A/D converters, oscillators,
active filters, sample and hold circuits, or general
purpose amplifiers. These devices are easy to apply
and offer an order of magnitude better AC
performance than industry standards such as the
LM709.
The LM218-N is identical to the LM118 except that
the LM218-N has its performance specified over a
−25°C to +85°C temperature range. The LM318-N is
specified from 0°C to +70°C.
Fast Voltage Follower
Do not hard-wire as voltage follower (R1 ≥5 kΩ)
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 1998–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LM118-N, LM218-N, LM318-N
SNOSBS8C –MARCH 1998–REVISED MARCH 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Supply Voltage ±20V
Power Dissipation (3) 500 mW
Differential Input Current (4) ±10 mA
Input Voltage (5) ±15V
Output Short-Circuit Duration Continuous
Operating Temperature Range
lm118-n −55°C to +125°C
LM218-N −25°C to +85°C
LM318-N 0°C to +70°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 10 sec.)
TO-99 Package 300°C
PDIP Package 260°C
Soldering Information
Dual-In-Line Package
Soldering (10 sec.) 260°C
SOIC Package
Vapor Phase (60 sec.) 215°C
Infrared (15 sec.) 220°C
ESD Tolerance (6) 2000V
(1) Refer to RETS118X for LM118H and LM118J military specifications.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(3) The maximum junction temperature of the lm118-n is 150°C, the LM218-N is 110°C, and the LM318-N is 110°C. For operating at
elevated temperatures, devices in the LMC package must be derated based on a thermal resistance of 160°C/W, junction to ambient, or
20°C/W, junction to case. The thermal resistance of the dual-in-line package is 100°C/W, junction to ambient.
(4) The inputs are shunted with back-to-back diodes for overvoltage protection. Therefore, excessive current will flow if a differential input
voltage in excess of 1V is applied between the inputs unless some limiting resistance is used.
(5) For supply voltages less than ±15V, the absolute maximum input voltage is equal to the supply voltage.
(6) Human body model, 1.5 kΩin series with 100 pF.
Electrical Characteristics (1)
Parameter Conditions LM118-N/LM218-N LM318-N Units
Min Typ Max Min Typ Max
Input Offset Voltage TA= 25°C 2 4 4 10 mV
Input Offset Current TA= 25°C 6 50 30 200 nA
Input Bias Current TA= 25°C 120 250 150 500 nA
Input Resistance TA= 25°C 1 3 0.5 3 MΩ
Supply Current TA= 25°C 5 8 5 10 mA
Large Signal Voltage Gain TA= 25°C, VS= ±15V 50 200 25 200 V/mV
VOUT = ±10V, RL≥2 kΩ
Slew Rate TA= 25°C, VS= ±15V, AV= 1 50 70 50 70 V/μs
(2)
Small Signal Bandwidth TA= 25°C, VS= ±15V 15 15 MHz
Input Offset Voltage 6 15 mV
Input Offset Current 100 300 nA
(1) These specifications apply for ±5V ≤VS≤±20V and −55°C ≤TA≤+125°C (lm118-n), −25°C ≤TA≤+85°C (LM218-N), and 0°C ≤TA≤
+70°C (LM318-N). Also, power supplies must be bypassed with 0.1 μF disc capacitors.
(2) Slew rate is tested with VS= ±15V. The lm118-n is in a unity-gain non-inverting configuration. VIN is stepped from −7.5V to +7.5V and
vice versa. The slew rates between −5.0V and +5.0V and vice versa are tested and specified to exceed 50V/μs.
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SNOSBS8C –MARCH 1998–REVISED MARCH 2013
Electrical Characteristics (1) (continued)
Parameter Conditions LM118-N/LM218-N LM318-N Units
Min Typ Max Min Typ Max
Input Bias Current 500 750 nA
Supply Current TA= 125°C 4.5 7 mA
Large Signal Voltage Gain VS= ±15V, VOUT = ±10V 25 20 V/mV
RL≥2 kΩ
Output Voltage Swing VS= ±15V, RL= 2 kΩ±12 ±13 ±12 ±13 V
Input Voltage Range VS= ±15V ±11.5 ±11. V
5
Common-Mode Rejection Ratio 80 100 70 100 dB
Supply Voltage Rejection Ratio 70 80 65 80 dB
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TYPICAL PERFORMANCE CHARACTERISTICS
LM118-N, LM218-N
Input Current Voltage Gain
Figure 1. Figure 2.
Power Supply Rejection Input Noise Voltage
Figure 3. Figure 4.
Common Mode Rejection Supply Current
Figure 5. Figure 6.
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SNOSBS8C –MARCH 1998–REVISED MARCH 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
LM118-N, LM218-N Closed Loop Output
Impedance Current Limiting
Figure 7. Figure 8.
Input Current Unity Gain Bandwidth
Figure 9. Figure 10.
Voltage Follower Slew Rate Inverter Settling Time
Figure 11. Figure 12.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
LM118-N, LM218-N
Large Signal Frequency Response Open Loop Frequency Response
Figure 13. Figure 14.
Voltage Follower Pulse Response Large Signal Frequency Response
Figure 15. Figure 16.
Open Loop Frequency Response Inverter Pulse Response
Figure 17. Figure 18.
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SNOSBS8C –MARCH 1998–REVISED MARCH 2013
Typical Performance Characteristics
LM318-N
Input Current Voltage Gain
Figure 19. Figure 20.
Power Supply Rejection Input Noise Voltage
Figure 21. Figure 22.
Common Mode Rejection Supply Current
Figure 23. Figure 24.
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Typical Performance Characteristics (continued)
LM318-N Closed Loop Output Impedance Current Limiting
Figure 25. Figure 26.
Input Current Unity Gain Bandwidth
Figure 27. Figure 28.
Voltage Follower Slew Rate Inverter Settling Time
Figure 29. Figure 30.
8Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated
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SNOSBS8C –MARCH 1998–REVISED MARCH 2013
Typical Performance Characteristics (continued)
LM318-N Large Signal Frequency Response Open Loop Frequency Response
Figure 31. Figure 32.
Voltage Follower Pulse Response Large Signal Frequency Response
Figure 33. Figure 34.
Open Loop Frequency Response Inverter Pulse Response
Figure 35. Figure 36.
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SNOSBS8C –MARCH 1998–REVISED MARCH 2013
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AUXILIARY CIRCUITS
Figure 39. Offset Balancing
*Balance circuit necessary for increased
slew.
Slew rate typically 150V/μs.
Figure 37. Feedforward Compensation
for Greater Inverting Slew Rate
Figure 40. Isolating Large Capacitive Loads
Figure 41. Overcompensation
Slew and settling time to 0.1% for a 10V
step change is 800 ns.
Figure 38. Compensation for Minimum Settling
Time
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SNOSBS8C –MARCH 1998–REVISED MARCH 2013
TYPICAL APPLICATIONS
Do not hard-wire as voltage follower (R1 ≥5 kΩ)
Figure 42. Fast Voltage Follower
CF= Large
(CF≥50 pF)
*Do not hard-wire as integrator or slow inverter; insert a 10k-5 pF network in series with the input, to prevent
oscillation.
Do not hard-wire as voltage follower (R1 ≥5 kΩ)
Figure 43.
Figure 45. Differential Amplifie
Figure 44. Fast Summing Amplifier
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SNOSBS8C –MARCH 1998–REVISED MARCH 2013
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Figure 46. Fast Sample and Hold
*Optional—Reduces settling time.
Figure 47. D/A Converter Using Ladder Network
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SNOSBS8C –MARCH 1998–REVISED MARCH 2013
ΔOutput zero.
*“Y” zero
+“X” zero
‡Full scale adjust.
Figure 48. Four Quadrant Multiplier
*Optional—Reduces settling time.
Figure 49. D/A Converter Using Binary Weighted Network
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SNOSBS8C –MARCH 1998–REVISED MARCH 2013
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Figure 50. Fast Summing Amplifier with Low Input Current
Figure 51. Wein Bridge Sine Wave Oscillator
Figure 52. Instrumentation Amplifier
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SNOSBS8C –MARCH 1998–REVISED MARCH 2013
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Pin Diagram
Available per JM38510/10107.
Available per JM38510/10107.
Dual-In-Line Package
(Top View) Dual-In-Line Package
See Package Number J (R-GDIP-T14) (Top View)
See Package Number NAB008A, D (R-PDSO-G8),
or P (R-PDIP-T8)
Pin connections shown on schematic diagram and typical applications are for TO-99 package.
TO-99 Package
(Top View)
See Package Number LMC (O-MBCY-W8)
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SNOSBS8C –MARCH 1998–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision B (March 2013) to Revision C Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 16
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PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM118H ACTIVE TO-99 LMC 8 500 Non-RoHS &
Non-Green Call TI Call TI -55 to 125 ( LM118H, LM118H)
LM118H/NOPB ACTIVE TO-99 LMC 8 500 RoHS & Green POST-PLATE Level-1-NA-UNLIM -55 to 125 ( LM118H, LM118H)
LM318M NRND SOIC D 8 95 Non-RoHS &
Non-Green Call TI Call TI 0 to 70 LM
318M
LM318M/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM 0 to 70 LM
318M
LM318MX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM 0 to 70 LM
318M
LM318N/NOPB ACTIVE PDIP P 8 40 RoHS & Green SN Level-1-NA-UNLIM 0 to 70 LM
318N
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM318MX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM318MX/NOPB SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 2
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PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
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EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
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EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
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