128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM
- 3 - Rev 0.2
Aug 2001
K7B401825B
K7B403225B Preliminary
BW
GW
FAST ACCESS TIMES
PARAMETER Symbol -65 -75 -80 Unit
Cycle Time tCYC 7.5 8.5 10 ns
Clock Access Time tCD 6.5 7.5 8.0 ns
Output Enable Access Time tOE 3.5 3.5 4.0 ns
128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Burst SRAM
The K7B403625B, K7B403225B and K7B401825B are
4,718,592 bits Synchronous Static Random Access Memory
designed to support zero wait state performance for advanced
Pentium/Power PC based system. And with CS1 high, ADSP is
blocked to control signals.
It can be organized as 128K(256K) words of 36(18) bits. And it
integrates address and control registers, a 2-bit burst address
counter and high output drive circuitry onto a single integrated
circuit for reduced components counts implementation of high
performance cache RAM applications.
Write cycles are internally self-timed and synchronous.
The self-timed write feature eliminates complex off chip write
pulse shaping logic, simplifying the cache design and further
reducing the component count.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system′s burst sequence and are controlled by the burst
address advance(ADV) input.
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
The K7B403625B, K7B403225B and K7B401825B are imple-
mented with SAMSUNG′s high performance CMOS technology
and is available in a 100pin TQFP package. Multiple power and
ground pins are utilized to minimize ground bounce.
GENERAL DESCRIPTIONFEATURES
LOGIC BLOCK DIAGRAM
• Synchronous Operation.
• On-Chip Address Counter.
• Write Self-Timed Cycle.
• On-Chip Address and Control Registers.
• VDD= 3.3V+0.3V/-0.165V Power Supply.
• VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• 5V Tolerant Inputs except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• LBO Pin allows a choice of either a interleaved burst or a lin-
ear burst.
• Three Chip Enables for simple depth expansion with No Data
Contention.
• TTL-Level Three-State Output.
• 100-TQFP-1420A
• Operating in commeical and industrial temperature range.
CLK
LBO
ADV
ADSC
ADSP
CS1
CS2
CS2
OE
ZZ
BURST CONTROL
LOGIC BURST 128Kx36/32 , 256Kx18
ADDRESS
CONTROL OUTPUT
DATA-IN
ADDRESS
COUNTER
MEMORY
ARRAY
REGISTER
REGISTER
BUFFER
LOGIC
CONTROL
REGISTER
CONTROL
REGISTER
A′0~A′1
A0~A1
or A2~A17
A0~A16
or A0~A17
A2~A16
DQa0 ~ DQd7
DQPa ~ DQPd or DQa0 ~ DQb7
DQPa ~ DQPb
36/32 or 18
WEx
(x=a,b,c,d or a,b)