International Rectifier HEXFET Power MOSFET Dynamic dv/dt Rating Repetitive Avalanche Rated Surface Mount (IRFR320) Straight Lead Description Third Generation HEXFETs from International Rectifier provide the designer with the best combination of fast switching, ruggedized device design, low Available in Tape & Reel Fast Switching Ease of Paralleling IRFR320 IRFU320 (IRFU320) Voss = A00V Rps(on) = 1.80 on-resistance and cost-effectiveness. The D-Pak is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRFU series) is for through-hole mounting applications. Power dissipation levels up to 1.5 watts are possible in typi cal surface mount applications. D-PAK I-PAK TO-252AA TO-251AA Absolute Maximum Ratings i Parameter a Max. _ Units Ip @ To = 25C Continuous Drain Current, Vas @ 10 V 3.4 - ip @ Te = 100C | Continuous Drain Current, Vas @ 10 V 2.0 / | A | lom | Pulsed Drain Current fo 18 | |Pp @ To = 25C _| Power Dissipation 42 tw! Po @ Ta= 25C | Power Dissipation (PCB Mount)** Po 2.5 ____.___| Linear Derating Factor 0.33 wre Linear Derating Factor (PCB Mount)** 0.020 Ves __|Gate-to-Source Voltage _ #20 v Eas Single Pulse Avalanche Energy @ 160 mJ _lar _____ [Avalanche Current _ 3.1 A Ear Repetitive Avalanche Energy 4200 mJ dv/dt Peak Diode Recovery dv/dt @ | 4.0 : Vins Ta, Tste Junction and Storage Temperature Range 5104150, ss] Cc ___| Soldering Temperature, for 10 seconds 260 (1.6mm from case) Thermal Resistance ______ ___ Parameter Min. Typ. _ | Max. Units | Rec Junction-to-Case = | 3.0 Rosa Junction-to-Ambient (PCB mount)** = | 50 C Raia | Junction-to-Ambient _ 110 ** When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to application note #AN-994. 1175IRFR320, IRFU320 Electrical Characteristics @ Tj = 25C (unless otherwise specified) Parameter Min. | Typ. | Max. | Units Test Conditions Vieryoss Drain-to-Source Breakdown Voltage 400 _ _ VV | Vas=0V, Ip= 250A AVarypss/ATy| Breakdown Voltage Temp. Coefficient [051 | | VC | Reference to 25C, lb= 1mA Rosjon) Static Drain-to-Source On-Resistance _ _ 1.8 Q | Vas=10V, Iln=1.9A Vasih) Gate Threshold Voltage 2.0 _ 40 V_ | Vps=Ves, Ip= 250A Ofs Forward Transconductance 1.7 = = S| Vps=50V, Ip=1.9A @ lpss Drain-to-Source Leakage Current 25 HA Vos=400V, Ves=0V _ _ 250 Vps=320V, Ves=0V, Ty=125C loss Gate-to-Source Forward Leakage _ _ 100 nA Ves=20V Gate-to-Source Reverse Leakage _ | -100 Ves=-20V Qg Total Gate Charge = _ 20 Ip=3.3A Qgs Gate-to-Source Charge | | 33} nC | Vpg=320Vv Qod Gate-to-Drain ("Miller") Charge _ in} | Vas=10V See Fig. 6 and 13 tavon) Turn-On Delay Time oa 10 _- Vpp=200V tr Rise Time _ 14 = ns Ip=3.3A tavoft) Turn-Off Delay Time 30 _ Ro=182 tr Fall Time _ 13 _ Rp=56Q. See Figure 10 @ Lo Internal Drain Inductance _ 45 _ ee pad ) 7 j nH | from package [= Ls Internal Source Inductance |75) and center of =) die contact s Ciss Input Capacitance _ 350 _ Vas=0V Coss Output Capacitance | 120! pF | Vps=25V Ciss Reverse Transfer Capacitance _ 47 _ f=1.0MHz See Figure 5 Source-Drain Ratings and Characteristics Parameter Min. | Typ. | Max. | Units Test Conditions ls Continuous Source Current _ _ 34 MOSFET symbol D (Body Diode) , A showing the Ism Pulsed Source Current _ _ 42 integral reverse a : (Body Diode) p-n junction diode. 8 Vsp Diode Forward Voltage _ _ 1.6 V_ | Tu=25C, Is=3.1A, Vas=0V ter Reverse Recovery Time | 270 | 600 | ns | Ty=25C, Ir=3.3A On Reverse Recovery Charge _ 1.4 | 3.0 | pC |di/dt=100A/us @ ton Forward Turn-On Time Intrinsic turn-on time is neglegible (turn-on is dominated by Ls+Lp) Notes: @ Repetitive rating; pulse width limited by Isp<3.1A, di/dts65A/us, VopsV(eR)Dss, max. junction temperature (See Figure 11) Tys150C Vop=50V, starting Ty=25C, L=29mH @ Pulse width < 300 us; duty cycle <2%, Ra=259, las=3.1A (See Figure 12) 1176Ip, Drain Current (Amps) Ip, Drain Current (Amps) 104 10 1074 20us WIDTH Te = 25C 4072 to-t Vps, Drain-to-Source Voltage (volts) Fig 1. Typicai Output Characteristics, To=25C 10! 100 Vpg = 50V 20us PULSE WIDTH Vas, Gate-to-Source Voltage (volts) Fig 3. Typical Transfer Characteristics Rosvon), Drain-to-Source On Resistance Ip, Drain Current (Amps) (Normalized) IRFR320, IRFU320 100 107! 20us PULSE WIDTH Te = 150C sot Vps, Drain-to-Source Voltage (volts) Fig 2. Typical Output Characteristics, Tco=150C 6.0 Ves = 10V ~60 -40 -20 0 20 40 60 80 100 120 140 160 Ty, Junction Temperature (C) Fig 4. Normalized On-Resistance Vs. Temperature 1177IRFR320, IRFU320 1000 20 6s = Ov. = iss = Cgg + Cgg, Cgg SHORTED aS Cyq Oo B00 Cas + = 16 o oO _ S 5 8 ~~" 600 > 12 g 5 5 400 8 a oO s * oO B 200 o 4 WY 6 > 0 0 SEE FIGURE 16 10 1 Vps, Drain-to-Source Voltage (volts) Qe, Total Gate Charge (nC) Fig 5. Typical Capacitance Vs. Fig 6. Typical Gate Charge Vs. Drain-to-Source Voltage Gate-to-Source Voltage 10? ~ 104 OPERATION IN THIS AREA LIMITED g 5 BY Ros (ON) E < ae e E g < ~ w oO 5 5 Sg = wo 3 & 100 6 ; Cc a gs o a > . a Oo 5 2 SL A 2 2 IT j=1500C 4 Ves = OV INGLE PULSE 10 0.4 . . . 1.2 . 1 2 5 10 2 5 102 2 5 403 Vsp, Source-to-Drain Voltage (volts) Vps, Drain-to-Source Voitage (volts) Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area Forward Voltage 1178Ip, Drain Current (Amps) 25 Fig 9. Vos D.U.T. > 2Voo VP10Vv Pulse Width < 1s Duty Factor < 0.1% t Fig 10a. Switching Time Test Circuit mA | | | | | | \ | \ 10% { t 50 75 400 125 150 Ves _/ ! Tc, Case Temperature (C) tdfon) tr taoty tt Maximum Drain Current Vs. Fig 10b. Switching Time Waveforms Case Temperature 40 be Thermal Response (Zajc) oO SINGLE PULSE Poh (THERMAL RESPONSE} jee tall NOTES: 1. DUTY FACTOR, D=t41/t2 2. PEAK Tj=Ppm x Zthjc + To 410 105 104 103 10 0.4 1 10 ty, Rectangular Pulse Duration (seconds) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case 1179IRFR320, IRFU320 Vary tp to obtain Vos > required Jas Ip TOP 4.4A 2.0A BOTTOM 3,4A Eas, Single Pulse Energy (mJ) pp = 50V Vps-5 / 25 75 100 125 150 50 Starting Ty, Junction Temperature(C) as Ta Fig 12c. Maximum Avalanche Energy Fig 12b. Unclamped Inductive Waveforms Vs. Drain Current Current Regulator Q wv a a SSE ES | oes Qen a Va ama] iq * Ip Charge > Current Sampling Resistors Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit Appendix A: Figure 14, Peak Diode Recovery dv/dt Test Circuit - See page 1505 Appendix B: Package Outline Mechanical Drawing - See pages 1512, 1513 Appendix C: Part Marking Information See page 1518 . Appendix D: Tape & Reel Information See page 1523 International 1180