Philips Semiconductors Product specification
TrenchMOS transistor BUK95180-100A
Logic level FET BUK96180-100A
GENERAL DESCRIPTION QUICK REFERENCE DATA
N-channel enhancement mode logic SYMBOL PARAMETER MAX. UNIT
level field-effect power transistor in a
plastic envelope available in VDS Drain-source voltage 100 V
TO220AB and SOT404 . Using IDDrain current (DC) 11 A
’trench’ technology which features Ptot Total power dissipation 54 W
very low on-state resistance. It is TjJunction temperature 175 ˚C
intended for use in automotive and RDS(ON) Drain-source on-state
general purpose switching resistance VGS = 5 V 180 mΩ
applications. VGS = 10 V 173 mΩ
PINNING
TO220AB & SOT404 PIN CONFIGURATION SYMBOL
PIN DESCRIPTION
1 gate
2 drain
3 source
tab/mb drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDS Drain-source voltage - - 100 V
VDGR Drain-gate voltage RGS = 20 kΩ- 100 V
±VGS Gate-source voltage - - 15 V
IDDrain current (DC) Tmb = 25 ˚C - 11 A
IDDrain current (DC) Tmb = 100 ˚C - 7.7 A
IDM Drain current (pulse peak value) Tmb = 25 ˚C - 44 A
Ptot Total power dissipation Tmb = 25 ˚C - 54 W
Tstg, TjStorage & operating temperature - - 55 175 ˚C
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
Rth j-mb Thermal resistance junction to - - 2.8 K/W
mounting base
Rth j-a Thermal resistance junction to in free air 60 - K/W
ambient(TO220AB)
Rth j-a Thermal resistance junction to Minimum footprint, FR4 50 - K/W
ambient(SOT404) board
123
tab
13
mb
2
SOT404 TO220AB
BUK96180-100A BUK95180-100A
d
g
s
May 2000 1 Rev 1.100
Philips Semiconductors Product specification
TrenchMOS transistor BUK95180-100A
Logic level FET BUK96180-100A
STATIC CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V(BR)DSS Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 100 - - V
voltage Tj = -55˚C 89 - - V
VGS(TO) Gate threshold voltage VDS = VGS; ID = 1 mA 1 1.5 2.0 V
Tj = 175˚C 0.5 - - V
Tj = -55˚C - - 2.3 V
IDSS Zero gate voltage drain current VDS = 100 V; VGS = 0 V; - 0.05 10 µA
Tj = 175˚C - - 500 µA
IGSS Gate source leakage current VGS = ±10 V; VDS = 0 V - 2 100 nA
RDS(ON) Drain-source on-state VGS = 5 V; ID = 5 A - 165 180 mΩ
resistance Tj = 175˚C - - 450 mΩ
VGS = 10 V; ID = 5 A - 152 173 mΩ
VGS = 4.5 V; ID = 5 A - 170 200 mΩ
DYNAMIC CHARACTERISTICS
Tmb = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Ciss Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 464 619 pF
Coss Output capacitance - 60 72 pF
Crss Feedback capacitance - 37 50 pF
td on Turn-on delay time VDD = 30 V; Rload =1.2Ω;-920ns
trTurn-on rise time VGS = 5 V; RG = 10 Ω- 112 157 ns
td off Turn-off delay time - 18 27 ns
tfTurn-off fall time - 25 38 ns
LdInternal drain inductance Measured from drain lead 6 mm - 4.5 - nH
from package to centre of die
LdInternal drain inductance Measured from contact screw on - 3.5 - nH
tab to centre of die(TO220AB)
LdInternal drain inductance Measured from upper edge of drain - 2.5 - nH
tab to centre of die(SOT404)
LsInternal source inductance Measured from source lead to - 7.5 - nH
source bond pad
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
IDR Continuous reverse drain - - 11 A
current
IDRM Pulsed reverse drain current - - 44 A
VSD Diode forward voltage IF = 5 A; VGS = 0 V - 0.85 1.2 V
IF = 11 A; VGS = 0 V - 1.1 - V
trr Reverse recovery time IF = 11 A; -dIF/dt = 100 A/µs; - 49 - ns
Qrr Reverse recovery charge VGS = -10 V; VR = 30 V - 0.13 - µC
May 2000 2 Rev 1.100
Philips Semiconductors Product specification
TrenchMOS transistor BUK95180-100A
Logic level FET BUK96180-100A
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
WDSS1Drain-source non-repetitive ID = 5.5 A; VDD ≤ 25 V; - - 1.5 mJ
unclamped inductive turn-off VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C
energy
!
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Tmb)
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
0 20 40 60 80 100 120 140 160 180
Tmb / C
PD% Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
1 10 100 1000
0.1
1
10
100
VSD/V
ID/A
DC
RDS(ON)=VSD/ID
0 20 40 60 80 100 120 140 160 180
Tmb / C
ID% Normalised Current Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
0.001
0.01
0.1
1
10
1E-07 1E-05 1E-03 1E-01 1E+01
t/s
Zth/(K/W)
0
0.02
0.05
0.1
0.2
0.5
1 For maximum permissible repetive avalanche current see fig.18.
May 2000 3 Rev 1.100
Philips Semiconductors Product specification
TrenchMOS transistor BUK95180-100A
Logic level FET BUK96180-100A
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
Fig.7. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(VGS); conditions: ID = 25 A;
Fig.8. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
Fig.9. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
Fig.10. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 25 A; VGS = 5 V
0
5
10
15
20
25
0246810
VDS/V
ID/A
2.8
3.0
3.6
3.8
4.0
5.0
10.0
VGS/V =
2.2
2.6
3.4
3.2
2.4
0
2
4
6
8
10
12
02468
VGS/V
ID/A
Tj/C= 175 25
100
120
140
160
180
200
220
240
24681012
ID/A
3.2
3.6
3.8
4.0
3.4
5.0
3.0
RDS(ON)/mOhm
0
2
4
6
8
10
12
14
16
02468101214
ID/A
gfs/S
0.5
1
1.5
2
2.5
3
-100 -50 0 50 100 150 200
Tmb / degC
aRds(on) normalised to 25degC
150
160
170
180
190
200
210
220
230
240
345678910
VGS/V
RDS(ON) Ohm
May 2000 4 Rev 1.100
Philips Semiconductors Product specification
TrenchMOS transistor BUK95180-100A
Logic level FET BUK96180-100A
Fig.11. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Fig.12. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Fig.13. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
Fig.14. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 25 A; parameter VDS
Fig.15. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
Fig.16. Normalised avalanche energy rating.
WDSS% = f(Tmb); conditions: ID = 75 A
-100 -50 0 50 100 150 200
0
0.5
1
1.5
2
2.5
Tj / C
VGS(TO) / V
max.
typ.
min.
0
1
2
3
4
5
0246810
QG / nC
VGS / V
0
5
10
15
0.0 0.2 0.4 0.6 0.8 1.0 1.2
VSDS/V
IF/A
25Tj/C= 150
0 0.5 1 1.5 2 2.5 3
1E-05
1E-05
1E-04
1E-03
1E-02
1E-01 Sub-Threshold Conduction
2% typ 98%
20 40 60 80 100 120 140 160 180
Tmb / C
120
110
100
90
80
70
60
50
40
30
20
10
0
WDSS%
0
200
400
600
800
1000
1200
0.01 0.1 1 10 100
VDS/V
Ciss
Coss
Crss
Capacitance / pF
May 2000 5 Rev 1.100
Philips Semiconductors Product specification
TrenchMOS transistor BUK95180-100A
Logic level FET BUK96180-100A
Fig.17. Avalanche energy test circuit.
Fig.18. Maximum permissible repetitive avalanche
current(IAV) versus avalanche time(tAV) for unclamped
inductive loads.
Fig.19. Switching test circuit.
L
T.U.T.
VDD
RGS R 01
VDS
-ID/100
+
-
shunt
VGS
0
RD
T.U.T.
VDD
RG
VDS
+
-
VGS
0
WDSS =0.5 ⋅LID
2⋅BVDSS/(BVDSS −VDD)
1
10
100
0.001 0.01 0.1 1 10
Avalanche Time, tAV (ms)
IAV Tj prior to avalanche 150oC
25oC
May 2000 6 Rev 1.100
Philips Semiconductors Product specification
TrenchMOS transistor BUK95180-100A
Logic level FET BUK96180-100A
MECHANICAL DATA
Dimensions in mm
Net Mass: 2 g
Fig.20. SOT78 (TO220AB); pin 2 connected to mounting base.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for SOT78 (TO220) envelopes.
3. Epoxy meets UL94 V0 at 1/8".
10,3
max
3,7
2,8
3,0
3,0 max
not tinned
1,3
max
(2x) 123
2,4
0,6
4,5
max
5,9
min
15,8
max
1,3
2,54 2,54
0,9 max (3x)
13,5
min
May 2000 7 Rev 1.100
Philips Semiconductors Product specification
TrenchMOS transistor BUK95180-100A
Logic level FET BUK96180-100A
MECHANICAL DATA
Fig.21. SOT404 surface mounting package. Centre pin connected to mounting base.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.
3. Epoxy meets UL94 V0 at 1/8".
UNIT A
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
mm
A1D1
D
max. EeL
pHDQc
2.54 2.60
2.20
15.40
14.80
2.90
2.10
11 1.60
1.20 10.30
9.70
4.50
4.10 1.40
1.27 0.85
0.60 0.64
0.46
b
DIMENSIONS (mm are the original dimensions)
SOT404
0 2.5 5 mm
scale
Plastic single-ended surface mounted package (Philips version of D
2
-PAK); 3 leads
(one lead cropped) SOT404
e e
E
b
D1
HD
D
Q
Lp
c
A1
A
13
2
mounting
base
98-12-14
99-06-25
May 2000 8 Rev 1.100
Philips Semiconductors Product specification
TrenchMOS transistor BUK95180-100A
Logic level FET BUK96180-100A
MOUNTING INSTRUCTIONS
Dimensions in mm
Fig.22. SOT404 : soldering pattern for surface mounting.
DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
17.5
11.5
9.0
5.08
3.8
2.0
May 2000 9 Rev 1.100
