MT48LC8M16A2B4-6AIT:G - Micron Technology, Inc.

Products and specifications discussed herein are subject to change by Micron without notice.

128Mb: x4, x8, x16 SDRAM

Features

PDF: 09005aef8091e66d/Source: 09005aef8091e625 Micron Technology, Inc., reserves the right to change products or specifications without notice.

SDRAM

MT48LC32M4A2 – 8 Meg x 4 x 4 banks

MT48LC16M8A2 – 4 Meg x 8 x 4 banks

MT48LC8M16A2 – 2 Meg x 16 x 4 banks

For the latest data sheet, refer to Micron’s Web site: www.micron.com

Features

• PC100- and PC133-compliant

• Fully synchronous; all signals registered on positive edge

of system clock

• Internal pipelined operation; column address can be

changed every clock cycle

• Internal banks for hiding row access/precharge

• Programmable burst length s (BL): 1, 2, 4, 8, or full page

• Auto precharge, includes concurrent auto precharge, and

auto refresh modes

• Self refresh mode; standard and low power

• 64ms, 4,096-cycle refresh (commercial & industrial)

• 16ms, 4,096-cycle refresh (Automotive)

• LVTTL-compatible inputs and outputs

• Single +3.3 ±0.3V power supply

Options Designator

• Configurations

• Write recovery (tWR)

• Package/Pinout

• Timing (cycle time)

• Self refresh

•Design revision

• Operating temperature r ange None

IT3

AT3

Notes: 1. Refer to Micron technical note: TN-48-05.

2. Off-center parting line.

3. Consult Micron for availability.

4. x16 only.

– 32 Meg x 4 (8 Meg x 4 x 4 banks) 32M4

– 16 Meg x 8 (4 Meg x 8 x 4 banks) 16M8

– 8 Me g x 16 (2 Meg x 16 x 4 banks) 8M16

– tWR = “2 CLK”1 A2

–Plastic package – OCPL2

–54-pin TSOP II (400 mil) TG

–54-pin TSOP II (400 mil) Pb-free P

–60-ball FBGA (8mm x 16mm) FB3

–60-ball FBGA (8mm x 16mm) Pb-free BB3

–54-ball VFBGA (8mm x 8mm) F44

–54-ball VFBGA (8mm x 8mm) Pb-free B44

–7.5ns @ CL = 3 (PC133) -75

–7.5ns @ CL = 2 (PC133) -7E

–6.0ns @ CL = 3 (x16 only) -6A

–Standard None

–Low power L

–Commercial (0°C to +70°C)

–Industrial (–40°C to +85°C)

–Automotive (–40°C to +105°C)

Figure 1: 54-Pin TSOP Pin Assignment

(Top View)

Notes: 1. The # symbol indicates signal is active LOW. A dash (-) indicates

x8 and x4 pin function is same as x16 pin function.

Table 1: Address Table

32 Meg x 4 16 Meg x 8 8 Meg x 16

Configuration 8 Meg x 4 x 4

banks 4 Meg x 8 x 4

banks 2 Meg x 16 x 4

banks

Refresh count 4K 4K 4K

Row addressing 4K (A0–A11) 4K (A0–A11) 4K (A0–A11)

Bank addressing 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)

Column addressing 2K (A0–A9,

A11) 1K (A0–A9) 512 (A0–A8)

Table 2: Key Timing Parameters

CL = CAS (Read) latency

Speed

Grade Clock

Frequency

Access Time Setup

Time Hold

Time

CL = 2 CL = 3

-6A 167 MHz – 5.4ns 1.5ns 0.8ns

-7E 143 MHz – 5.4ns 1.5ns 0.8ns

-7E 133 MHz 5.4ns – 1.5ns 0.8ns

-75 133 MHz – 5.4ns 1.5ns 0.8ns

-75 100 MHz 6ns – 1.5ns 0.8ns

DQ0

DQ1

DQ2

VssQ

DQ3

DQ4

DQ5

DQ6

VssQ

DQ7

DQML

WE#

CAS#

RAS#

CS#

BA0

BA1

A10

Vss

DQ15

VssQ

DQ14

DQ13

DQ12

DQ11

VssQ

DQ10

DQ9

DQ8

Vss

DQMH

CLK

CKE

A11

Vss

x8x16 x16x8 x4x4

DQ0

DQ1

DQ2

DQ3

DQ0

DQ1

DQ7

DQ6

DQ5

DQ4

DQM

DQ3

DQ2

DQM

PDF: 09005aef8091e66d/Source: 09005aef8091e625 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

128Mb: x4, x8, x16 SDRAM

General Description

Notes: 1. FBGA Device Decode: http://www.micron.com/support/FBGA/FBGA.asp

General Description

The Micron® 128Mb SDRAM is a high-speed CMOS, dynamic random access memory

containing 134,217,728 bits. It is internally configured as a quad-bank DRAM with a

synchronous inte rface (all signals are registered on the positive edge of the clock signal,

CLK). Each of the x4’s 33,554,432-bit banks is organized as 4,096 rows by 2,048 columns

b y 4 bits . Each of the x8’s 33,554,432-bit banks is organized as 4,096 rows by 1,024

columns by 8 bits. Each of the x16’s 33,554,432-bit banks is organized as 4,096 rows by

512 columns by 16 bits .

Read and write accesses to the SDRAM are burst oriented; accesses start at a selected

location and continue for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an ACTIVE command, which is then

followed by a READ or WRITE command. The address bits registered coincident with the

ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select

the bank; A0–A11 select the row). The address bits registered coincident with the READ

or WRITE command are used to select the starting column location for the burst access.

The SDRAM provides for programmable read or write burst lengths of 1, 2, 4, or 8 loca-

tions, or the full page , with a burst terminate option. An auto precharge function may be

enabled to provide a self-timed row precharge that is initiated at the end of the burst

sequence.

The 128Mb SDRAM uses an internal pipelined ar chi tectur e to achieve high-spe ed opera -

tion. This architecture is compatible with the 2n rule of prefetch architectures, but it also

allows the column address to be changed on every clock cycle to achieve a high-speed,

fully random access. Precharging one bank while accessing one of the other three banks

will hide the precharge cycles and provide seamless high-speed, random-access opera-

tion.

The 128Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh

mode is provided along with a power-saving, power-down mode. All inputs and outputs

are LVTTL-compatible.

SDRAMs offer substantial advances in DRAM operating perfor mance, including the

ability to synchronously burst data at a high data rate with automatic column-address

generation, the ability to interleave be tween internal banks to hide pre charge time, and

the capability to randomly change column addresses on each clock cycl e during a burst

access.

Table 3: 128Mb SDRAM Part Numbers

Part Number Architecture

MT48LC32M4A2TG 32 Meg x 4

MT48LC32M4A2P 32 Meg x 4

MT48LC16M8A2TG 16 Meg x 8

MT48LC16M8A2P 16 Meg x 8

MT48LC16M8A2FB116 Meg x 8

MT48LC16M8A2BB116 Meg x 8

MT48LC8M16A2TG 8 Meg x 16

MT48LC8M16A2P 8 Meg x 16

MT48LC8M16A2B418 Meg x 16

MT48LC8M16A2F418 Meg x 16

PDF: 09005aef8091e66d/Source: 09005aef8091e625 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

128Mb: x4, x8, x16 SDRAM

Automotive Temperature

The automotive temperature (AT) option adheres to the following specifications:

• 16ms refresh rate

• Self refresh not supported

• Ambient and case temperature cannot be less than –40°C or greater than +105°C

PDF: 09005aef8091e66d/Source: 09005aef8091e625 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

128Mb: x4, x8, x16 SDRAM

Table of Contents

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Automotive Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

FBGA Ball Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Functional Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Pin/Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Mode Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Burst Length (BL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Burst Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Operating Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Write Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

COMMAND INHIBIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

LOAD MODE REGISTER (LMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Bank/row Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

WRITEs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Clock Suspend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

BURST READ/SINGLE WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

READ with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

WRITE with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Temperature and Thermal Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

PDF: 09005aef8091e66d/Source: 09005aef8091e625 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

128Mb: x4, x8, x16 SDRAM

List of Figur es

List of Figures

Figure 1: 54-Pin TSOP Pin Assignment (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Figure 2: 60-Ball FBGA Ball Assignments (Top View), 16 Meg x 8, 8mm x 16mm . . . . . . . . . . . . . . . . . . . . . . . . . .8

Figure 3: 54-Ball VFBGA Assignments (Top View), 8 Meg x 16, 8mm x 8mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 4: 32 Meg x 4 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 5: 16 Meg x 8 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Figure 6: 8 Meg x 16 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 7: Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Figure 8: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 9: Activating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 10: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK ≤ 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 11: READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 12: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 13: Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 14: Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 15: READ-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 16: READ-to-WRITE with Extra Clock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 17: READ-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 18: Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 19: WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 20: WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 21: WRITE-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 22: Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 23: WRITE-to-READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Figure 24: WRITE-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Figure 25: Terminating a WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Figure 26: PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 27: Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 28: Clock Suspend During WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 29: Clock Suspend During READ Bu rst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Figure 30: READ With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Figure 31: READ With Auto Precharge Interr upted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Figure 32: WRITE With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Figure 33: WRITE With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Figure 34: Example Tempe rature Test Point Location, 54-Pin TSOP: Top View . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Figure 35: Example Temperature Test Point Location, 54-Ball VFBGA: Top View . . . . . . . . . . . . . . . . . . . . . . . . .48

Figure 36: Example Temperature Test Point Location, 60-Ball FBGA: Top View . . . . . . . . . . . . . . . . . . . . . . . . . .48

Figure 37: Ini tial ize a nd Load Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Figure 38: Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Figure 39: Clock Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Figure 40: Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Figure 41: Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Figure 42: READ – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Figure 43: READ – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Figure 44: Single READ – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Figure 45: Single READ – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Figure 46: Alternating Bank Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Figure 47: READ – Full-Page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Figure 48: READ – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Figure 49: WRITE – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Figure 50: WRITE – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Figure 51: Single WRITE – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Figure 52: Single WRITE – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Figure 53: Alternating Bank Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Figure 54: WRITE – Full-Page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Figure 55: WRITE – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Figure 56: 54-Pin Plastic TSOP (400 mil) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

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128Mb: x4, x8, x16 SDRAM

List of Figur es

Figure 57: 60- Bal l FB GA “F B/ BB ” Package (x8 device), 8mm x 16mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Figure 58: 54-Ball VFBGA “F4/B4” Package (x16 device), 8mm x 8mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

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128Mb: x4, x8, x16 SDRAM

List of Tables

Table 1: Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Table 2: Key Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Table 3: 128Mb SDRAM Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 4: Pin/Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Table 5: Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 6: CAS Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Table 7: Truth Table 1 – Commands and DQM Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 8: Truth Table 2 – CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Table 9: Truth Table 3 – Current State Bank n, Command to Bank n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Table 10: Truth Table 4 – Current State Bank n, Command to Bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 11: Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Table 12: Temperature Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 13: Thermal Impedance Simulated Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 14: DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Table 15: IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Table 16: Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Table 17: Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .50

Table 18: AC Functional Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

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128Mb: x4, x8, x16 SDRAM

FBGA Ball Assignments

Figure 2: 60-Ball FBGA Ball Assignments (Top View), 16 Meg x 8, 8mm x 16mm

12345678

Depopulated Balls

DQ7 Vss

NC VssQ

VDDQDQ6

DQ5 NC

NC VssQ

VDDQDQ4

NC NC

NC Vss

NC DQM

NC CK

NC CKE

A11 A9

A8 A7

A6 A5

A4 Vss

VDD DQ0

VDDQNC

DQ1 VssQ

NC DQ2

VDDQNC

DQ3 VssQ

NC NC

VDD NC

WE# CAS#

RAS# NC

NC CS#

BA1 BA0

A0 A10

A2 A1

VDD A3

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128Mb: x4, x8, x16 SDRAM

FBGA Ball Assignments

Figure 3: 54-Ball VFBGA Assignments (Top View), 8 Meg x 16, 8mm x 8mm

Notes: 1. The balls at A4, A5, and A6 are not in the physical package. They are included in the draw-

ing to illustrate that rows 4, 5, and 6 exist bu t contain no sold er balls.

12345678

Top View

(Ball Down)

VSS

DQ14

DQ12

DQ10

DQ8

DQMH

NC/A12

VSS

DQ15

DQ13

DQ11

DQ9

CLK

A11

VSSQ

VDDQ

VSSQ

VDDQ

VSS

CKE

VDDQ

VSSQ

VDDQ

VSSQ

VDD

CAS#

BA0

DQ0

DQ2

DQ4

DQ6

DQML

RAS#

BA1

VDD

DQ1

DQ3

DQ5

DQ7

WE#

CS#

A10

VDD

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128Mb: x4, x8, x16 SDRAM

Functional Block Diagrams

Figure 4: 32 Meg x 4 SDRAM

DATA

INPUT

DATA

OUTPUT

RAS#

CAS#

ROW-

ADDRESS

MUX

CLK

CS#

WE#

CKE

CONTROL

LOGIC

COLUMN-

ADDRESS

COUNTER/

LATCH

MODE REGISTER

COMMAND

DECODE

A0–A11,

BA0, BA1

DQM

ADDRESS

2,048

(x4)

4,096

I/O GATING

DQM MASK LOGIC

READ DATA LATCH

WRITE DRIVERS

COLUMN

DECODER

BANK0

MEMORY

ARRAY

(4,096 x 2,048 x 4)

BANK0

ROW-

ADDRESS

LATCH

DECODER

4,096

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

DQ0–

DQ3

BANK1BANK2 BANK3

REFRESH

COUNTER

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128Mb: x4, x8, x16 SDRAM

Functional Block Diagrams

Figure 5: 16 Meg x 8 SDRAM

DATA

INPUT

DATA

OUTPUT

RAS#

CAS#

ROW-

ADDRESS

MUX

CLK

CS#

WE#

CKE

CONTROL

LOGIC

COLUMN-

ADDRESS

COUNTER/

LATCH

MODE REGISTER

COMMAND

DECODE

A0–A11,

BA0, BA1

DQM

ADDRESS

1,024

(x8)

4,096

I/O GATING

DQM MASK LOGIC

READ DATA LATCH

WRITE DRIVERS

COLUMN

DECODER

BANK0

MEMORY

ARRAY

(4,096 x 1,024 x 8)

BANK0

ROW-

ADDRESS

LATCH

DECODER

4,096

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

DQ0–

DQ7

BANK1BANK2 BANK3

REFRESH

COUNTER

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128Mb: x4, x8, x16 SDRAM

Functional Block Diagrams

Figure 6: 8 Meg x 16 SDRAM

RAS#

CAS#

ROW-

ADDRESS

MUX

CLK

CS#

WE#

CKE

CONTROL

LOGIC

COLUMN-

ADDRESS

COUNTER/

LATCH

MODE REGISTER

COMMAND

DECODE

A0–A11,

BA0, BA1

DQML,

DQMH

ADDRESS

512

(x16)

4,096

I/O GATING

DQM MASK LOGIC

READ DATA LATCH

WRITE DRIVERS

COLUMN

DECODER

BANK0

MEMORY

ARRAY

(4,096 x 512 x 16)

BANK0

ROW-

ADDRESS

LATCH

DECODER

4,096

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

DQ0–

DQ15

16 DATA

INPUT

DATA

OUTPUT

BANK1BANK2 BANK3

2 2

REFRESH

COUNTER

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128Mb: x4, x8, x16 SDRAM

Pin/Ball Descriptions

Table 4: Pin/Ball Descriptions

54-Pin TSOP 54-Ball

VFBGA 60-Ball

FBGA Symbol Type Description

38 F2 K2 CLK Input Clock: CLK is driven by the system clock. All SDRAM input

signals are sampled on the positive edge of CLK. CLK also

increments the internal burst counter and controls the

output registers.

37 F3 L2 CKE Input Clock enable: CKE activates (HIGH) and deactivates (LOW)

the CLK signal. Deactivating the clock provides

PRECHARGE power- do wn an d SELF REFRESH operation

(all banks idle), ACTIVE power-down (row active in any

bank), or CLOCK SUSPEND operation (burst/access in

progress). CKE is synchronous except after the device

enters power-down and self refresh modes, where CKE

becomes asynchronous until after exiting the same mode.

The input buffers, including CLK, are disabled during

power-down and self refresh modes, providing low

standby power. CKE may be tied HIGH.

19 G9 L8 CS# Input Chip select: CS# enables (registered LOW) and disables

(registered HIGH) the command decoder. All commands

are masked when CS# is registered HIGH, but READ/WRITE

bursts already in progress will continue and DQM

operation will retain its DQ mask capability while CS# is

HIGH. CS# provides for external bank selection on systems

with multiple banks. CS# is considered part of the

command code.

16, 17, 18 F9, F7, F8 J7, J8, K7 WE#,

CAS#,

RAS#

Input Command inputs: WE#, CAS#, and RAS# (along with CS#)

define the command being entered.

39 –J2 x4, x8:

DQM Input Input/Output mask: DQM is an input mask signal for write

accesses and an output enable signal for read accesses.

Input data is masked when DQM is sampled HIGH during

a WRITE cycle. The output buffers are placed in a High-Z

state (2-clock latency) when DQM is sampled HIGH during

a READ cycle. On the x4 and x8, DQML (pin 15) is a NC and

DQMH is DQM. On the x16, DQML corresponds to DQ0–

DQ7, and DQMH corresponds to DQ8–DQ15. DQML and

DQMH are considered same state when referenced as

DQM.

15, 39 E8, F1 –x16:

DQML,

DQMH

20, 21 G7, G8 M8, M7 BA0, BA1 Input Bank address inputs: BA0 and BA1 define to which bank

the ACTIVE, READ, WRITE, or PRECHARGE command is

being applied.

23–26, 29–

34, 22, 35 H7, H8, J8,

J7, J3, J2, H3,

H2, H1, G3,

H9, G2

N7, P8, P7,

R8, R1, P2,

P1, N2, N1,

M2, N8, M1

A0–A11 Input Address inputs: A0–A11 are sampled during the ACTIVE

command (row-address A0–A11) and READ/WRITE

command (column-address A0–A9, A11 [x4]; A0–A9 [x8];

A0–A8 [x16]; with A10 defining auto precharge) to select

one location out of the memory array in the respective

bank. A10 is sampled during a precharge command to

determine whether all banks are to be prec harged (A10

[HIGH]) or bank selected by BA0, BA1 (A10 [LOW]). The

address inputs also provide the op-code during a LOAD

MODE REGISTER (LMR) command.

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128Mb: x4, x8, x16 SDRAM

Pin/Ball Descriptions

2, 4, 5, 7, 8,

10, 11, 13,

42, 44, 45,

47, 48, 50,

51, 53

A8, B9, B8,

C9, C8, D9,

D8, E9, E1,

D2, D1, C2,

C1, B2, B1,

–DQ0–

DQ15 x16: I/O Data input/output: Data bus for x16 (pins 4, 7, 10, 13, 42,

45, 48, and 51 are NCs for x8; and 2, 4, 7, 8, 10, 13, 42, 45,

47, 48, 51, and 53 are NCs for x4).

2, 5, 8, 11,

44, 47, 50,

–A8, C7, D8,

F7, F2, D1,

C2, A1

DQ0–DQ7 x8: I/O Data input/output: Data bus for x8 (pins 2, 8, 47, and 53

are NCs for x4; balls A8, D8, D1, and A1 are NCs for x4).

5, 11, 44, 50 –C7, F7, F2,

C2 DQ0–DQ3 x4: I/O Data input/output: Data bus for x4.

40 E2 B1, B8, D2,

D7, E1, E8,

G1, G2, G7,

G8, H1, H8,

J1, K1, K8,

NC –No connect: Th ese pins should be l eft unconnected.

36 G1 L1 NC –Address input (A12) for the 256Mb and 512Mb devices.

3, 9, 43, 49 A7, B3, C7,

D3 B7, C1, E7,

F1 VDDQSupply DQ power: Isolated DQ power on the die for improved

noise immunity.

6, 12, 46, 52 A3, B7, C3,

D7 B2, C8, E2,

F8 VSSQSupply DQ ground: Isolated DQ ground on the die for improved

noise immunity.

1, 14, 27 A9, E7, J9 A7, R7 VDD Supply Power supply: +3.3 ±0.3V.

28, 41, 54 A1, E3, J1 A2, H2, R2 VSS Supply Ground.

Table 4: Pin/Ball Descriptions (Continued)

54-Pin TSOP 54-Ball

VFBGA 60-Ball

FBGA Symbol Type Description

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128Mb: x4, x8, x16 SDRAM

Functional Description

In general, the 128Mb SDRAMs (8 M eg x 4 x 4 banks, 4 Meg x 8 x 4 banks, and 2 Meg x 16

x 4 banks) are quad-bank DRAMs that operate at 3.3V and include a synchronous inter-

face (all signals are registered on the positive edge of the clock signal, CLK). Each of the

x4’s 33,554,432-bit banks is organized as 4,096 rows by 2,0 48 columns by 4 bits. Each of

the x8’s 33,554,432-bit banks is organized as 4,096 rows by 1,024 columns by 8 bits. Each

of the x16’s 33,554,432-bit bank s is organized as 4,096 rows b y 512 columns by 16 bits.

Read and write accesses to the SDRAM are burst oriented; accesses start at a selected

location and continue for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an ACTIVE command, which is then

followed by a READ or WRITE command. The address bits registered coincident with the

ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1

select the bank, A0–A11 select the row). The address bits (x4: A0–A9, A11; x8: A0–A9; x16:

A0–A8) registered coincident with the READ or WRITE command are used to select the

starting column location for the burst access.

Prior to normal ope ration, the SDR AM must be initialized . The fo ll owing sections

provide detailed information covering device initialization, register definition,

command descriptions, and device operation.

Initialization

SDRAMs must be powered up and initialized in a predefined manner. Operational

procedures other than those specified may r esult in undefined operation. After power is

applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is

defined as a signal cycling within timing constraints specified for the clock pin), the

SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND

INHIBIT or NOP. Starting at some point during this 100µs period and continuing at least

through the end of this pe riod, C O MMAND INHIBIT or NOP commands must be

applied.

After the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP

command having been applied, a PRECHARGE command should be applied. All banks

must then be pr echarged, thereby placing the device in the all banks idle state.

Once in the idle state, at least two AUTO REFRESH cycles must be performed. After the

AUTO REFRESH cycles are complete, the SDRAM is ready for mode register program-

ming. Because the mode register will power up in an unknown state, it must be loaded

prior to applying any operational command. If desired, the two AUTO REFRESH

commands can be issued after the LMR command.

The recommended power-up sequence for SDRAMs:

1. Simultaneously apply power to VDD and VDDQ.

2. Assert and hold CKE at a LVTTL logic LOW since all inputs and outputs are LVTTL-

compatible.

3. Provide stable CLOCK signal. S table clock is defined as a signal cycling within timing

constraints speci fie d for th e c loc k pin.

4. Wait at least 100µs pr ior to is sui n g any command other than a COMMAND INHIBIT

or NOP.

5. Starting at some point during this 100µs period, bring CKE HIGH. Continuing at least

through the end of this period, one or more COMMAND INHIBIT or NOP commands

must be applied.

6. Per for m a PRECHARGE ALL command.

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Functional Description

7. Wa it at least tRP time; during this time, NOPs or DESELECT commands must be

given. All banks will complete their precharge, thereby placing the device in the all

banks idle state.

8. Issue an AUTO REFRESH command.

9. Wa it at least tRFC time, during which only NOPs or COMMAND INHIBIT commands

are allowed.

10. I ssue an AUTO REFRESH command.

11. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands

are allowed.

12. The SDRAM is now ready for mode register programming. Because the mode register

will power up in an unknown state, it should be loaded with desired bit values prior to

applying any operational command. Using the LMR command, program the mode

with BA1 = 0, BA0 = 0 and retains the stored information until it is programmed again

or the device loses power. N ot programming the mode register upon initi alization will

result in default settings, which may not be desired. Outputs are guaranteed High-Z

after the LMR command is issued. Outputs should be High-Z already before the LMR

command is issued.

13. Wait at least tMRD time, during which only NOP or DESELECT commands are

allowed.

At this poi n t, the DRAM is ready for any valid command.

Note: If desired, more than two AUTO REFRESH commands can be issue d in th e se que n c e.

After steps 9 and 10 are complete, repeat them until the desired number of AUTO

REFRESH + tRFC loops is achieved.

Mode Register

The mode register is used to define the specific mode of operation of the SDRAM. This

definition includes the selection of a burst length (BL), a burst type, a CAS latency (CL),

an operating mode, and a write burst mode, as shown in Figure 7 on page 18. The mode

until it is programmed again or the device loses power.

Mode r egister bits M0–M2 specify the BL, M3 specifies the type of burst (sequential or

interleaved), M4–M6 specify the CL, M7 and M8 specify the operating mode, M9 speci-

fies the write burst mode, and M10 and M11 are reserved for future use.

The mode regi ster must be loaded when all banks are idle, and the controller must wait

the specified time before initiating the subsequent operation. Violating either of these

requirements will result in unspecified operation.

Burst Length (BL)

Read and write accesses to the SDRAM are burst oriented, with the BL being program-

mable , as shown in Figure 7 on page 18. BL determines the maximum number of

column locations that can be accessed for a given READ or WRITE command. BL of 1, 2,

4, or 8 locations ar e available for both the sequential and the interleaved burst types, and

a full-page burst is available for the sequential mode. The full-page burst is used in

conjunction with the BURST TERMINATE command to generate arbitrary BLs.

Reserved states cannot be used because unknown operation or incompatibility with

future vers ions may resul t.

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128Mb: x4, x8, x16 SDRAM

Functional Description

When a READ or WRITE comm and is issu ed , a block of col u m n s eq ual to the BL is effe c-

tively selected. All accesses for that burst take place within this block, meaning that the

burst will wrap within the block if a boundary is reached. The block is uniquely sel ected

b y A1–A9, A11 (x4), A1–A9 (x8), or A1–A8 (x16) when BL = 2; by A2–A9, A11 (x4), A2–A9

(x8), or A2–A8 (x16) when BL = 4; and by A3–A9, A11 (x4), A3–A9 (x8), or A3–A8 (x16)

when BL = 8. The remaining (least significant) address bit(s) is (a re) used to select the

starting location within the block. Full-page bursts wrap within the page if the boundary

is reached.

Burst Type

Accesses wi thin a given burst may be programmed either to be sequential or interleaved;

this is referred to as the burst type and is selected via bit M3.

The ordering of accesses within a burst is determined by the BL, the burst type, and the

starting column address, as shown in Table 5 on page 19.

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Functional Description

Figure 7: Mode Register Definition

A3 = 0

Reserved

Full Page

A3 = 1

Reserved

Operating Mode

Standard Operation

All other states reserved

–

Defined

–

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Burst Length

Burst LengthCAS Latency BT

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Mode Register (Ax)

Address Bus

976543

8210

A6–A0

A8 A7

Op Mode

A10

A11

Reserved WB

Write Burst Mode

Programmed Burst Length

Single Location Access

Program

A11, A10 = “0, 0”

to ensure compatibility

with future devices.

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128Mb: x4, x8, x16 SDRAM

Functional Description

Notes: 1. For full-page accesses: y = 2,048 (x4), y = 1,024 (x8), and y = 512 (x16).

2. For BL = 2, A1–A9, A11 (x4), A1–A9 (x8), or A1–A8 (x16) select the block-of-two burst; A0

selects the starting column within the block.

3. For BL = 4, A2–A9, A11 (x4), A2–A9 (x8), or A2–A8 (x16) select the block-of-four burst; A0–

A1 select the starting column within the block.

4. For BL = 8, A3–A9, A11 (x4), A3–A9 (x8), or A3–A8 (x16) select the block-of-eight burst; A0–

A2 select the starting column within the block.

5. For a full-page burst, the full row is selected and A0–A9, A11 (x4), A0–A9 (x8), or A0–A8

(x16) select the starting column.

6. Whenever a boundary of the block is reached within a given sequence above, the following

access wraps within the block.

CAS Latency

The CL is the delay, in clock cycles, between the registration of a READ command and

the availability of the first piece of output data. The latency can be set to 2 or 3 clocks.

If a READ command is registered at clock edge n and the latency is m clocks, the data will

be available by clock edge n + m. Th e D Q will start driving as a result of the clock edge 1

cycle earlier (n + m - 1), and pro vided that the relev ant access times are met, the data will

be valid by clock edge n + m. F or example , assuming that the clock cycle time is such that

all re lev ant access ti mes ar e met, if a r ead command is registered at T0 and the latency i s

programmed to 2 clocks, the DQ will start driving after T1 and the data will be valid by

T2, as shown in Figure 8 on page 20. Table 6 on page 20 indicates the operating frequen -

cies at which each CL setting can be used.

Reserved states should not be used as unknown oper ation or incompatibility with future

versions may result.

Table 5: Burst Definition

Burst

Length Starting Column

Address

Order of Accesses Within a Burst

Type = Sequential Type = Interleaved

2A0

00-1 0-1

11-0 1-0

A1 A0

0 0 0-1-2-3 0-1-2-3

0 1 1-2-3-0 1-0-3-2

1 0 2-3-0-1 2-3-0-1

1 1 3-0-1-2 3-2-1-0

A2 A1 A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Full page

(y) n = A0–A11/9/8

(location 0–y)

Cn, Cn + 1, Cn + 2,

Cn + 3, Cn + 4...,

...Cn - 1, Cn Not supported

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Functional Description

Figure 8: CAS Latency

Operating Mode

The normal operating mode is selected by setting M7 and M8 to 0; the other combina-

tions of values for M7 and M8 are reser ved for future use and/or test modes. The

programmed BL applies to both read and write bursts.

Test modes and reserved states should not be used because unknow n operation or

incompatibility with future versions may result.

Write Burst Mode

When M9 = 0, the BL programmed via M0–M2 applies both to read and write bursts;

when M9 = 1, the programmed BL applies to read bursts, but write accesses are single-

location (nonburst) accesses.

Table 6: CAS Latency

Speed

Allowable Operating Frequency (MHz)

CL = 2 CL = 3

-6A – ≤ 167

-7E ≤ 133 ≤ 143

-75 ≤ 100 ≤ 133

CLK

T2T1 T3T0

CL = 3

DOUT

tOH

COMMAND NOPREAD

tAC

NOP

DON’T CARE

UNDEFINED

CLK

T2T1 T3T0

CL = 2

DOUT

tOH

COMMAND NOPREAD

tAC

NOP

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128Mb: x4, x8, x16 SDRAM

Commands

Commands Table 7 provides a quick reference of available commands. This is followed by a written

description of each command. Three additional truth tables appear following “Opera-

tions” on page 24; these tables provide current state/next state information.

Table 7: Truth Table 1 – Commands and DQM Operation

CKE is HIGH for all commands shown except SELF REFRESH

Name (Function) CS# RAS# CAS# WE# DQM ADDR DQ Notes

COMMAND INHIBIT (NOP) HXXXXXX

NO OPERATION (NOP) L H H H X X X

ACTIVE (Sel ec t ban k an d activate row) L L H H X Bank/

row X 1

READ (Select bank and column, and start READ

burst) L H L H L/H8 Bank/

colX 2

WRITE (Select bank and column, and start WRITE

burst) L H L L L/H8 Bank/

col Valid 2

BURST TERMINATE L H H L X X Active

PRECHARGE (Deactivate row in bank or banks) L L H L X Code X 3

AUTO refresh or self refresh

(Enter self refresh mode) L L L H X X X 4, 5

LMR L L L L X Op-

code X 6

Write enable/output enable ––––L–Active 7

Write inhibit/output High-Z – – – – H – High-Z 7

Notes: 1. A0–A11 provide row address, and BA0, BA1 determine which bank is made active.

2. A0–A9; A11 (x4); A0–A9 (x8); or A0–A8 (x16) provide column address; A10 HIGH enables the

auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge fea-

ture; BA0, BA1 determine which bank is being read from or written to.

3. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged

and BA0, BA1 are “Don’t Care.”

4. This command is AUTO REFRESH if CKE is HIGH and SELF REFRESH if CKE is LOW.

5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except

for CKE.

6. A0–A11 define the op-code written to the mode register.

7. Activates or deactivates the DQ during WRITEs (0-clock delay) and READs (2-clock delay).

COMMAND INHIBIT

The COMMAND INHIBIT function pr events new commands from being executed b y the

SDRAM, regardless of whether the CLK signal is e nabled. The SDRAM is effectively dese-

lected. Operations already in progress are not affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM, which is

selected (CS# is L O W). This prevents unwanted commands fr om bein g r egister ed during

idle or wait states. Operations already in progress are not affected.

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128Mb: x4, x8, x16 SDRAM

Commands

LOAD MODE REGISTER (LMR)

The mode register is loaded via inputs A0–A11 (A12 should be driven LOW). See “Mode

can only be issued when all banks are idle, and a sub sequent executable command

cannot be issued until tMRD is met.

ACTIVE

The ACTIVE command is used to open (or activate) a row in a particular bank for a

subsequent access. The value on the BA0, BA1 inputs selects the bank, and the addr ess

provided on inputs A0–A11 s el ects th e row. This row rema ins acti ve (or ope n ) for

accesses until a PRECHARGE command is issued to that bank. A PRECHARGE

command must be issued before opening a different row in the same bank.

READ

The READ command is used to initiate a burst r ead access to an activ e row. The value on

the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A9, A11

(x4), A0–A9 (x8), or A0–A8 (x16) selects the starting column location. The value on input

A10 determines whether auto precharge is used. If auto precharge is selected, the row

being accessed will be precharged at the end of the read burst; if auto precharge is not

selected, the row will remain open for subsequent accesses. Read data appears on the

DQs subject to the logic level on the DQM inputs 2 clocks earlier. If a given DQM signal

was registered HIGH, the corresponding DQ will be High-Z 2 clocks later; if the DQM

signal was registered LOW, the DQ will provide valid data.

WRITE

The WRITE command is used to initiate a burst write access to an active row. The value

on the BA0, BA1 inputs selects the bank, and the ad dress provided on inputs A0–A9, A11

(x4), A0–A9 (x8), or A0–A8 (x16) selects the starting column location. The value on input

A10 determines whether auto precharge is used. If auto precharge is selected, the row

being accessed will be precharged at the end of the write burst; if auto prechar ge is not

selected, the row will r emain open for s ubsequent accesses . I nput data appearing on the

DQ is written to the memory array subject to the DQM input logic leve l appearing coin-

cident with the data. If a given DQM signal is registered LOW, the corresponding data

will be written to memory; if the DQM signal is r e gistered HIGH, the corresponding data

inputs will be ignored, and a write will not be executed to that byte/column location.

PRECHARGE

The PRECHARGE command is used to deactivate the open row in a particular bank or

the open row in all banks. The bank(s) will be available for a subsequent row access a

specifie d time (tRP) after the PRECHARGE command is issued. Input A10 determines

whether one or all banks ar e to be precharged, and in the case where only one bank is to

be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as

“Don’t Care.” After a bank has been precharg ed, it is in the idle state and must be acti-

vated prior to any READ or WRITE commands being issued to that bank.

Auto Precharge

Auto precharge is a feature that performs the same individua l-b ank precharge function

described above , without r e quiring an explic it command. This is accomplished by using

A10 to enable auto precharge in conjunction with a specific READ or WRITE command.

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128Mb: x4, x8, x16 SDRAM

Commands

A prechar ge of the bank/row that is addressed with the READ or WRITE command is

automatically performed upon completion of the READ or WRITE burst, except in the

full-page burst mode, where auto precharge does not apply. Auto precharge is nonper-

sistent in that either it is enabled or disabled for each individual READ or WRITE

command.

Auto precharge ensures that the precharge is initiated at the earliest valid stage within a

burst. The user must not issue another command to the same bank until the precharge

time (tRP) is completed. This is determined as if an explicit PRECHARGE command was

issued at the earliest possible time, as described for each burst type in the “Operations”

section on page 24.

BURST TERMINATE

The BURST TERMINATE command is used either to truncate fixed-length or full-page

bursts. The most recently re gistered READ or WRITE command prior to the BURST

TERMINATE command will be truncated, as shown in the “Operations” section on

page 24.

The BURST TERMINATE command does not precharge the row; the row will remain

open until a PRECHARGE command is issued.

AUTO REFRESH

AUTO REFRESH is used during normal operation of the SDRAM and is analogous to

CAS#-BEFORE-RAS# (CBR) refresh in older DRAM s. This command is nonpersistent, so

it must be issued each time a re fre sh is r equir ed. All acti ve banks must be PRECHAR GED

prior to issuing an AUT O REFRESH command. The AUTO REFRESH command should

not be issued until the minimum tRP has been met after the PRECHARGE command as

shown in the operation section.

The addressing is generated by the internal refresh controller. This makes the address

bits “Don’t Care” during an AUTO REFRESH command. Regardless of device width, the

128Mb SDRAM requires 4,096 AUTO REFRESH cycles every 64ms (commercial and

industrial) or 16ms (automotive). Providing a distributed AUTO REFRESH command

every 15.625µs (commercial and industrial) or 3.906µs (automotive) will meet the

refresh requirement and ensure that each row is refreshed. Alternatively, 4,096 AUTO

REFRESH commands can be issued in a burst at the minimum cycl e rate ( tRFC), once

every 64ms (commercial and industrial) or 16ms (automotive).

SELF REFRESH

The SELF REFRESH co mm and can be use d to retain data in the SDRAM, even if the rest

of the system is powered down. When in the self r efresh mode, the SDRAM retains data

without external clo ck ing. The SELF REF RESH com m and is initiated like an AUTO

REFRESH command except CKE is disabled (LOW). After the SELF REFRESH command

is registered, all the inputs to the SDRAM become “Don’t Care” with the exception o f

CKE, which must remain LOW.

After self refresh mode is engaged, the SDRAM provides its own internal clocking,

causing it to perform its o wn auto r e fr esh cy cles . The SDRAM must r emain in self r efr esh

mode for a minimum period equal to tRAS and may remain in self refresh mode for an

indefinite period beyond that.

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Operations

The procedur e for exit ing self r efresh requires a sequence of commands . F irst, CLK m ust

be stable (stable clock is defined as a signal cycling within timing constraints specified

for the clock pin) prior to CKE going back HIGH. After CKE is HIGH, the SD RA M mus t

have NOP commands issued (a minimum of 2 clocks) for tXSR because this amount of

time is required for the completion of any internal refresh in progr ess.

Upon exiting the self refresh mode, AUTO REFRESH commands must be issued every

15.625µs or less because both SELF REFRESH and AUTO REFRESH utilize the row

refresh counter.

Self refresh is not supporte d on automotive temperature (AT) devices .

Operations

Bank/row Activation

Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row

in that bank must be “opened.” This is accomplished via the ACTIVE command, which

selects both the bank and the row to be activated (see Figure 9 on page 25).

After opening a ro w (issuing an A CTIVE command), a RE AD or WRITE command may be

issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by

the clock period and rounded up to the next whole number to determine the earliest

clock edge after the ACTIVE command on which a READ or WRITE command can be

entered. Fo r e xample, a tRCD specification of 20ns with a 125 MHz clock (8ns period)

results in 2.5 clocks, rounded to 3. This is r eflected in Figure 10 on page 25, which covers

any case where 2 < tRCD (MIN)/tCK ≤ 3. (The same procedure is used to convert other

specificati o n limits from time units to clock cycle s.)

A subsequent ACTIVE command to a differ ent row in the same bank can only be issued

after the previous active row has been “closed” (precharged). The minimum time

interval between successive ACTIVE commands to the same bank is defined by tRC.

A subsequent ACTIVE command to another bank can be issued while the first bank is

being accessed, which resul ts in a r eduction of total r o w-access o verhead. The minimum

time interval between successive ACTIVE commands to different banks is defined by

tRRD.

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128Mb: x4, x8, x16 SDRAM

Operations

Figure 9: Activating a Specific Row in a Specific Bank

Figure 10: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK ≤ 3

Reads

READ bursts are initiated with a READ command, as shown in Figure 11 on page 26.

The starting column and bank addresses are provided with the READ command, and

auto precharg e either i s enabled or disabled for that burst access. If auto precharge is

enabled, the row being accessed is precharged at the completion of the burst. For the

generic READ commands used in the following illustrations, auto precharge is disabled.

During READ bursts, the valid data-out element from the starting column address will

be available following the CL after the READ command. Each subsequent data-out

element will be v ali d by the next positive clock edge. Figure 12 on page 26 sho ws genera l

timing for each possible CL setting.

Upon completion of a burst, assuming no other commands have been initia ted, the DQ

will go High-Z . A full-page burst will continue until terminated. (At the end of the page , it

will wrap to column 0 and continue.)

CS#

WE#

CAS#

RAS#

CKE

CLK

A0–A10, A11 ROW

ADDRESS

DON’T CARE

HIGH

BA0, BA1 BANK

ADDRESS

CLK

T2T1 T3T0

COMMAND NOPACTIVE READ or

WRITE

NOP

RCD

DON’T CARE

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128Mb: x4, x8, x16 SDRAM

Operations

Figure 11: READ Command

Figure 12: CAS Latency

CS#

WE#

CAS#

RAS#

CKE

CLK

COLUMN

ADDRESS

A10

BA0, BA1

HIGH

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

BANK

ADDRESS

A0–A9, A11: x4

A0–A9: x8

A0–A8: x16

A11: x8

A9, A11: x16

CLK

T2T1 T3T0

CL = 3

DOUT

tOH

COMMAND NOPREAD

tAC

NOP

UNDEFINED

DON’T CARE

CLK

T2T1 T3T0

CL = 2

DOUT

tOH

COMMAND NOPREAD

tAC

NOP

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128Mb: x4, x8, x16 SDRAM

Operations

Data from any READ burst may be truncated with a subsequent READ com ma nd, and

data from a fixed-length READ burst may be immediately followed by data from a READ

command. In either case, a continuous flow of data can be maintained. The first data

element from the new burst either follows the last element of a completed burst or the

last desired data element of a longer burst that is being truncated. The new READ

command should be issued x cycles before the clock edge at which the last desired data

element is valid, where x = CL - 1.

This is shown in Figure 13 for L = 2 and CL = 3; data element n + 3 is either the last of a

burst of four or the last desired of a longer burst. The 128Mb SDRAM uses a pipelined

architec ture and, therefore, does not require the 2n rule associated with a prefetch ar chi-

tectur e. A READ command can be i nitiated on any clock cycle fol lo wing a previous READ

command. Full-speed random read accesses can be performed to the same bank, as

shown in Figure 14 on page 28, or each subsequent READ may be performed to a

different bank.

Figure 13: Consecutive READ Bursts

Notes: 1. Each READ command may be to any bank. DQM is LOW.

DON’T CARE

CLK

DQ D

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK,

COL n

NOP

BANK,

COL b

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3 D

OUT

READ

X = 1 cycle

CL = 2

CLK

DQ D

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK,

COL n

NOP

BANK,

COL b

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3 D

OUT

READ NOP

X = 2 cycles

CL = 3

TRANSITIONING DATA

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128Mb: x4, x8, x16 SDRAM

Operations

Figure 14: Random READ Accesses

Notes: 1. Each READ command may be to any bank. DQM is LOW.

Data from any READ burst may be truncated with a subsequent WRITE command, and

data from a fixed-length READ burs t may be immediately followed by data from a

WRITE command (subject to bus turnaround limitations). Th e WRI TE burst may be

initiated on the clock edge immediately following the last (or last desired) data element

from the READ burst, provided that I/O contention can be avoided. In a given system

design, ther e may be a possibility that the device driving the input data will go Low-Z

before the SDRAM DQ go High-Z. In this case, at least a single-cycle delay should occur

between the last read data and the WRITE command.

The DQM input is used to avoid I/O contention, as shown in Figure 15 on page 29 and

Figure 16 on page 29. The DQM signal must be asserted (HIGH) at leas t 2 clocks prior to

the WRITE command (DQM latency is 2 clocks for output buffers) to suppress data-out

from the READ. After the WRITE command is registered, the DQ will go High-Z (or

remai n High-Z), regardless of the state of the DQM signal, provided the DQM was active

on the clock just prior to the WRITE command that truncated the READ command. If

not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during

T4 in Figure 16, then the WRITEs at T5 and T7 would be vali d, whil e the WRIT E at T6

would be invalid.

CLK

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP

BANK,

COL n

DON’T CARE

OUT

READ READ READ NOP

BANK,

COL aBANK,

COL xBANK,

COL m

CLK

OUT

T2T1 T4T3 T5T0

COMMAND

ADDRESS

READ NOP

BANK,

COL n

OUT

READ READ READ NOP

BANK,

COL aBANK,

COL xBANK,

COL m

CL = 2

CL = 3

TRANSITIONING DATA

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128Mb: x4, x8, x16 SDRAM

Operations

The DQM signal must be de-asserted prior to the WRITE command (DQM latency is

zero clocks for input buffers) to ensure that the written data is not masked. Figure 15

shows the case where the clock frequency allows for bus contention to be avoided

without adding a NOP cycle, and Figure 16 shows the case where the additional NOP is

needed.

Figure 15: READ-to-WRITE

Notes: 1. CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE com-

mand may be to any bank. If a burst of 1 is used, then DQM is not required.

Figure 16: READ-to-WRITE with Extra Clock Cycle

Notes: 1. CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE com-

mand may be to any bank.

A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE

command to the same bank (provided that auto precharge was not activated), and a full-

page burst may be truncated with a PRECHARGE command to the same bank. The

PRECHAR GE command should be issued x cycles before the clock edge at which the last

DON’T CARE

READ NOP NOP WRITE

NOP

CLK

T2T1 T4T3T0

DQM

OUT

COMMAND

ADDRESS

BANK,

COL nBANK,

COL b

tHZ

tCK

TRANSITIONING DATA

DON’T CARE

READ NOP NOPNOP NOP

DQM

CLK

OUT

T2T1 T4T3T0

COMMAND

ADDRESS

BANK,

COL n

WRITE

BANK,

COL b

tHZ

TRANSITIONING DATA

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128Mb: x4, x8, x16 SDRAM

Operations

desired data element is valid, where x = CL - 1. This is shown in Figure 17 for each

possible CL; data element n + 3 is either the last of a burst of four or the last desired of a

longer burst. Following the PRECHARGE command, a subsequent command to the

same bank cannot be issued until tRP is met. Note that part of the row precharge time is

hidden during the access of the last data element(s).

In the case of a fixed-length burst being executed to completion, a PRECHARG E

command issued at the optimum time (as desc ribed abov e) provi des the same operation

that would result from the same fixed-length burst with auto precharge. The disadvan-

tage of the PRECHARGE command is that it requires that the command and address

buses be available at the appropriate time to issue the command; the advantage of the

PRECHARG E command is that it can be used to truncate fixed-leng th or full-page bursts .

Full-page READ bursts can be truncated with the BURST TERMINATE command, and

fixed-length READ bursts may be truncated with a BURST TERMINATE command,

provided that auto precharge was not activated. The BURST TERMINATE command

should be issued x cycles before the clock edge at which the last desired data element is

valid, where x = CL - 1. This is shown in Figure 18 on page 31 for each possible CL; data

element n + 3 is the last desired data element of a longer burst.

Figure 17: READ-to-PRECHARGE

Notes: 1. DQM is LOW.

DON’T CARE

CLK

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOPNOP PRECHARGE ACTIVE

tRP

CLK

DQ DOUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOPNOP

DOUT

n + 1 DOUT

n + 2 DOUT

n + 3

PRECHARGE ACTIVE

tRP

X = 1 cycle

CL = 2

CL = 3

X = 2 cycles

BANK a,

COL nBANK a,

ROW

BANK

(a or all)

BANK a,

COL nBANK a,

ROW

BANK

(a or all)

TRANSITIONING DATA

DOUT

nDOUT

n + 1 DOUT

n + 2 DOUT

n + 3

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Operations

Figure 18: Terminating a READ Burst

Notes: 1. DQM is LOW.

WRITEs

WRITE bursts are initiated with a WRITE command, as shown in Figure 19 on page 32.

The starting column and bank addresses are provided with the WRITE command, and

auto prec harge e ither is enabled or dis abled for that access . I f auto pr echarge is enabled,

the row being accessed is precharged at the completion of the burst. For the generic

WRITE commands us ed in the fol lowing illustrations, auto precharge is disabled.

During WRITE bursts, the first valid data-in element will be registered coincident with

the WRITE command. Subsequent data elements will be registered on each successive

positive clock edge. Upon completion of a fixed-length burst, assu ming no other

commands have been initiated, the DQ will remain High-Z and any additiona l input

data will be ignored (see Figure 20 on page 32). A full-page burst will continue until

terminated. (At the end of the page, it will wrap to column 0 and continue.)

CLK

DQ DOUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK,

COL n

NOP

DOUT

n + 1 DOUT

n + 2 DOUT

n + 3

BURST

TERMINATE NOP

DON’T CARE

CLK

DQ DOUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP

BANK,

COL n

NOP

DOUT

n + 1 DOUT

n + 2 DOUT

n + 3

BURST

TERMINATE NOP

X = 1 cycle

CL = 2

CL = 3

X = 2 cycles

TRANSITIONING DATA

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128Mb: x4, x8, x16 SDRAM

Operations

Figure 19: WRITE Command

Figure 20: WRITE Burst

Notes: 1. BL = 2. DQM is LOW.

Data for any WRITE burst may be truncated with a subsequent WRITE command, and

data for a fixed-length WRI TE burst may be immediately followed by data for a WRITE

command. The new WRITE command can b e issued on any c lock follo wi ng the pr evious

WRITE command, and the data provided coincident with the new command applie s to

the new command. An example is shown in Figure 21 on page 33. Data n + 1 is either the

last of a burst of two or the last desired element of a longer burst. The 128Mb SDRAM

uses a pipelined ar chitec ture and , ther efor e , does not r equir e the 2n rule associated with

CS#

WE#

CAS#

RAS#

CKE

CLK

COLUMN

ADDRESS

A10

DON’T CARE

HIGH

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

A0–A9, A11: x4

A0–A9: x8

A0–A8: x16

A11: x8

A9, A11: x16

BA0, BA1 BANK

ADDRESS

CLK

DQ DIN

T2T1 T3T0

COMMAND

ADDRESS

NOP NOP

DON’T CARE

WRITE

DIN

n + 1

NOP

BANK,

COL n

TRANSITIONING DATA

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128Mb: x4, x8, x16 SDRAM

Operations

a prefetc h arc hitectur e . A WRITE command can be initiated on any clock cycle following

a previous WRITE command. Full-speed random write accesses within a page can be

performed to the same bank, as sh own in Figure 22 on page 33, or each subsequent

WRITE may be performed to a different bank.

Data for any WRITE burst may be truncated with a subsequent READ command, and

data for a fixed -length WRITE burst m ay be imme diately fol lowed b y a REA D command.

After the READ command is registered, the data inputs will be ignor ed, and writes will

not be executed. An example is shown in Figure 23 on page 34. Data n + 1 is either the

last of a burst of two or the last desired element of a longer burst.

Figure 21: WRITE-to-WRITE

Notes: 1. DQM is LOW. Each WRITE command may be to any bank.

Figure 22: Random WRITE Cycles

CLK

T2T1T0

COMMAND

ADDRESS

NOPWRITE WRITE

BANK,

COL nBANK,

COL b

n + 1 D

DON’T CARE

TRANSITIONING DATA

DON’T CARE

CLK

DQ DIN

T2T1 T3T0

COMMAND

ADDRESS

WRITE

BANK,

COL n

DIN

aDIN

xDIN

WRITE WRITE WRITE

BANK,

COL aBANK,

COL xBANK,

COL m

TRANSITIONING DATA

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128Mb: x4, x8, x16 SDRAM

Operations

Figure 23: WRITE-to-READ

Data for a fixed-length WRITE burst may be followed by, or truncated with, a

PRECHARGE command to the same bank (provided that auto precharge was not acti-

vated), and a full-page WRITE burst may be truncated with a PRECHARGE command to

the same bank. The PRECHARGE command should be issued tWR after the clock edge at

which the last desired input data element is registered. The auto precharge mode

requires a tWR of at least 1 clock plus time (see note 24 on page 52), regardless of

frequency. In addition, when truncating a WRITE burst, the DQM signal must be used to

mask input data for the clock edge prior to, and the clock edge coincident with, the

PRECHARGE command. An example is shown in Figure 24 on page 35. Data n + 1 is

either the last of a burst of two or the last desired of a longer burst. Following the

PRECHAR GE command, a subsequent command to the same bank cannot be issued

until tRP is met.

In the case of a fixed-length burst being executed to completion, a PRECHARG E

command issued at the optimum time (as desc ribed abov e) provi des the same operation

that would result from the same fixed-length burst with auto precharge. The disadvan-

tage of the PRECHARGE command is that it requires that the command and address

buses be available at the appropriate time to issue the command; the advantage of the

PRECHAR GE command is that it can be used to truncate fixed-length or full-page bursts.

Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE

command. When truncating a WRITE burst, the inpu t data applied coincident with the

BURST TERMINATE command will be ignored. The last data written (provided that

DQM is LOW at that time) will be the input data applied 1 clock previous to the BURST

TERMINATE command. This is shown in Figure 25 on page 35, where data n is the last

desir ed data element of a longer burst.

DON’T CARE

CLK

T2T1 T3T0

COMMAND

ADDRESS

NOPWRITE

BANK,

COL n

n + 1 D

OUT

READ NOP NOP

BANK,

COL b

NOP

OUT

b + 1

T4 T5

TRANSITIONING DATA

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128Mb: x4, x8, x16 SDRAM

Operations

Figure 24: WRITE-to-PRECHARGE

Notes: 1. DQM could remain LOW in this example if the WRITE burst is a fixed length of two.

Figure 25: Terminating a WRITE Burst

Notes: 1. DQMs are LOW.

DON’T CARE

DQM

CLK

T2T1 T4T3T0

COMMAND

ADDRESS

BANK a,

COL n

NOPWRITE

PRECHARGE

NOPNOP

n + 1

ACTIVE

tRP

BANK

(a or all)

BANK a,

ROW

DQM

COMMAND

ADDRESS

BANK a,

COL n

NOPWRITE

PRECHARGE

NOPNOP

n + 1

ACTIVE

tRP

BANK

(a or all)

BANK a,

ROW

NOP

tWR @ tCLK ≥ 15ns

tWR = tCLK < 15ns

TRANSITIONING DATA

DON’T CARE

CLK

T2T1T0

COMMAND

ADDRESS BANK,

COL n

WRITE BURST

TERMINATE NEXT

COMMAND

(ADDRESS)

(DATA)

TRANSITIONING DATA

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128Mb: x4, x8, x16 SDRAM

Operations

PRECHARGE

The PRECHARGE command (see Figure 26) is used to deactivate the open row in a

particular bank or the open row in all banks. The bank(s) will be available for a subse-

quent row access some specified time (tRP) after the PRECHARGE command is issued.

Input A10 determines whether one or all banks are to be precharged, and in the case

where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all

banks are to be pr echarged, inputs BA0, BA1 ar e tr eated as “ Don’t Car e .” After a bank has

been pre charged, it is in the idle state and must be activated prior to any READ or WRITE

commands being issued to that bank.

Figure 26: PRECHARGE Command

Power-Down

Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND

INHIBIT when no accesses are in progress. If power-down occurs when all banks are

idle, this mode is referred to as precharge power -down; if power-down occurs when

there is a ro w activ e in any bank, this mode is referred to as active power-down. Entering

power-down deactivates the input and output buffers, excluding CKE, for maximum

power savings while in standby. The device may not remain in the power-down state

longer than the refresh period (tREF or tREFAT) since no REFRESH operations are

performed in this mode.

The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE

HIGH at the desired clock edge (meeting tCKS). See Figure 27 on page 37.

CS#

WE#

CAS#

RAS#

CKE

CLK

A10

DON’T CARE

HIGH

All Banks

Bank Selected

A0–A9

BA0, BA1

BANK

ADDRESS

VALID ADDRESS

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Operations

Figure 27: Power-Down

Clock Suspend

The clock suspend mode occurs when a column access/burst is in progress and CKE is

registered low. In the clock suspend mode, the internal clock is deactivated, “freezing”

the synchronous logic.

For each positive clock edge on which CKE is sampled LOW, the next internal positive

clock edge is suspended. Any command or data pr esent on the input pins at the time of a

suspended internal clock edge is ignored; any data present on the DQ pins remains

driven; and burst counters are not incremented, as long as the clock is sus pen ded. (See

examples in Figure 28 and Figure 29 on page 38.)

Clock suspend mode is exited by registering CKE HIGH; the internal clock and related

operation will resume on the subsequent positive clock edge.

Figure 28: Clock Suspend During WRITE Burst

DON’T CARE

tRAS

tRCD

tRC

All banks idle Input buffers gated off

Exit power-down mode

()()

tCKS > tCKS

COMMAND

NOP ACTIVE

Enter power-down mode

NOP

CLK

CKE

()()

DON’T CARE

COMMAND

ADDRESS

WRITE

BANK,

COL n

NOPNOP

CLK

T2T1 T4T3 T5T0

CKE

INTERNAL

CLOCK

NOP

n + 1 D

n + 2

TRANSITIONING DATA

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Operations

Figure 29: Clock Suspend During READ Burst

Notes: 1. For this example, CL = 2, BL = 4 or greater, and DQM is LOW.

BURST READ/SINGLE WRITE

The burst read/single write mode is entered by programming the write burst mode bit

(M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the

access of a single column location (burst of one), regardless of the programmed BL.

READ commands access columns according to the programmed BL and sequence, just

as in the normal mode of operation (M9 = 0).

Concurrent Auto Precharge

An access command (READ or WRITE) to another bank while an access command with

auto precharge enabled is executing is not allowed by SDRAMs, unle ss the SDRAM

supports con current auto precharge. Micron SDRAMs support co ncurrent auto

precharge. Fo ur cas es where concurrent auto precharge occurs are defined below.

READ with Auto Precharge

• Int errupted by a READ (with or without auto prechar ge): A READ to bank m will inter-

rupt a READ on bank n, CL later. The precharge to bank n will begin when the READ

to bank m is registered (Figure 30 on page 39).

• Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will

interrupt a READ on bank n when registered. DQM should be used 2 clocks prior to

the WRITE command to prevent bus conten tion. The precharge to bank n will begin

when the WRITE to bank m is registered (Figure 31 on page 39).

DON’T CARE

CLK

DQ DOUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP

BANK,

COL n

NOP

DOUT

n + 1 DOUT

n + 2 DOUT

n + 3

CKE

INTERNAL

CLOCK

NOP

TRANSITIONING DATA

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128Mb: x4, x8, x16 SDRAM

Operations

Figure 30: READ With Auto Precharge Interrupted by a READ

Notes: 1. DQM is LOW.

Figure 31: READ With Auto Precharge Interrupted by a WRITE

Notes: 1. DQM is HIGH at T2 to prevent DOUT a + 1 from contendi ng with DIN at T4.

WRITE with Auto Precharge

• Int errupted by a READ (with or without auto prechar ge): A READ to bank m will inter-

rupt a WRITE on bank n when registered, with the data-out appearing CL later. The

precharge to bank n will begin after tWR is met, where tW R be gi ns whe n the REA D to

bank m is registered. The last valid WRITE to bank n will be data-in registered one

clock prior to the READ to bank m (Figure 32 on page 40).

DON’T CARE

CLK

DQ DOUT

T2T1 T4T3 T6T5T0

COMMAND READ - AP

BANK nNOP NOPNOPNOP

DOUT

a + 1 DOUT

dDOUT

d + 1

NOP

BANK n

CL = 3 (BANK m)

BANK m

ADDRESS

Idle

NOP

BANK n,

COL aBANK m,

COL d

READ - AP

BANK m

Internal

States t

Page Active READ with Burst of 4 Interrupt Burst, Precharge

Page Active READ with Burst of 4 Precharge

RP - BANK n tRP - BANK m

CL = 3 (BANK n)

TRANSITIONING DATA

CLK

T2T1 T4T3 T6T5T0

COMMAND NOPNOPNOPNOP

DIN

d + 1

DIN

dDIN

d + 2 DIN

d + 3

NOP

BANK n

BANK m

ADDRESS

Idle

NOP

DQM1

BANK n,

COL aBANK m,

COL d

WRITE - AP

BANK m

Internal

States t

Page

Active READ with Burst of 4 Interrupt Burst, Precharge

Page Active WRITE with Burst of 4 Write-Back

RP - BANK ntWR - BANK m

CL = 3 (BANK n)

READ - AP

BANK n

DON’T CARETRANSITIONING DATA

DOUT

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128Mb: x4, x8, x16 SDRAM

Operations

• Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will

interrupt a WRITE on bank n when registered. The precharge to bank n will begin

after tWR is met, where tWR begins when the WRITE to bank m is registered. The last

valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank

m (Figure 33).

Figure 32: WRITE With Auto Precharge Interrupted by a READ

Notes: 1. DQM is LOW.

Figure 33: WRITE With Auto Precharge Interrupted by a WRITE

Notes: 1. DQM is LOW.

DON’T CARE

CLK

T2T1 T4T3 T6T5T0

COMMAND

WRITE - AP

BANK nNOPNOPNOPNOP

a + 1

NOP NOP

BANK n

BANK m

ADDRESS

BANK n,

COL aBANK m,

COL d

READ - AP

BANK m

Internal

States

Page Active WRITE with Burst of 4

Interrupt Burst, Write-Back

Precharge

Page Active READ with Burst of 4

RP - BANK m

OUT

d + 1

CL = 3 (BANK m)

RP - BANK n

WR - BANK n

TRANSITIONING DATA

DON’T CARE

CLK

T2T1 T4T3 T6T5T0

COMMAND

WRITE - AP

BANK nNOPNOPNOPNOP

d + 1

a + 1 D

a + 2

d + 2 D

d + 3

NOP

BANK n

BANK m

ADDRESS

NOP

BANK n,

COL aBANK m,

COL d

WRITE - AP

BANK m

Internal

States

Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge

Page Active WRITE with Burst of 4 Write-Back

tWR - BANK n

RP - BANK n

tWR - BANK m

TRANSITIONING DATA

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128Mb: x4, x8, x16 SDRAM

Operations

Notes: 1. CKEn is the logic state of CKE at clock edge n; CKEn - 1 was the state of CKE at the previous

clock edge.

2. Current state is the state of the SDRAM immediately prior to clock edge n.

3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COM-

MANDn.

4. All state s and sequences not shown are illegal or reserved.

5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for

clock edge n + 1 (provided that tCKS is met).

6. Exiting self refresh at clock edge n will put the device in the all banks idle state after tXSR is

met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring

during the tXSR period. A minimum of two NOP commands must be provided during tXSR

period.

7. After exiting clock suspend at clock edge n, the device will resume operati on and re cognize

the next command at clock edge n + 1.

Table 8: Truth Table 2 – CKE

Notes: 1–4

CKEn - 1 CKEnCurrent State CommandnActionnNotes

L L Power-down X Maintain power-down

Self refresh X Maintain self refresh

Clock suspend X Maintain clock suspend

L H Power-down COMMAND INHIBIT or NOP Exit power-down 5

Self refresh COMMAND INHIBIT or NOPX Exit self refresh 6

Clock suspend X Exit clock suspend 7

H L All banks idle COMMAND INHIBIT or NOP Power-down entry

All banks idle AUTO REFRESH Self refresh entry

Reading or writing WRITE or NOP Clock suspend entry

H H See Table 9 on page 42

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128Mb: x4, x8, x16 SDRAM

Operations

Notes: 1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH (see Table 8 on page 41) and

after tXSR has been met (if the previous state was self refresh).

2. This table is bank-specific, except where noted; that is, the current state is for a specific

bank, and the commands shown are those allowed to be issued to that bank when in that

state. Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and tRP has been met.

Row active: A row in the bank has been activated, and tRCD has been met. No data

bursts/accesses and no register accesses are in progress.

Read: A READ burst has been initiated, with auto precharge disabled, and has not

yet terminated or been terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not

yet terminated or been terminated.

4. The following states must not be interrupted by a command issued to the same bank. COM-

MAND INHIBIT or NOP commands or allowable commands to the other bank should be

issued on any clock edge occurring during these states. Allowable commands to the other

bank are determined by its current state and Truth Table 3 and according to Truth Table 4.

Precharging: Starts with registration of a PRECHARG E com m an d an d ends when

tRP is met. After tRP is met, the bank will be in the idle state.

Row activating: Starts with registration of an ACTIVE command and ends when tRCD

is met. After tRCD is met, the bank will be in the row active state.

Read w/auto

precharge enabled: Starts with registration of a READ command with auto precharge

enabled and ends when tRP has been met. After tRP is met, the bank

will be in the idle state.

Write w/auto

precharge enabled: Starts with registration of a WRITE command with auto precharge

enabled and ends when tRP has been met. After tRP is met, the bank

will be in the idle state.

Table 9: Truth Table 3 – Current State Bank n, Command to Bank n

Notes: 1–6; notes appear below an d on next page

Current

State CS# RAS# CAS# WE# Command (Action) Notes

Any HXXX

COMMAND INHIBIT (NO P/continue previ ous operation)

LHHH

NO OPERATION (NOP/continue previous operati on)

Idle L L H H ACTIVE (Select and activate row)

LLLH

AUTO REFRESH 7

LLLL

LMR 7

LLHL

PRECHARGE 11

Row activeLHLH

READ (Select column and start READ burst) 10

LHLL

WRITE (Select column and start WRITE burst) 10

LLHL

PRECHARGE (Deactivate row in bank or banks) 8

Read

(auto

precharge

disabled)

LHLH

READ (Select column and start new READ burst) 10

LHLL

WRITE (Select column and start WRITE burst) 10

LLHL

PRECHARGE (Truncate READ burst, start precharge) 8

LHHL

BURST TER MINATE 9

Write

(Aauto

precharge

disabled)

LHLH

READ (Select column and start READ burst) 10

LHLL

WRITE (Select column and start new WRITE burst) 10

LLHL

PRECHARGE (Truncate WRITE burst, start precharge) 8

LHHL

BURST TER MINATE 9

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Operations

5. The following states must not be interrupted by any executable command; COMMA ND

INHIBIT or NOP commands must be applied on each positive clock edge during these states.

Refreshing: Starts with registra tion of an AUTO REFRESH comma nd and ends

when tRC is met. After tRC is met, the SDRAM will be in the all banks

idle state.

Accessing mode

has been met. After tMRD is met, the SDRAM will be in the all banks

idle state.

Precharging all: Starts with registration of a PRECHARGE ALL command and ends

when tRP is met. After tRP is met, all banks will be in the idle state.

6. All states and sequences not sh own are illegal or reserved.

7. Not bank-specific; requires that all banks are idle.

8. May or may not be bank-s pecific; if all banks are to be precharged, all must be in a valid

state for precharging.

9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regard-

less of bank.

10. READs or WRITEs listed in the Command (Action) column incl ude READs or WRITEs with

auto precharge enabled and READs or WRITEs with auto precharge disabled.

11. Does not affect the state of the bank and acts as a NOP to that bank.

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Operations

Notes: 1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH (see Table 8 on page 41) and

after tXSR has been met (if the previous state was self refresh).

2. This table describes alternate bank operation, except where noted; that is, the current state

is for bank n, and the commands shown are those allowed to be issued to bank m (assuming

that bank m is in such a state that the given command is allowable). Exceptions are covered

in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and tRP has been met.

Row active: A row in the bank has been activated, and tRCD has bee n me t . No

data bursts/accesses and no register accesses are in progress.

Read: A READ burst has been initiated, with auto precha rge disabl ed, and

has not yet terminated or been terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and

has not yet terminated or been terminated.

Read w/auto

precharge enabled: Starts with registration of a READ command with auto precharge

enabled, and ends when tRP has been met. After tRP is met, the

bank will be in the idle state.

Write w/auto

precharge enabled: Starts with registration of a WRITE command with auto precharge

enabled, and ends when tRP has been met. After tRP is met, the

bank will be in the idle state.

4. AUTO REFRESH, SELF REFRESH, and LMR commands may o nly be issued when all banks are

idle.

Table 10: Truth Table 4 – Current State Bank n, Command to Bank m

Notes: 1–6; notes appear below an d on next page

Current

State CS# RAS# CAS# WE# Command (Action) Notes

Any HXXX

COMMAND INHIBIT (NO P/continue previ ous operation)

LHHH

NO OPERATION (NOP/continue previous operati on)

Idle XXXX

Any command otherw ise allowed to bank m

Row

activating,

active, or

precharging

LLHH

ACTIVE (Select and activate row)

LHLH

READ (Select column and start READ burst) 7

LHLL

WRITE (Select column and start WRITE burst) 7

LLHL

PRECHARGE

Read

(auto

precharge

disabled)

LLHH

ACTIVE (Select and activate row)

LHLH

READ (Select column and start new READ burst) 7, 10

LHLL

WRITE (Select column and start WRITE burst) 7, 11

LLHL

PRECHARGE 9

Write

(auto

precharge

disabled)

LLHH

ACTIVE (Select and activate row)

LHLH

READ (Select column and start READ burst) 7, 12

LHLL

WRITE (Select column and start new WRITE burst) 7, 13

LLHL

PRECHARGE 9

Read

(with auto

precharge)

LLHH

ACTIVE (Select and activate row)

LHLH

READ (Select column and start new READ burst) 7, 8, 14

LHLL

WRITE (Select column and start WRITE burst) 7, 8, 15

LLHL

PRECHARGE 9

Write

(with auto

precharge)

LLHH

ACTIVE (Select and activate row)

LHLH

READ (Select column and start READ burst) 7, 8, 16

LHLL

WRITE (Select column and start new WRITE burst) 7, 8, 17

LLHL

PRECHARGE 9

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Operations

5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank

represented by the current state only.

6. All state s and sequences not shown are illegal or reserved.

7. READs or WRITEs to bank m listed in the Command (Action) column includ e READs or

WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.

8. Conc urrent auto precharge: Bank n will initiate the auto pr echarge command when its

burst has been interrupted by bank m’s burst.

9. Burst in bank n conti nues as initiated.

10. For a READ without auto precharge interrupted by a READ (with or without auto pre-

charge), the READ to bank m will interrupt the READ on bank n, CL later (Figure 13 on

page 27).

11. For a READ without auto precharge interrupted by a WRITE (with or without auto pre-

charge), th e WRITE to bank m will interrupt the READ on bank n when registered (Figure 15

on page 29 an d Figure 16 on page 29). DQM should be used 1 clock prior to the WRITE com-

mand to prevent bus contention.

12. For a WRITE without auto precharge inte rrupted by a READ (with or without auto pre-

charge), the READ to bank m will interrupt the WRITE on bank n when registered (Figure 23

on page 34), with the data-out appearing CL later. The last valid WRITE to bank n will be

data-in registered 1 clock prior to the READ to bank m.

13. For a WRITE without auto precharge inte rrupted by a WRITE (with or without auto pre-

charge), th e WR ITE to bank m will interrupt the WRITE on bank n when registered

(Figure 21 on page 33). The la s t val id WRIT E t o ba nk n will be data-in registered 1 clock

prior to the READ to bank m.

14. For a READ with auto precharge interrupted by a READ (with or without auto precharge),

the READ to bank m will interrupt the READ on bank n, CL later. The pr echarge to bank n

will begin when the READ to bank m is registered (Figure 30 on page 39).

15. For a READ with auto precharge interrupted by a WRITE (with or wit h out auto precharge),

the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be

used 2 clocks prior to the WRITE command to prevent bus contention. The precharge to

bank n will begi n when the WRITE to bank m is registered (Figure 31 on page 39).

16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge),

the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out

appearing CL later. The precharge to bank n will begin after tWR is met, where tWR begins

when the READ to bank m is registered. The last valid WRITE to bank n will be data-in regis-

tered one clock prior to the READ to bank m (Figure 32 on page 40).

17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge) ,

the WRITE to bank m will interrupt the WRITE on bank n when registered. The precharge to

bank n will begi n after tWR is met, where tWR begins when the WRITE to bank m is regis-

tered. The last valid WRITE to bank n will be data registered 1 clock prior to the WRITE to

bank m (Figure 33 on page 40).

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Electrical Specifications

S tresses greater than those listed in Table 11 may cause per m anen t damage to the

device. This is a stress rating only, and functional operation of the device at these or any

other conditions above those indicated in the operational sections of this specification is

not implied. Exposure to absolute maximum rating condi tions for extended periods may

affect reli ability.

Temperature and Thermal Impedance

It is imper ative that the SDRAM device’s temperature specifications, shown in Table 12

on page 47, be maintained to ensure the junction temperature is in the proper operating

range to meet data sheet specifications. An important step in maintaining the proper

junction temperature is using the device’s thermal impedances correctly. The thermal

impedances are listed in Table 13 on page 47 for the applicable die revision and pack-

ages being made available. The se thermal impedance values v a ry according to the

density, package, and particular design used for each device.

Incorr ectly using thermal impedances can produce significant errors. Read Micron tech-

nical note TN-00-08, “Thermal Applications” prior to using the thermal impedances

listed in Table 13. To ens u re the compatib il it y o f current and future designs, contact

Micron Applications Engineering to confirm the rmal impedance values.

The SDRAM device’s safe junction temperature r a nge can be maintained when the T C

specification is not exceeded. In applications where the device’s ambient temper ature is

too high, use of forced air and/or heat sinks may be required to satisfy the case tempera-

ture specifications.

Table 11: Absolute Maximum Ratings

Parameter Min Max Rating

Voltage on VDD/VDDQ supply relative to VSS –1 +4.6 V

Voltage on inputs, NC or I/O pins relative to VSS –1 +4.6 V

Operating temperature

TA (commercial)

TA (industrial)

TA (autom otive)

–40

+70

+85

+105

°C

Storage temperature (plastic) –55 +150 °C

Power dissipation 1W

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Electrical Specifications

Notes: 1. MAX operating case temperature, TC is measured in the center of the package on the top

side of the device, as shown in Figure 34, Figure 35, and Figure 36 on page 48.

2. Device functionality is not guaranteed if the device exceeds maximum TC during operation.

3. All temper ature specifications must be satisfied

4. The case temperature should be measured by gluing a thermocouple to the top center of

the component. This should be done with a 1mm bead of conductive epoxy, as defined by

the JEDEC EIA/JESD51 standards. Care should be taken to ensure the ther mocouple bead is

touching the case.

5. Operating ambient temperature surrounding the package.

Notes: 1. For designs expected to last beyond the die revision listed, contact Micron Applications

Engineering to confirm thermal impedance values.

2. Thermal resistance data is sampled from multiple lots, and the values should be viewed as

typical.

3. These are estimates; actual results may vary.

Table 12: Temperature Limits

Parameter Symbol Min Max Units Notes

Operating case temperature:

Commercial

Industrial

Automotive

TC0

–40

105

°C 1, 2, 3, 4

Junction temperature:

Commercial

Industrial

Automotive

TJ0

–40

110

°C 3

Ambient temperature:

Commercial

Industrial

Automotive

TA0

–40

105

°C 3, 5

Peak reflow temperature TPEAK –260°C

Table 13: Thermal Impedance Simulated Values

Die Revision Package Substrate

θ JA (°C/W)

Airflow =

0m/s

θ JA (°C/W)

Airflow =

1m/s

θ JA (°C/W)

Airflow =

2m/s θ JB (°C/W) θ JC (°C/W)

G54-pin

TSOP 2-layer 86.2 67.8 62 46.9 11.3

4-layer 58.9 50.7 47.6 41.5

54-ball

VFBGA 2-layer 72.1 57.3 50.6 36 4.1

4-layer 54.5 46.6 42.8 35.5

60-ball

FBGA 2-layer 70.9 56.8 50.3 36.3 1.9

4-layer 54.6 47.3 43.5 36.3

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Electrical Specifications

Figure 34: Example Temperature Test Point Location, 54-Pin TSOP: Top View

Figure 35: Example Temperature Test Point Location, 54-Ball VFBGA: Top View

Figure 36: Example Temperature Test Point Location, 60-Ball FBGA: Top View

22.22mm

11.11mm

Test point

10.16mm

5.08mm

8.00mm

4.00mm

Test point

4.00mm

8.00mm

Test point

8.00mm

16.00mm

4.00mm

8.00mm

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Electrical Specifications

Table 14: DC Electrical Characteristics and Operating Conditions

Notes: 1, 5, 6; notes appear on page 51; VDD/VDDQ = +3.3 ±0.3V

Parameter/Condition Symbol Min Max Units Notes

Supply voltage VDD/VDDQ3 3.6 V

Input high voltage: Logic 1; All inputs VIH 2VDD + 0.3 V 22

Input low voltage: Logic 0; All inputs VIL –0.3 0.8 V 22

Input leakage current: Any input 0V ≤ VIN ≤ VDD (All other

pins not under test = 0V) II–5 5 µA

Output leakage current: DQ are disabled; 0V ≤ VOUT ≤ VDDQIOZ –5 5 µA

Output levels:

Output high voltage (IOUT = –4mA)

Output low voltage (IOUT = 4mA) VOH 2.4 – V

VOL –0.4V

Table 15: IDD Specifications and Conditions

Notes: 1, 5, 6, 11, 13; notes appear on page 51; VDD/VDDQ = +3.3 ±0.3V

Parameter/Condition Symbol

Max

Units Notes-6A -7E -75

Operating current: Active mode;

Burst = 2; READ or WRITE; tRC = tRC (MIN) IDD1 170 160 150 mA 3, 18 ,

19, 32

Standby current: Power-down mode;

All banks idle; CKE = LOW IDD2222mA32

Standby current: Active mode;

CKE = HIGH; CS# = HIGH; All banks active after tRCD met; No

accesses in progress

IDD3 50 50 50 mA 3, 12,

19, 32

Operating current: Burst mode; Page burst;

READ or WRITE; All banks active IDD4 165 165 150 mA 3, 18 ,

19, 32

Auto refresh current:

CKE = HIGH; CS# = HIGH

tRFC = tRFC (MIN) IDD5 330 330 310 mA 3, 12 ,

18, 19,

32, 33

tRFC = 15.625µs IDD6333mA

tRFC = 3.906µs(AT) IDD6666mA

Self refresh current:

CKE ≤ 0.2V Standard IDD7222mA4

Low power (L) IDD7–11mA

Table 16: Capacitance

Note: 2; notes appear on page 51

Parameter – TSOP “TG” Package Symbol Min Max Units Notes

Input capacitance: CLK CI12.53.5pF 29

Input capacitance: All other input-only pin s CI22.53.8pF 30

Input/output capacitance: DQ CIO 4.0 6.0 pF 31

Parameter – FBGA “FB”

Input capacitance: CLK CI11.53.5pF 34

Input capacitance: All other input-only pin s CI21.53.8pF 35

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Electrical Specifications

Table 17: Electrical Characteristics and Recommended AC Operating Conditions

Notes: 5, 6, 8, 9, 11; notes appear on page 51

AC Characteristics

Symbol

-6A -7E -75

Units NotesParameter Min Max Min Max Min Max

Access time from CLK (positive

edge) CL = 3 tAC(3) – 5.4 5.4 – 5.4 ns 27

CL = 2 tAC(2) – – 5.4 – 6 ns

Address hold time tAH 0.8 – 0.8 – 0.8 – ns

Address setup time tAS 1.5 – 1.5 – 1.5 – ns

CLK high-level width tCH 2.5 – 2.5 – 2.5 – ns

CLK low-level width tCL 2.5 – 2.5 – 2.5 – ns

Clock cycle time CL = 3 tCK(3) 6 – 7 – 7.5 – ns 23

CL = 2 tCK(2) – – 7.5 – 10 – ns 23

CKE hold time tCKH 0.8 – 0.8 – 0.8 – ns

CKE setup time tCKS 1.5 – 1.5 – 1.5 – ns

CS#, RAS#, CAS#, WE#, DQM hold time tCMH 0.8 – 0.8 – 0.8 – ns

CS#, RAS#, CAS#, WE#, DQM setup time tCMS 1.5 – 1.5 – 1.5 – ns

Data-in hold time tDH 0.8 – 0.8 – 0.8 – ns

Data-in setup time tDS 1.5 – 1.5 – 1.5 – ns

Data-out High-Z time CL = 3 tHZ(3) – 5.4 5.4 – 5.4 ns 10

CL = 2 tHZ(2) – – 5.4 – 6 ns 10

Data-out Low-Z time tLZ1–1–1–ns

Data-out hold time (load) tOH3–3–3–ns

Data-out hold time (no load) tOHN 1.8 – 1.8 – 1.8 – ns 28

ACTIVE-to-PRECHARGE command tRAS 42 120,000 37 120,000 44 120,000 ns

ACTIVE-to-ACTIVE command period tRC 60 – 60 – 66 – ns

ACTIVE-to-READ or WRITE delay tRCD18–15–20–ns

Refresh period (4,096 rows) tREF – 64 – 64 – 64 ms

Refresh period - Automotive

(4,096 rows)

tREFAT –16–16–16ms

AUTO REFRESH period tRFC60–66–66–ns

PRECHARGE command period tRP 18 – 15 – 20 – ns

ACTIVE bank a to ACTIVE bank b

command

tRRD12–14–15–ns

Transition time tT 0.3 1.2 0.3 1.2 0.3 1.2 ns 7

WRITE recovery time tWR 1 CLK

+ 7ns –1 CLK

+ 7.5ns ––24

12 – 14 – 15 – ns 25

Exit SELF REFRESH to ACTIVE command tXSR67–67–75–ns20

Table 18: AC Functional Characteristics

Notes: 5, 6, 7, 8, 9, 11; notes appear on page 51

Parameter Symbol -6A -7E -75 Units Notes

READ/WRITE command to READ/WRITE command tCCD111

tCK 17

CKE to clock disable or power-down entry mode tCKED111

tCK 14

CKE to clock enable or power-down exit setup mode tPED 1 1 1 tCK 14

DQM to input data delay tDQD000

tCK 17

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Notes

Notes 1. All voltage s referenced to VSS.

2. This parameter is sampled. VDD, VDDQ = +3.3V; f = 1 MHz, TA = 25°C; pin under test

biased at 1.4V.

3. IDD is dependent on output loading and cycle rates. Specified va lues are obtained

with minimum cycle time and the outputs open.

4. Enables on-chip refresh and address counters.

5. The minimum specifications are used only to indicate cycle time at which proper

operation o v er the full temper atur e rang e (0°C ≤ T A ≤ +70°C (commercial), –40°C ≤ TA ≤

+85°C (industrial), and –40°C ≤ TA ≤ +105°C (automotive) ) is ensured.

6. An initial pause of 100µs is required after power-up , followed by two AUTO REFRESH

commands, before proper device operation is ensured. (VDD and VDDQ must be pow-

ered up simultaneously. VSS and VSSQ must be at same po te ntial.) The two AU TO

REFRESH command wake-ups should be repeated any time the tREF re fresh require-

ment is exceeded.

7. AC characteristics assume tT = 1ns.

8. In addition to meeting the transition rate specification, the clock and CKE must tran-

sit between VIH and VIL (or between VIL and VIH) in a monotonic manner.

9. Outputs measured at 1.5V with equivalent load:

Q50pF

10. tHZ defines the time at which the output achieves the open circuit condition; it is not

a reference to VOH or VOL. The last valid data element will meet tOH before going

High-Z.

11. AC timing and IDD test s have VIL = 0V and VIH = 3V, with timing r eferenced to 1.5V

crossover point. If the input transition time is longer than 1 ns, then the timing is ref-

erenced at VIL (MAX) and VIH (MIN) and no longer at the 1.5V crossover point. CLK

should always be 1.5V referenced to crossover. Refer to Micron technical note

TN-48-09 for more details.

DQM to data mask during WRITEs tDQM000

tCK 17

DQM to data High-Z during READs tDQZ222

tCK 17

WRITE command to input data delay tDWD000

tCK 17

Data-in to ACTIVE command tDAL 5 4 5 tCK 15, 21

Data-in to PRECHARGE command tDPL222

tCK 16, 21

Last data-in to burst STOP command tBDL111

tCK 17

Last data-in to new READ/WRITE command tCDL111

tCK 17

Last data-in to PRECHARGE command tRDL222

tCK 16, 21

LMR command to ACTIVE or REFRESH command tMRD222

tCK 26

Data-out to High-Z from PRECHARGE command CL = 3 tROH(3)333

tCK 17

CL = 2 tROH(2) – 2 2 tCK 17

Table 18: AC Functional Characteristics

Notes: 5, 6, 7, 8, 9, 11; notes appear on page 51

Parameter Symbol -6A -7E -75 Units Notes

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Notes

12. Other input signals are allowed to transition no more than once ev ery 2 clocks and are

otherwise at valid VIH or VIL level s.

13. IDD specifications are tested after the device is properly initialized.

14. Timing actually specified by tCKS; clock(s) spec ifi ed as a reference only at minimum

cycle rate.

15. Timing actually specified by tWR plus tRP; clock(s) specified as a referen ce on ly at

minimum cycle rate.

16. Timing actually specified by tWR.

17. Requir ed clocks ar e specified by JEDEC functionality and are not dependent on any

timing parameter.

18. The IDD current will increase or decrease proportionally according to the amount of

frequency alteration for the test condition.

19. Address transitions average one transition every 2 clocks.

20. CLK must be toggled a minimum of two times during this period.

21. Based on tCK = 7.5ns for -75/-7E, and tCK = 6ns for -6A.

22. VIH overshoot: VIH (MA X) = VDDQ + 2V for a pulse width ≤ 3ns, and the pulse width

cannot be greater than one-thir d of the cycle rate . VIL undershoot: VIL (MIN) = –2V for

a pulse width ≤ 3ns.

23. The clock frequency must remain constant (stable clock is define d as a signal cycling

within timing constraints specified for the clock pin) during access or precharge

states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be

used to reduce the data rate.

24. Auto prechar ge mode only. The precharge timing budget (tRP) begins 6ns for -6A, 7ns

for -7E, and 7.5ns for -75 after the first clock delay, after the last WRITE is executed.

25. Precharge mode only.

26. JEDEC and PC100 specify 3 clocks.

27. tAC for -75/-7E at CL = 3 with no load is 4.6ns and is guaranteed by design.

28. Parameter guaranteed by design.

29. PC100 specifies a maximum of 4pF.

30. PC100 specifies a maximum of 5pF.

31. PC100 specifies a maximum of 6.5pF.

32. Fo r -75, CL = 3 and tCK = 7.5ns; for -7E, CL = 2 and tCK = 7.5ns, and CL = 3 and tCK =

6ns.

33. CK E i s H IGH during refresh co mmand perio d tRFC (MIN) else CKE is LOW. The IDD6

limit is actually a nomina l value and does not result in a fail value.

34. PC133 specifies a minimum of 2.5pF.

35. PC133 specifies a minimum of 2.5pF.

36. PC133 specifies a minimum of 3.0pF.

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128Mb: x4, x8, x16 SDRAM

Timing Diagrams

Figure 37: Initialize and Load Mode Register

Notes: 1. If CS# is HIGH at clo ck HIGH time, all commands applied are NOP.

2. The mode register may be loaded prior to the AUTO REFRESH cycles if desired.

3. JEDEC and PC100 specify 3 clocks.

4. Outputs are guaranteed High-Z after comma nd is issued.

tCH

tCL

tCK

CKE

CLK

COMMAND

BA0, BA1

BANK

tRFC tMRD

tRFC

AUTO REFRESH AUTO REFRESH Program Mode Register 2, 3, 4

tCMH

tCMS

Precharge

all banks

()()

tRP

()()

tCKS

Power-up:

VDD and

CLK stable

T = 100µs

MIN

PRECHARGE NOP AUTO

REFRESH NOP

LOAD MODE

()()

AUTO

REFRESH

ALL

BANKS

()()

High-Z

tCKH

()()

DQM /

DQML, DQMH

()()

()()()()

()()

NOP

()()

tCMH

tCMS tCMH

tCMS

A0–A9, A11

ROW

tAH

tAS

CODE

()()

A10

ROW

tAH

tAS

CODE

()()

ALL BANKS

SINGLE BANK

()()

DON’T CARE

T0 T1 Tn + 1 To + 1 Tp + 1 Tp + 2 Tp + 3

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Timing Diagrams

Figure 38: Power-Down Mode

Notes: 1. Violating refresh requirements during power-down may result in a loss of data.

tCH

tCL

tCK

Two clock cycles

CKE

CLK

All banks idle, enter

power-down mode

Precharge all

active banks

Input buffers gated off while in

power-down mode

Exit power-down mode

()()

DON’T CARE

tCKS tCKS

COMMAND

tCMH

tCMS

PRECHARGE NOP NOP ACTIVENOP

()()

All banks idle

BA0, BA1

BANK

BANK(S)

()()

High-Z

tAH

tAS

tCKH

tCKS

DQM /

DQML, DQMH

()()

A0–A9, A11

ROW

()()

ALL BANKS

SINGLE BANK

A10

ROW

()()

T0 T1 T2 Tn + 1 Tn + 2

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128Mb: x4, x8, x16 SDRAM

Timing Diagrams

Figure 39: Clock Suspend Mode

Notes: 1. For this example, BL = 2, CL = 3, and auto precharge is disabled.

2. x16: A9 and A11 = “Don’t Care.”

x8: A11 = “Don’t Care.”

tCH

tCL

tCK

tAC

tLZ

DQM /

DQML, DQMH

CLK

A0–A9, A11

BA0, BA1

A10

tOH

OUT

tAH

tAS

tAH

tAS

tAH

tAS

BANK

tDH

tAC tHZ

OUT

m + 1

COMMAND

tCMH

tCMS

NOPNOP NOP NOPNOPREAD WRITE

DON’T CARE

UNDEFINED

CKE

tCKS tCKH

BANK

COLUMN m

tDS

e + 1

NOP

tCKH

tCKS

tCMH

tCMS

COLUMN e

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

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128Mb: x4, x8, x16 SDRAM

Timing Diagrams

Figure 40: Auto Refresh Mode

Notes: 1. Each AUTO REFRESH command performs a refresh cycle. Back-to-back commands are not

required.

tCH

tCL

tCK

CKE

CLK

tRFC1

()()

tRP

()()

COMMAND

tCMH

tCMS

NOPNOP

()()

BANK

ACTIVE

AUTO

REFRESH

()()

NOPNOPPRECHARGE

Precharge all

active banks

AUTO

REFRESH

tRFC1

High-Z

BA0, BA1 BANK(S)

()()

tAH

tAS

tCKH

tCKS

()()

NOP

()()

DQM /

DQML, DQMH

A0–A9, A11 ROW

()()

ALL BANKS

SINGLE BANK

A10 ROW

()()

T0 T1 T2 Tn + 1 To + 1

DON’T CARE

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Timing Diagrams

Figure 41: Self Refresh Mode

Notes: 1. No maximum time limit for self refresh. tRAS MAX applies to non-self refresh mode.

2. tXSR requires minimum of 2 clocks regardless of frequency or timing.

3. Self refresh mode not supported on automotive temperature (AT) devices.

tCH

tCL

tCK

tRP

CKE

CLK

Enter self refresh mode

Precharge all

active banks

tXSR

CLK stable prior to exiting

self refresh mode

Exit self refresh mode

(Restart refresh time base)

()()()()

()()

DON’T CARE

COMMAND

tCMH

tCMS

AUTO

REFRESH

PRECHARGE NOP NOP or COMMAND

INHIBIT

()()

BA0, BA1 BANK(S)

()()

High-Z

tCKS

AUTO

REFRESH

tRAS min1

()()

tCKH

tCKS

()()

A0–A9, A11

()()

ALL BANKS

SINGLE BANK

A10

()()

T0 T1 T2

≥

Tn + 1 To + 1 To + 2

()()

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Timing Diagrams

Figure 42: READ – Without Auto Precharge

Notes: 1. For this example, BL = 4, CL = 2, and the READ burst is followed by a “manual” PRECHARGE.

2. x16: A9 and A11 = “Don’t Care.”

x8: A11 = “Don’t Care.”

ALL BANKS

tCH

tCL

tCK

tAC

tLZ

tRP

tRAS

tRCD CAS Latency

tRC

tOH

OUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

BANK BANK(S) BANK

ROW

BANK

tHZ

tOH

DOUT m+3

tAC tOH

tAC

DOUT m+2DOUT m+1

tCMH

tCMS

PRECHARGE

NOPNOP NOPACTIVE NOP READ NOP ACTIVE

DISABLE AUTO PRECHARGE SINGLE BANKS

DON’T CARE

UNDEFINED

COLUMN m

tCKH

tCKS

T0 T1 T2 T3 T4 T5 T6 T7 T8

DQM /

DQML, DQMH

CKE

CLK

A0–A9, A11

BA0, BA1

A10

COMMAND

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Timing Diagrams

Figure 43: READ – With Auto Precharge

Notes: 1. For this example, BL = 4, and CL = 2.

2. x16: A9 and A11 = “Don’t Care.”

x8: A11 = “Don’t Care.”

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tAC

tLZ

tRP

tRAS

tRCD CAS Latency

tRC

DQM /

DQML, DQMH

CKE

CLK

A0–A9, A11

BA0, BA1

A10

tOH

DOUT m

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

BANK BANK

ROW

BANK

DON’T CARE

UNDEFINED

tHZ

tOH

OUT

+ 3

tAC tOH

tAC

OUT

+ 2D

OUT

+ 1

COMMAND

tCMH

tCMS

NOPNOP NOPACTIVE NOP READ NOP ACTIVENOP

tCKH

tCKS

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8

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Timing Diagrams

Figure 44: Single READ – Without Auto Precharge

Notes: 1. For this example, BL = 1, CL = 2, and the READ burst is followed by a “manual” PRECHARGE.

2. x16: A9 and A11 = “Don’t Care.”

x8: A11 = “Don’t Care.”

3. PRECHARGE command not allowed or tRAS would be violated.

ALL BANKS

tCH

tCL

tCK

tAC

tLZ

tRP

tRAS

tRCD CAS Latency

tRC

tOH

OUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

BANK BANK(S) BANK

ROW

BANK

tHZ

tCMH

tCMS

NOP

NOPNOP PRECHARGE

ACTIVE NOP READ ACTIVE NOP

DISABLE AUTO PRECHARGE SINGLE BANKS

DON’T CARE

UNDEFINED

COLUMN m2

tCKH

tCKS

T0 T1 T2 T3 T4 T5 T6 T7 T8

DQM /

DQML, DQMH

CKE

CLK

A0–A9, A11

BA0, BA1

A10

COMMAND

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Timing Diagrams

Figure 45: Single READ – With

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tRP

tRAS

tRCD CAS Latency

tRC

DQM /

DQML, DQMU

CKE

CLK

A0–A9, A11

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

BANK BANK

ROW

BANK

DON’T CARE

UNDEFINED

tHZ

tOH

OUT

tAC

COMMAND

tCMH

tCMS

NOP2READACTIVE NOP NOP2ACTIVENOP

tCKH

tCKS

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8

NOP NOP

Auto Precharge

Notes: 1. For this example, BL = 1, and CL = 2.

2. x16: A9 and A11 = “Don’t Care.”

x8: A11 = “Don’t Care.”

3. READ command not allowed or tRAS would be violated.

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Timing Diagrams

Figure 46: Alternating Bank Read Accesses

Notes: 1. For this example, BL = 4, and CL = 2.

2. x16: A9 and A11 = “Don’t Care.”

x8: A11 = “Don’t Care.”

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tAC

tLZ

DQM /

DQML, DQMH

CLK

A0–A9, A11

BA0, BA1

A10

tOH

OUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

DON’T CARE

UNDEFINED

tOH

DOUT m + 3

tAC tOH

tAC

DOUT m + 2DOUT m + 1

COMMAND

tCMH

tCMS

NOP NOPACTIVE NOP READ NOP ACTIVE

tOH

OUT

tAC tAC

READ

ENABLE AUTO PRECHARGE

ROW

ACTIVE

ROW

BANK 0 BANK 0 BANK 3 BANK 3 BANK 0

CKE

tCKH

tCKS

COLUMN m

COLUMN b

T0 T1 T2 T4T3 T5 T6 T7 T8

tRP - BANK 0

tRAS - BANK 0

tRCD - BANK 0 tRCD - BANK 0

CAS Latency - BANK 0

tRCD - BANK 3 CAS Latency - BANK 3

tRC - BANK 0

RRD

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Timing Diagrams

Figure 47: READ – Full-Page Burst

Notes: 1. For this example, CL = 2.

2. x16: A9 and A11 = “Don’t Care.”

x8: A11 = “Don’t Care.”

3. Page left open; no tRP.

tCH

tCL tCK

tAC

tLZ

tRCD CAS Latency

DQM /

DQML, DQMH

CKE

CLK

A0–A9, A11

BA0, BA1

A10

tOH

OUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAC tOH

OUT

m+1

ROW

tHZ

tAC tOH

OUT

m+1

tAC tOH

OUT

m+2

tAC tOH

OUT

m-1

tAC tOH

OUT

Full-page burst does not self-terminate.

Can use BURST TERMINATE command.

()()

Full page completed

512 (x16) locations within same row

1,024 (x8) locations within same row

2,048 (x4) locations within same row

DON’T CARE

UNDEFINED

COMMAND

tCMH

tCMS

NOPNOP NOPACTIVE NOP READ NOP BURST TERMNOP NOP

()()

NOP

()()

tAH

tAS

BANK

()()

BANK

tCKH

tCKS

()()

COLUMN m

T0 T1 T2 T4T3 T5 T6 Tn + 1 Tn + 2 Tn + 3 Tn + 4

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Timing Diagrams

Figure 48: READ – DQM Operation

Notes: 1. For this example, BL = 4, and CL = 2.

2. x16: A9 and A11 = “Don’t Care.”

x8: A11 = “Don’t Care.”

tCH

tCL

tCK

tRCD CAS Latency

DQM /

DQML, DQMH

CKE

CLK

A0–A9, A11

BA0, BA1

A10

tCMS

ROW

BANK

ROW

BANK

tAC

DOUT m

tOH

DOUT m + 3DOUT m + 2

ttHZ LZ

tCMH

COMMAND

NOPNOP NOPACTIVE NOP READ NOPNOP NOP

tHZ

tAC tOH

tAH

tAS

tCMS tCMH

tAH

tAS

tAH

tAS

tCKH

tCKS

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8

DON’T CARE

UNDEFINED

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Timing Diagrams

Figure 49: WRITE – Without Auto Precharge

Notes: 1. For this example, BL = 4, and the WRITE burst is followed by a “manual” PRECHARGE.

2. 15ns is required between <DIN m + 3> and the PRECHARGE command, regardless of fre-

quency.

3. x16: A9 and A11 = “Don’t Care.”

x8: A11 = “Don’t Care.”

DISABLE AUTO PRECHARGE

ALL BANKS

tCH

tCL

tCK

tRP

tRAS

tRCD

tRC

DQM /

DQML, DQMH

CKE

CLK

A0–A9, A11

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

ROW

BANK BANK BANK

ROW

BANK

tWR

tDH

tDS

m + 1 D

m + 2 D

m + 3

COMMAND

tCMH

tCMS

NOPNOP NOPACTIVE NOP WRITE NOPPRECHARGE ACTIVE

tAH

tAS

tAH

tAS

tDH

tDS tDH

tDS

SINGLE BANK

tCKH

tCKS

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8

DON’T CARE

NOP

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Timing Diagrams

Figure 50: WRITE – With Auto Precharge

Notes: 1. For this example, BL = 4.

2. x16: A9 and A11 = “Don’t Care.”

x8: A11 = “Don’t Care.”

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tRP

tRAS

tRCD

tRC

DQM /

DQML, DQMH

CKE

CLK

A0–A9, A11

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

ROW

BANK BANK

ROW

BANK

tWR

tDH

tDS

m + 1 D

m + 2 D

m + 3

COMMAND

tCMH

tCMS

NOPNOP NOPACTIVE NOP WRITE NOP ACTIVE

tAH

tAS

tAH

tAS

tDH

tDS tDH

tDS

tCKH

tCKS

NOP NOP

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8 T9

DON’T CARE

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Timing Diagrams

Figure 51: Single WRITE – Without Auto Precharge

Notes: 1. For this example, BL = 1, and the WRITE burst is followed by a “manual” PRECHARGE.

2. 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.

3. x16: A9 and A11 = “Don’t Care.”

x8: A11 = “Don’t Care.”

DISABLE AUTO PRECHARGE

ALL BANKS

tCH

tCL

tCK

tRP

tRAS

tRCD

tRC

DQM /

DQML, DQMU

CKE

CLK

A0–A9, A11

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

ROW

BANK BANK BANK

ROW

BANK

tWR

tDH

tDS

COMMAND

tCMH

tCMS

NOP2

NOP2PRECHARGEACTIVE NOP WRITE ACTIVENOP NOP

tAH

tAS

tAH

tAS

SINGLE BANK

tCKH

tCKS

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8

DON’T CARE

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Timing Diagrams

Figure 52: Single WRITE – With Auto Precharge

Notes: 1. For this example, BL = 1.

2. x16: A9 and A11 = “Don’t Care.”

x8: A11 = “Don’t Care.”

3. Write command not allowed or tRAS would be violate d.

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tRP

tRAS

tRCD

tRC

DQM /

DQML, DQMH

CKE

CLK

A0–A9, A11

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

ROW

BANK BANK

ROW

BANK

tWR

COMMAND

tCMH

tCMS

NOP3NOP3NOPACTIVE NOP3WRITE NOP

ACTIVE

tAH

tAS

tAH

tAS

tDH

tDS

tCKH

tCKS

NOP NOP

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8 T9

DON’T CARE

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Timing Diagrams

Figure 53: Alternating Bank Write Accesses

Notes: 1. For this example, BL = 4.

2. x16: A9 and A11 = “Don’t Care.”

x8: A11 = “Don’t Care.”

DON’T CARE

tCH

tCL

tCK

CLK

tDH

tDS

m + 1 D

m + 2 D

m + 3

COMMAND

tCMH

tCMS

NOP

ACTIVE NOP WRITE

NOP NOP ACTIVE

tDH

tDS tDH

tDS

ACTIVE WRITE

tDH

tDS

b + 1 D

b + 3

tDH

tDS tDH

tDS

ENABLE AUTO PRECHARGE

DQM /

DQML, DQMH

A0–A9, A11

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

ENABLE AUTO PRECHARGE

ROW

BANK 0 BANK 0 BANK 1

BANK 0

BANK 1

CKE

tCKH

tCKS

b + 2

tDH

tDS

COLUMN b

COLUMN m

tRP - BANK 0

tRAS - BANK 0

tRCD - BANK 0 t

RCD - BANK 0

tWR - BANK 0

WR - BANK 1

tRCD - BANK 1

tRC - BANK 0

RRD

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

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Timing Diagrams

Figure 54: WRITE – Full-Page Burst

Notes: 1. x16: A9 and A11 = “Don’t Care.”

x8: A11 = “Don’t Care.”

2. tWR must be sati sf ied prior to PRECHARGE command.

3. Page left open; no tRP.

tCH

tCL tCK

tRCD

DQM /

DQML, DQMH

CKE

CLK

A0–A9, A11

BA0, BA1

A10

tCMS

tAH

tAS

tAH

tAS

ROW

Full-page burst does not

self-terminate. Can use

BURST TERMINATE

command to stop.

2, 3

()()

Full page completed

DON’T CARE

COMMAND

tCMH

tCMS

NOPNOP NOPACTIVE NOP WRITE BURST TERMNOP NOP

()()

tDH

tDS

m + 1 D

m + 2 D

m + 3

tDH

tDS tDH

tDS

m - 1

tDH

tDS

tAH

tAS

BANK

()()

BANK

tCMH

tCKH

tCKS

()()

512 (x16) locations within same row

1,024 (x8) locations within same row

2,048 (x4) locations within same row

COLUMN m

T0 T1 T2 T3 T4 T5 Tn + 1 Tn + 2 Tn + 3

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Timing Diagrams

Figure 55: WRITE – DQM Operation

Notes: 1. For this example, BL = 4.

2. x16: A9 and A11 = “Don’t Care.”

x8: A11 = “Don’t Care.”

DON’T CARE

tCH

tCL

tCK

tRCD

DQM /

DQML, DQMH

CKE

CLK

A0–A9, A11

BA0, BA1

A10

tCMS

tAH

tAS

ROW

BANK

ROW

BANK

ENABLE AUTO PRECHARGE

m + 3

tDH

tDS

m + 2

tCMH

COMMAND NOPNOP NOPACTIVE NOP WRITE NOPNOP

tCMS tCMH

tDH

tDS

tDH

tDS

tAH

tAS

tAH

tAS

DISABLE AUTO PRECHARGE

tCKH

tCKS

COLUMN m

T0 T1 T2 T3 T4 T5 T6 T7

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Package Dimensions

Figure 56: 54-Pin Plastic TSOP (400 mil)

Notes: 1. All dimensions in millimeters.

2. Package width and length do not include mold protrusion; allowable mol d protru sio n is

0.25mm per side.

3. “2X” means the notch is present in two locations (both ends of the device).

SEE DETAIL A

0.10 +0.10

-0.05

0.15 +0.03

-0.02

2X R 1.00

2X R 0.75

0.80 TYP

(FOR REFERENCE

ONLY)

2X 0.71

0.50 ±0.10

PIN #1 ID

DETAIL A

22.22 ±.08

10.16 ±0.08

11.76 ±0.20

0.375 ±0.075 TYP

1.2 MAX

0.25

0.80

2X 0.10

2.80 GAGE PLANE

PLATED LEAD FINISH: 90% Sn, 10% Pb OR 100%Sn

PLASTIC PACKAGE MATERIAL: EPOXY NOVOLAC

PACKAGE WIDTH AND LENGTH DO NOT

INCLUDE MOLD PROTRUSION. ALLOWABLE

PROTRUSION IS 0.25 PER SIDE.

0.10

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Package Dimensions

Figure 57: 60-Ball FBGA “FB/BB” Package (x8 device), 8mm x 16mm

Notes: 1. All dimensions in millimeters.

2. Recommended pa d size for PCB is 0.33mm ±0.025mm.

3. Topside part marking decoder can be found at http://www.micron.com/decoder.

BALL #1 ID

SUBSTRATE:

PLASTIC LAMINATE

ENCAPSULATION MATERIAL:

EPOXY NOVOLAC

SOLDER BALL MATERIAL:

62% Sn, 36% Pb, 2% Ag OR

96.5% Sn. 3% Ag, 0.5% Cu

SEATING PLANE

0.850 ±0.05

0.155 ±0.013

0.10 A

0.80

TYP

16.00 ±0.10

11.20

1.20 MAX

5.60

8.00 ±0.05

BALL #1 ID

BALL A1

BALL

0.80

TYP

4.00 ±0.05

2.80

2.40 ±0.05

CTR

8.00 ±0.10

5.60

60X Ø 0.45

DIMENSIONS APPLY

TO SOLDER BALLS

POST REFLOW. PRE-

REFLOW DIAMETER

IS 0.42 ON A 0.33 NSMD

BALL PAD.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

prodmktg@micron.com www.micron.com Customer Comment Line: 800-932- 4992

Micron, the M logo, and the Micron logo are trademarks of Micron Technology , Inc. All other trademarks ar e the property of

their respective owners.

This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range

set forth herein. Although consider ed final, th es e specifications ar e subject to ch ange, as further product development and

data characterization sometimes occur.

128Mb: x4, x8, x16 SDRAM

Package Dimensions

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Figure 58: 54-Ball VFBGA “F4/B4” Package (x16 device), 8mm x 8mm

Notes: 1. All dimensions in millimeters.

2. Recommended pad size for PCB is 0.40mm SMD.

3. Topside part marking decoder can be found at http://www.micron.com/decoder.

BALL A1 ID

0.65 ±0.05

SEATING PLANE

0.10 C

1.00 MAX

BALL A9

0.80

TYP

0.80 TYP

3.20

6.40

8.00 ±0.10

4.00 ±0.05

SOLDER BALL

DIAMETER REFERS

TO POST REFLOW

CONDITION. THE PRE-

REFLOW DIAMETER

IS 0.42.

54X Ø0.45 ±0.05

SOLDER BALL MATERIAL:

62% Sn, 36% Pb, 2% Ag OR

96.5% Sn, 3% Ag, 0.5% Cu

SOLDER MASK DEFINED BALL PADS:

Ø0.40

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE MATERIAL: PLASTIC LAMINATE

6.40

3.20

4.00 ±0.05

8.00 ±0.10

BALL A1 ID

BALL A1