APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 4Gb DDR3 SDRAM 4Gb DDR3 SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TQ4G43BMR-xxC H5TQ4G83BMR-xxC * Hynix Semiconductor reserves the right to change products or specifications without notice. Rev. 0.2 / Jun. 2010 *182fd049-db40* 1 B48614/178.104.2.80/2010-06-08 13:31 APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 Revision History Revision No. History Draft Date 0.1 Initial Release Apr. 2010 0.2 Corrected typo on row and column address table Jun. 2010 Rev. 0.2 / Jun. 2010 *182fd049-db40* Remark 2 B48614/178.104.2.80/2010-06-08 13:31 APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 Description The H5TQ4G43BMR-xxC, H5TQ4G83BMR-xxC are a 4,294,967,296-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. Hynix 2Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth. Device Features and Ordering Information FEATURES * VDD=VDDQ=1.5V +/- 0.075V * 8banks * Fully differential clock inputs (CK, CK) operation * Average Refresh Cycle (Tcase of 0 oC~ 95 oC) * Differential Data Strobe (DQS, DQS) - 7.8 s at 0oC ~ 85 oC - 3.9 s at 85oC ~ 95 oC * On chip DLL align DQ, DQS and DQS transition with CK transition * Auto Self Refresh supported * DM masks write data-in at the both rising and falling edges of the data strobe * JEDEC standard 82ball FBGA(x4/x8) * All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock * Dynamic On Die Termination supported * Driver strength selected by EMRS * Asynchronous RESET pin supported * Programmable CAS latency 6, 7, 8, 9, 10 and (11) supported * ZQ calibration supported * Programmable additive latency 0, CL-1, and CL-2 supported * Write Levelization supported * TDQS (Termination Data Strobe) supported (x8 only) * Programmable CAS Write latency (CWL) = 5, 6, 7, 8 * Programmable burst length 4/8 with both nibble sequential and interleave mode * 8 bit pre-fetch * BL switch on the fly * This product in compliance with the RoHS directive. Rev. 0.2 / Jun. 2010 *182fd049-db40* 3 B48614/178.104.2.80/2010-06-08 13:32 APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 ORDERING INFORMATION Part No. Configuration H5TQ4G43BMR-*xxC 1G x 4 H5TQ4G83BMR-*xxC 512M x 8 Package 82ball FBGA OPERATING FREQUENCY Speed Grade (Marking) Frequency [MHz] CL5 CL6 CL7 CL8 CL9 CL10 -G7 O O O -H9 O O O O O -PB O O O O O CL11 CL12 CL13 Remark (CL-tRCD-tRP) DDR3-1066 7-7-7 O O O DDR3-1333 9-9-9 O DDR3-1600 11-11-11 * xx means Speed Bin Grade Rev. 0.2 / Jun. 2010 *182fd049-db40* 4 B48614/178.104.2.80/2010-06-08 13:32 APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 Package Ballout/Mechanical Dimension x4 Package Ball out (Top view): 82ball FBGA Package A 1 2 NC 3 4 5 6 7 8 9 10 11 NC VSS VDD NC NF VSS VDD B VSS VSSQ DQ0 DM VSSQ VDDQ B C VDDQ DQ2 DQS DQ1 DQ3 VSSQ C D VSSQ NF DQS VDD VSS VSSQ D E VREFDQ VDDQ NF NF NF VDDQ E F ODT1 VSS RAS CK VSS CKE1 F G ODT0 VDD CAS CK VDD CKE0 G H CS1 CS0 WE A10/AP ZQ0 ZQ1 H J VSS BA0 BA2 NC VREFCA VSS J K VDD A3 A0 A12/BC BA1 VDD K L VSS A5 A2 A1 A4 VSS L M VDD A7 A9 A11 A6 VDD M NC VSS RESET A13 A14 A8 VSS NC 1 2 3 4 8 9 10 11 N 5 6 7 A N Note: NF (No Function) - This is applied to balls only used in x4 configuration. 1 2 3 4 8 9 10 11 A B C D E F G H J K (Top View: See the balls through the Package) Populated ball Ball not populated L M N Rev. 0.2 / Jun. 2010 *182fd049-db40* 5 B48614/178.104.2.80/2010-06-08 13:32 APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 x8 Package Ball out (Top view): 82ball FBGA Package A 1 2 NC 3 4 5 6 7 8 9 10 11 NC VSS VDD NC NF/TDQS VSS VDD B VSS VSSQ DQ0 DM/TDQS VSSQ VDDQ B C VDDQ DQ2 DQS DQ1 DQ3 VSSQ C D VSSQ DQ6 DQS VDD VSS VSSQ D E VREFDQ VDDQ DQ4 DQ7 DQ5 VDDQ E F ODT1 VSS RAS CK VSS CKE1 F G ODT0 VDD CAS CK VDD CKE0 G H CS1 CS0 WE A10/AP ZQ0 ZQ1 H J VSS BA0 BA2 NC VREFCA VSS J K VDD A3 A0 A12/BC BA1 VDD K L VSS A5 A2 A1 A4 VSS L M VDD A7 A9 A11 A6 VDD M NC VSS RESET A13 A14 A8 VSS NC 1 2 3 4 8 9 10 11 N 1 2 3 4 5 6 7 A N 8 9 10 11 A B C D E F G H J K (Top View: See the balls through the Package) Populated ball Ball not populated L M N Rev. 0.2 / Jun. 2010 *182fd049-db40* 6 B48614/178.104.2.80/2010-06-08 13:32 APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 Pin Functional Description Symbol Type Function CK, CK Input Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. CKE, (CKE0), (CKE1) Input Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is asynchronous for Self-Refresh exit. After VREFCA and VREFDQ have become stable during the power on and initialization sequence, they must be maintained during all operations (including Self-Refresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE, are disabled during powerdown. Input buffers, excluding CKE, are disabled during Self-Refresh. CS, (CS0), (CS1), (CS2), (CS3) Input Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on systems with multiple Ranks. CS is considered part of the command code. ODT, (ODT0), (ODT1) Input On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS, NU/TDQS (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x4/x8 configurations. For x16 configuration, ODT is applied to each DQ, DQSU, DQSU, DQSL, DQSL, DMU, and DML signal. The ODT pin will be ignored if MR1 is programmed to disable ODT. RAS. CAS. WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. DM, (DMU), (DML) Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS. For x8 device, the function of DM or TDQS/TDQS is enabled by Mode Register A11 setting in MR1. BA0 - BA2 Input Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines if the mode register or extended mode register is to be accessed during a MRS cycle. Input Address Inputs: Provide the row address for Active commands and the column address for Read/Write commands to select one location out of the memory array in the respective bank. (A10/AP and A12/BC have additional functions, see below). The address inputs also provide the op-code during Mode Register Set commands. A10 / AP Input Auto-precharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH: Autoprecharge; LOW: no Autoprecharge).A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses. A12 / BC Input Burst Chop: A12 / BC is sampled during Read and Write commands to determine if burst chop (on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped). See command truth table for details. A0 - A15 Rev. 0.2 / Jun. 2010 *182fd049-db40* 7 B48614/178.104.2.80/2010-06-08 13:32 APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 Symbol Type Function Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when RESET is HIGH. RESET must be HIGH during normal operation. RESET is a CMOS rail-to-rail signal with DC high and low at 80% and 20% of VDD, i.e. 1.20V for DC high and 0.30V for DC low. RESET Input DQ Input / Output Data Input/ Output: Bi-directional data bus. Input / Output Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. The data strobe DQS, DQSL, and DQSU are paired with differential signals DQS, DQSL, and DQSU, respectively, to provide differential pair signaling to the system during reads and writes. DDR3 SDRAM supports differential data strobe only and does not support single-ended. Output Termination Data Strobe: TDQS/TDQS is applicable for x8 DRAMs only. When enabled via Mode Register A11 = 1 in MR1, the DRAM will enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When disabled via mode register A11 = 0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. x4/x16 DRAMs must disable the TDQS function via mode register A11 = 0 in MR1. DQU, DQL, DQS, DQS, DQSU, DQSU, DQSL, DQSL TDQS, TDQS NC No Connect: No internal electrical connection is present. NF No Function VDDQ Supply DQ Power Supply: 1.5 V +/- 0.075 V VSSQ Supply DQ Ground VDD Supply Power Supply: 1.5 V +/- 0.075 V VSS Supply Ground VREFDQ Supply Reference voltage for DQ VREFCA Supply Reference voltage for CA ZQ Supply Reference Pin for ZQ calibration Note: Input only pins (BA0-BA2, A0-A15, RAS, CAS, WE, CS, CKE, ODT, DM, and RESET) do not supply termination. Rev. 0.2 / Jun. 2010 *182fd049-db40* 8 B48614/178.104.2.80/2010-06-08 13:32 APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 ROW AND COLUMN ADDRESS TABLE 4Gb (2Gbx2) Configuration # of Banks Bank Address Auto precharge BL switch on the fly Row Address Column Address Page size 1 512Mb x 4 256Mb x 8 8 BA0 - BA2 A10/AP A12/BC A0 - A14 A0 - A9,A11 1 KB 8 BA0 - BA2 A10/AP A12/BC A0 - A14 A0 - A9 1 KB Note1: Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered. Page size is per bank, calculated as follows: page size = 2 COLBITS * ORG 8 where COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits Rev. 0.2 / Jun. 2010 *182fd049-db40* 9 B48614/178.104.2.80/2010-06-08 13:32 APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 Absolute Maximum Ratings Absolute Maximum DC Ratings Absolute Maximum DC Ratings Symbol VDD VDDQ Parameter Rating Units Notes Voltage on VDD pin relative to Vss - 0.4 V ~ 1.975 V V 1,3 Voltage on VDDQ pin relative to Vss - 0.4 V ~ 1.975 V V 1,3 - 0.4 V ~ 1.975 V V 1 -55 to +100 oC 1, 2 VIN, VOUT Voltage on any pin relative to Vss TSTG Storage Temperature Notes: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than 0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV. DRAM Component Operating Temperature Range Temperature Range Symbol TOPER Parameter Normal Operating Temperature Range Extended Temperature Range (Optional) Rating Units Notes 0 to 85 oC 1,2 85 to 95 oC 1,3 Notes: 1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions. 3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 s. It is also possible to specify a component with 1X refresh (tREFI to 7.8s) in the Extended Temperature Range. Please refer to the DIMM SPD for option availability b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b). Rev. 0.2 / Jun. 2010 *182fd049-db40* 10 B48614/178.104.2.80/2010-06-08 13:32 APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 AC & DC Operating Conditions Recommended DC Operating Conditions Recommended DC Operating Conditions Symbol VDD VDDQ Parameter Rating Units Notes 1.575 V 1,2 1.575 V 1,2 Min. Typ. Max. Supply Voltage 1.425 1.500 Supply Voltage for Output 1.425 1.500 Notes: 1. Under all conditions, VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. Rev. 0.2 / Jun. 2010 *182fd049-db40* 11 B48614/178.104.2.80/2010-06-08 13:32 APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 IDD and IDDQ Specification Parameters and Test Conditions IDD and IDDQ Measurement Conditions In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure 1. shows the setup and test load for IDD and IDDQ measurements. * IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and IDD7) are measured as time-averaged currents with all VDD balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD currents. * IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ currents. Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one merged-power layer in Module PCB. For IDD and IDDQ measurements, the following definitions apply: * "0" and "LOW" is defined as VIN <= VILAC(max). * "1" and "HIGH" is defined as VIN >= VIHAC(max). * "MID_LEVEL" is defined as inputs are VREF = VDD/2. * Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1. * Basic IDD and IDDQ Measurement Conditions are described in Table 2. * Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 10. * IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting RON = RZQ/7 (34 Ohm in MR1); Qoff = 0B (Output Buffer enabled in MR1); RTT_Nom = RZQ/6 (40 Ohm in MR1); RTT_Wr = RZQ/2 (120 Ohm in MR2); TDQS Feature disabled in MR1 * Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started. * Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW} * Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH} Rev. 0.2 / Jun. 2010 *182fd049-db40* 12 B48614/178.104.2.80/2010-06-08 13:32 APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 IDDQ (optional) IDD VDD VDDQ RESET CK/CK DDR3 SDRAM CKE CS RAS, CAS, WE DQS, DQS DQ, DM, TDQS, TDQS A, BA ODT ZQ VSS RTT = 25 Ohm VDDQ/2 VSSQ Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements [Note: DIMM level Output test load condition may be different from above] Application specific memory channel environment IDDQ Test Load Channel IO Power Simulation IDDQ Simulation IDDQ Simulation Correction Channel IO Power Number Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement Rev. 0.2 / Jun. 2010 *182fd049-db40* 13 B48614/178.104.2.80/2010-06-08 13:32 APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns Symbol tCK DDR3-1066 DDR3-1333 DDR3-1600 7-7-7 9-9-9 11-11-11 1.875 1.5 1.25 Unit ns CL 7 9 11 nCK nRCD 7 9 11 nCK nRC 27 33 39 nCK nRAS 20 24 28 nCK nRP 7 9 11 nCK 1KB page size 20 20 24 nCK 2KB page size 27 30 32 nCK 1KB page size 4 4 5 nCK nFAW nRRD 6 5 6 nCK nRFC -512Mb 2KB page size 48 60 72 nCK nRFC-1 Gb 59 74 88 nCK nRFC- 2 Gb 86 107 128 nCK nRFC- 4 Gb 160 200 240 nCK nRFC- 8 Gb 187 234 280 nCK Table 2 -Basic IDD and IDDQ Measurement Conditions Symbol Description Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT IDD0 and PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 3. Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8a); AL: 0; CS: High between IDD1 ACT, RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to Table 4; DM: stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 4. Rev. 0.2 / Jun. 2010 *182fd049-db40* 14 B48614/178.104.2.80/2010-06-08 13:32 APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 Symbol Description Precharge Standby Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, IDD2N Bank Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 5. Precharge Standby ODT Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, IDD2NT Bank Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: toggling according to Table 6; Pattern Details: see Table 6. Precharge Power-Down Current Slow Exit CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, IDD2P0 Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exitc) Precharge Power-Down Current Fast Exit CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, IDD2P1 Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exitc) Precharge Quiet Standby Current IDD2Q CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0 Active Standby Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, IDD3N Bank Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 5. Rev. 0.2 / Jun. 2010 *182fd049-db40* 15 B48614/178.104.2.80/2010-06-08 13:32 APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 Symbol Description Active Power-Down Current IDD3P CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0 Operating Burst Read Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between RD; Command, IDD4R Address, Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst with different data between one burst and the next one according to Table 7; DM: stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 7. Operating Burst Write Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between WR; Command, IDD4W Address, Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst with different data between one burst and the next one according to Table 8; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at HIGH; Pattern Details: see Table 8. Burst Refresh Current CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8a); AL: 0; CS: High between REF; Com- IDD5B mand, Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: REF command every nREF (see Table 9); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 9. Self-Refresh Current: Normal Temperature Range TCASE: 0 - 85 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Normale); IDD6 CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL Self-Refresh Current: Extended Temperature Range (optional)f) TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): ExtendIDD6ET ede); CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL Rev. 0.2 / Jun. 2010 *182fd049-db40* 16 B48614/178.104.2.80/2010-06-08 13:32 APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 Symbol Description Auto Self-Refresh Current (optional)f) TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Enabledd);Self-Refresh Temperature Range (SRT): Normale); IDD6TC CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Auto Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL Operating Bank Interleave Read Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8a), f); AL: CL1; CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling accord- IDD7 ing to Table 10; Data IO: read data burst with different data between one burst and the next one according to Table 10; DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...7) with different addressing, wee Table 10; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 10. a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature range f) Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B Rev. 0.2 / Jun. 2010 *182fd049-db40* 17 B48614/178.104.2.80/2010-06-08 13:32 APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 ACT 0 0 1 1 0 0 00 0 0 0 0 - 1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 - D, D 1 1 1 1 0 0 00 0 0 0 0 - 0 0 0 - 0 F 0 - Cycle Number Datab) Sub-Loop CKE CK, CK Table 3 - IDD0 Measurement-Loop Patterna) 0 3,4 ... nRAS Static High toggling ... repeat pattern 1...4 until nRAS - 1, truncate if necessary PRE 0 0 1 0 0 0 00 0 repeat pattern 1...4 until nRC - 1, truncate if necessary 1*nRC+0 ACT 1*nRC+1, 2 D, D 1 0 0 0 0 0 00 0 0 F 0 - 1*nRC+3, 4 D, D 1 1 1 1 0 0 00 0 0 F 0 - 0 - ... 1*nRC+nRAS 0 0 1 1 0 0 00 0 repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary PRE 0 0 1 0 0 0 00 0 0 ... repeat pattern 1...4 until 2*nRC - 1, truncate if necessary 1 2*nRC repeat Sub-Loop 0, use BA[2:0] = 1 instead 2 4*nRC repeat Sub-Loop 0, use BA[2:0] = 2 instead 3 6*nRC repeat Sub-Loop 0, use BA[2:0] = 3 instead 4 8*nRC repeat Sub-Loop 0, use BA[2:0] = 4 instead 5 10*nRC repeat Sub-Loop 0, use BA[2:0] = 5 instead 6 12*nRC repeat Sub-Loop 0, use BA[2:0] = 6 instead 7 14*nRC repeat Sub-Loop 0, use BA[2:0] = 7 instead F a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. b) DQ signals are MID-LEVEL. Rev. 0.2 / Jun. 2010 *182fd049-db40* 18 B48614/178.104.2.80/2010-06-08 13:32 APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 ACT 0 0 1 1 0 0 00 0 0 0 0 - 1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 - D, D 1 1 1 1 0 0 00 0 0 0 0 - 0 0 00000000 0 0 0 - Cycle Number Datab) Sub-Loop CKE CK, CK Table 4 - IDD1 Measurement-Loop Patterna) 0 3,4 ... nRCD ... nRAS Static High toggling ... repeat pattern 1...4 until nRCD - 1, truncate if necessary RD 0 1 0 1 0 0 00 0 0 repeat pattern 1...4 until nRAS - 1, truncate if necessary PRE 0 0 1 0 0 0 00 0 repeat pattern 1...4 until nRC - 1, truncate if necessary 1*nRC+0 ACT 0 0 1 1 0 0 00 0 0 F 0 - 1*nRC+1,2 D, D 1 0 0 0 0 0 00 0 0 F 0 - D, D 1 1 1 1 0 0 00 0 0 F 0 - 1*nRC+3,4 ... 1*nRC+nRCD ... 1*nRC+nRAS repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary RD 0 1 0 1 0 0 00 0 0 F 0 00110011 repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary PRE 0 0 1 0 0 0 00 0 0 F ... repeat pattern nRC + 1,...4 until *2 nRC - 1, truncate if necessary 1 2*nRC repeat Sub-Loop 0, use BA[2:0] = 1 instead 2 4*nRC repeat Sub-Loop 0, use BA[2:0] = 2 instead 3 6*nRC repeat Sub-Loop 0, use BA[2:0] = 3 instead 4 8*nRC repeat Sub-Loop 0, use BA[2:0] = 4 instead 5 10*nRC repeat Sub-Loop 0, use BA[2:0] = 5 instead 6 12*nRC repeat Sub-Loop 0, use BA[2:0] = 6 instead 7 14*nRC repeat Sub-Loop 0, use BA[2:0] = 7 instead 0 - a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID_LEVEL. Rev. 0.2 / Jun. 2010 *182fd049-db40* 19 B48614/178.104.2.80/2010-06-08 13:32 APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 Static High CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 D 1 0 0 0 0 0 0 0 0 0 0 - 1 D 1 0 0 0 0 0 0 0 0 0 0 - 2 D 1 1 1 1 0 0 0 0 0 F 0 - 3 D 1 1 1 1 0 0 0 0 0 F 0 - Cycle Number Command 0 toggling Datab) Sub-Loop CKE CK, CK Table 5 - IDD2N and IDD3N Measurement-Loop Patterna) 1 4-7 repeat Sub-Loop 0, use BA[2:0] = 1 instead 2 8-11 repeat Sub-Loop 0, use BA[2:0] = 2 instead 3 12-15 repeat Sub-Loop 0, use BA[2:0] = 3 instead 4 16-19 repeat Sub-Loop 0, use BA[2:0] = 4 instead 5 20-23 repeat Sub-Loop 0, use BA[2:0] = 5 instead 6 24-17 repeat Sub-Loop 0, use BA[2:0] = 6 instead 7 28-31 repeat Sub-Loop 0, use BA[2:0] = 7 instead a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. b) DQ signals are MID-LEVEL. Static High CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 D 1 0 0 0 0 0 0 0 0 0 0 - 1 D 1 0 0 0 0 0 0 0 0 0 0 - 2 D 1 1 1 1 0 0 0 0 0 F 0 - 3 D 1 1 1 1 0 0 0 0 0 F 0 - Cycle Number Command 0 toggling Datab) Sub-Loop CKE CK, CK Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Patterna) 1 4-7 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1 2 8-11 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2 3 12-15 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3 4 16-19 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4 5 20-23 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5 6 24-17 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6 7 28-31 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7 a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. b) DQ signals are MID-LEVEL. Rev. 0.2 / Jun. 2010 *182fd049-db40* 20 B48614/178.104.2.80/2010-06-08 13:32 APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 RD 0 1 0 1 0 0 00 0 0 0 0 00000000 1 D 1 0 0 0 0 0 00 0 0 0 0 - 2,3 D,D 1 1 1 1 0 0 00 0 0 0 0 - 4 RD 0 1 0 1 0 0 00 0 0 F 0 00110011 D 1 0 0 0 0 0 00 0 0 F 0 - D,D 1 1 1 1 0 0 00 0 0 F 0 - Cycle Number Datab) Sub-Loop CKE CK, CK Table 7 - IDD4R and IDDQ4R Measurement-Loop Patterna) 0 Static High toggling 5 6,7 1 8-15 repeat Sub-Loop 0, but BA[2:0] = 1 2 16-23 repeat Sub-Loop 0, but BA[2:0] = 2 3 24-31 repeat Sub-Loop 0, but BA[2:0] = 3 4 32-39 repeat Sub-Loop 0, but BA[2:0] = 4 5 40-47 repeat Sub-Loop 0, but BA[2:0] = 5 6 48-55 repeat Sub-Loop 0, but BA[2:0] = 6 7 56-63 repeat Sub-Loop 0, but BA[2:0] = 7 a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL. Rev. 0.2 / Jun. 2010 *182fd049-db40* 21 B48614/178.104.2.80/2010-06-08 13:32 APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 WR 0 1 0 0 1 0 00 0 0 0 0 00000000 1 D 1 0 0 0 1 0 00 0 0 0 0 - 2,3 D,D 1 1 1 1 1 0 00 0 0 0 0 - 4 WR 0 1 0 0 1 0 00 0 0 F 0 00110011 D 1 0 0 0 1 0 00 0 0 F 0 - D,D 1 1 1 1 1 0 00 0 0 F 0 - Cycle Number Datab) Sub-Loop CKE CK, CK Table 8 - IDD4W Measurement-Loop Patterna) 0 Static High toggling 5 6,7 1 8-15 repeat Sub-Loop 0, but BA[2:0] = 1 2 16-23 repeat Sub-Loop 0, but BA[2:0] = 2 3 24-31 repeat Sub-Loop 0, but BA[2:0] = 3 4 32-39 repeat Sub-Loop 0, but BA[2:0] = 4 5 40-47 repeat Sub-Loop 0, but BA[2:0] = 5 6 48-55 repeat Sub-Loop 0, but BA[2:0] = 6 7 56-63 repeat Sub-Loop 0, but BA[2:0] = 7 a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL. b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL. Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 REF 0 0 0 1 0 0 0 0 0 0 0 - 1 1.2 D, D 1 0 0 0 0 0 00 0 0 0 0 - 3,4 D, D 1 1 1 1 0 0 00 0 0 F 0 - Cycle Number 0 Sub-Loop CKE Datab) Static High toggling CK, CK Table 9 - IDD5B Measurement-Loop Patterna) 2 5...8 repeat cycles 1...4, but BA[2:0] = 1 9...12 repeat cycles 1...4, but BA[2:0] = 2 13...16 repeat cycles 1...4, but BA[2:0] = 3 17...20 repeat cycles 1...4, but BA[2:0] = 4 21...24 repeat cycles 1...4, but BA[2:0] = 5 25...28 repeat cycles 1...4, but BA[2:0] = 6 29...32 repeat cycles 1...4, but BA[2:0] = 7 33...nRFC-1 repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary. a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. b) DQ signals are MID-LEVEL. Rev. 0.2 / Jun. 2010 *182fd049-db40* 22 B48614/178.104.2.80/2010-06-08 13:32 APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 Table 10 - IDD7 Measurement-Loop Patterna) 0 1 2 3 4 Static High 5 6 7 8 toggling 9 10 0 1 2 ... nRRD nRRD+1 nRRD+2 ... 2*nRRD 3*nRRD 4*nRRD nFAW nFAW+nRRD nFAW+2*nRRD nFAW+3*nRRD nFAW+4*nRRD 2*nFAW+0 2*nFAW+1 2&nFAW+2 11 2*nFAW+nRRD 2*nFAW+nRRD+1 2&nFAW+nRRD+ 2 12 13 2*nFAW+2*nRRD 2*nFAW+3*nRRD 14 2*nFAW+4*nRRD 15 16 17 18 3*nFAW 3*nFAW+nRRD 3*nFAW+2*nRRD 3*nFAW+3*nRRD 19 3*nFAW+4*nRRD A[2:0] A[6:3] A[9:7] A[10] A[15:11] BA[2:0] ODT WE CAS RAS CS Command Cycle Number Sub-Loop CKE CK, CK ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9 ACT 0 0 1 1 0 0 00 0 0 0 0 RDA 0 1 0 1 0 0 00 1 0 0 0 D 1 0 0 0 0 0 00 0 0 0 0 repeat above D Command until nRRD - 1 ACT 0 0 1 1 0 1 00 0 0 F 0 RDA 0 1 0 1 0 1 00 1 0 F 0 D 1 0 0 0 0 1 00 0 0 F 0 repeat above D Command until 2* nRRD - 1 repeat Sub-Loop 0, but BA[2:0] = 2 repeat Sub-Loop 1, but BA[2:0] = 3 D 1 0 0 0 0 3 00 0 0 F 0 Assert and repeat above D Command until nFAW - 1, if necessary repeat Sub-Loop 0, but BA[2:0] = 4 repeat Sub-Loop 1, but BA[2:0] = 5 repeat Sub-Loop 0, but BA[2:0] = 6 repeat Sub-Loop 1, but BA[2:0] = 7 D 1 0 0 0 0 7 00 0 0 F 0 Assert and repeat above D Command until 2* nFAW - 1, if necessary ACT 0 0 1 1 0 0 00 0 0 F 0 RDA 0 1 0 1 0 0 00 1 0 F 0 D 1 0 0 0 0 0 00 0 0 F 0 Repeat above D Command until 2* nFAW + nRRD - 1 ACT 0 0 1 1 0 1 00 0 0 0 0 RDA 0 1 0 1 0 1 00 1 0 0 0 D 1 0 0 0 0 1 00 0 0 0 0 Repeat above D Command until 2* nFAW + 2* nRRD - 1 repeat Sub-Loop 10, but BA[2:0] = 2 repeat Sub-Loop 11, but BA[2:0] = 3 D 1 0 0 0 0 3 00 0 0 0 0 Assert and repeat above D Command until 3* nFAW - 1, if necessary repeat Sub-Loop 10, but BA[2:0] = 4 repeat Sub-Loop 11, but BA[2:0] = 5 repeat Sub-Loop 10, but BA[2:0] = 6 repeat Sub-Loop 11, but BA[2:0] = 7 D 1 0 0 0 0 7 00 0 0 0 0 Assert and repeat above D Command until 4* nFAW - 1, if necessary Datab) 00000000 00110011 - - 00110011 00000000 - - - a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL. Rev. 0.2 / Jun. 2010 *182fd049-db40* 23 B48614/178.104.2.80/2010-06-08 13:32 APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 IDD Specifications IDD values are for full operating range of voltage and temperature unless otherwise noted. IDD Specification Speed Grade Bin DDR3 - 1066 7-7-7 DDR3 - 1333 9-9-9 DDR3 - 1600 11-11-11 Symbol Max. Max. Max. IDD0 70 80 85 mA IDD01 80 90 95 mA IDD2P0 24 24 24 mA IDD2P1 30 30 30 mA Unit IDD2N 50 60 60 mA IDD2NT 70 80 80 mA IDD2Q 50 60 60 mA IDD3P 30 30 30 mA IDD3N 60 70 80 mA IDD4R 105 125 135 mA IDD4W 110 128 140 mA IDD5B 190 195 200 mA Notes x4/x8 IDD6 24 24 24 mA x4/x8,1 IDD6ET 30 30 30 mA x4/x8,2 IDD6TC 30 30 30 mA x4/x8,3 IDD7 135 165 175 mA x4/x8 Notes: 1. Applicable for MR2 settings A6=0 and A7=0. Temperature range for IDD6 is 0 - 85oC. 2. Applicable for MR2 settings A6=0 and A7=1. Temperature range for IDD6ET is 0 - 95oC. 3. Applicable for MR2 settings A6=1 and A7=0. IDD6TC is measured at 95oC Rev. 0.2 / Jun. 2010 *182fd049-db40* 24 B48614/178.104.2.80/2010-06-08 13:32 APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 Input/Output Capacitance Parameter Input/output capacitance (DQ, DM, DQS, DQS, TDQS, TDQS) Input capacitance, CK and CK Input capacitance delta CK and CK Input capacitance delta, DQS and DQS Input capacitance (All other input-only pins) Input capacitance delta (All CTRL input-only pins) Input capacitance delta (All ADD/CMD input-only pins) Input/output capacitance delta (DQ, DM, DQS, DQS) Input/output capacitance of ZQ pin Notes: Symbol DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units Notes 2.3 pF 1,2,3 0.8 1.4 pF 2,3 0.15 0 0.15 pF 2,3,4 0 0.15 0 0.15 pF 2,3,5 1.35 0.75 1.3 0.75 1.3 pF 2,3,6 -0.5 0.3 -0.4 0.2 -0.4 0.2 pF 2,3,7,8 0.5 -0.5 0.5 -0.4 0.4 -0.4 0.4 pF 2,3,9,10 -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 pF 2,3,11 - 3 - 3 - 3 - 3 pF 2,3,12 Min Max Min Max Min Max Min Max CIO 1.5 3.0 1.5 2.7 1.5 2.5 1.5 CCK 0.8 1.6 0.8 1.6 0.8 1.4 CDCK 0 0.15 0 0.15 0 CDDQS 0 0.20 0 0.20 CI 0.75 1.35 0.75 CDI_CTRL -0.5 0.3 CDI_ADD_C -0.5 CDIO CZQ MD 1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS. 2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is measured according to JEP147("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER(VNA)") with VDD, VDDQ, VSS,VSSQ applied and all other pins floating (except the pin under test, CKE, RESET and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off. 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. Absolute value of CCK-CCK. 5. Absolute value of CIO(DQS)-CIO(DQS). 6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE. 7. CDI_CTR applies to ODT, CS and CKE. 8. CDI_CTRL=CI(CNTL) - 0.5 * CI(CLK) + CI(CLK)) 9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE. 10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK)) 11. CDIO=CIO(DQ) - 0.5*(CIO(DQS)+CIO(DQS)) 12. Maximum external load capacitance an ZQ pin: 5 pF. Rev. 0.2 / Jun. 2010 *182fd049-db40* 25 B48614/178.104.2.80/2010-06-08 13:32 APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 Standard Speed Bins DDR3L SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin. DDR3-800 Speed Bins For specific Notes See "Speed Bin Table Notes" on page 30. Speed Bin DDR3-800E CL - nRCD - nRP 6-6-6 Unit Parameter Symbol min max Internal read command to first data tAA 15 20 ns ACT to internal read or write delay time tRCD 15 -- ns PRE command period tRP 15 -- ns ACT to ACT or REF command period tRC 52.5 -- ns ACT to PRE command period tRAS 37.5 9 * tREFI ns CL = 5 CWL = 5 tCK(AVG) CL = 6 CWL = 5 tCK(AVG) Reserved 2.5 3.3 ns 1, 2, 3, 4 ns 1, 2, 3 Supported CL Settings 6 nCK Supported CWL Settings 5 nCK Rev. 0.2 / Jun. 2010 *182fd049-db40* Notes 26 B48614/178.104.2.80/2010-06-08 13:32 APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 DDR3-1066 Speed Bins For specific Notes See "Speed Bin Table Notes" on page 30. Speed Bin DDR3-1066F CL - nRCD - nRP Parameter Symbol Unit 7-7-7 min max Internal read command to first data tAA 13.125 20 ns ACT to internal read or write delay time tRCD 13.125 -- ns PRE command period tRP 13.125 -- ns ACT to ACT or REF command period tRC 50.625 -- ns ACT to PRE command period tRAS 37.5 9 * tREFI ns CL = 5 CL = 6 CL = 7 CL = 8 Note CWL = 5 tCK(AVG) Reserved ns 1, 2, 3, 4, 5 CWL = 6 tCK(AVG) Reserved ns 4 CWL = 5 tCK(AVG) ns 1, 2, 3, 5 CWL = 6 tCK(AVG) Reserved ns 1, 2, 3, 4 CWL = 5 tCK(AVG) Reserved ns 4 CWL = 6 tCK(AVG) ns 1, 2, 3, 4 CWL = 5 tCK(AVG) ns 4 CWL = 6 tCK(AVG) ns 1, 2, 3 2.5 3.3 1.875 < 2.5 Reserved 1.875 < 2.5 Supported CL Settings 6, 7, 8 nCK Supported CWL Settings 5, 6 nCK Rev. 0.2 / Jun. 2010 *182fd049-db40* 27 B48614/178.104.2.80/2010-06-08 13:32 APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 DDR3-1333 Speed Bins For specific Notes See "Speed Bin Table Notes" on page 30. Speed Bin DDR3-1333H CL - nRCD - nRP Parameter Symbol Unit 9-9-9 min max Internal read command to first data tAA 13.5 (13.125)8 20 ns ACT to internal read or write delay time tRCD 13.5 (13.125)8 -- ns PRE command period tRP 13.5 (13.125)8 -- ns ACT to ACT or REF command period tRC 49.5 (49.125)8 -- ns ACT to PRE command period tRAS 36 9 * tREFI ns Note CWL = 5 tCK(AVG) Reserved ns 1,2, 3,4, 6 CWL = 6, 7 tCK(AVG) Reserved ns 4 CWL = 5 tCK(AVG) ns 1, 2, 3, 6 CWL = 6 tCK(AVG) Reserved ns 1, 2, 3, 4, 6 CWL = 7 tCK(AVG) Reserved ns 4 CWL = 5 tCK(AVG) Reserved ns 4 CWL = 6 tCK(AVG) ns 1, 2, 3, 4, 6 CWL = 7 tCK(AVG) Reserved ns 1, 2, 3, 4 CWL = 5 tCK(AVG) Reserved ns 4 CWL = 6 tCK(AVG) ns 1, 2, 3, 6 CWL = 7 tCK(AVG) Reserved ns 1, 2, 3, 4 CWL = 5, 6 tCK(AVG) Reserved ns 4 CWL = 7 tCK(AVG) ns 1, 2, 3, 4 CWL = 5, 6 tCK(AVG) ns 4 CWL = 7 tCK(AVG) ns ns 1, 2, 3 Reserved Supported CL Settings 6, 8, (7), 9, (10) nCK Supported CWL Settings 5, 6, 7 nCK CL = 5 CL = 6 CL = 7 CL = 8 CL = 9 CL = 10 Rev. 0.2 / Jun. 2010 *182fd049-db40* 2.5 3.3 1.875 < 2.5 Reserved 1.875 < 2.5 1.5 <1.875 Reserved 1.5 <1.875 28 B48614/178.104.2.80/2010-06-08 13:32 APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 DDR3-1600 Speed Bins For specific Notes See "Speed Bin Table Notes" on page 30. Speed Bin DDR3-1600K CL - nRCD - nRP Parameter Symbol Unit 11-11-11 min max Internal read command to first data tAA 13.75 (13.125)8 20 ns ACT to internal read or write delay time tRCD 13.75 (13.125)8 -- ns PRE command period tRP 13.75 (13.125)8 -- ns ACT to ACT or REF command period tRC 48.75 (48.125)8 -- ns ACT to PRE command period tRAS 35 9 * tREFI ns CL = 5 CL = 6 CL = 7 CL = 8 CL = 9 Note CWL = 5 tCK(AVG) Reserved ns 1, 2, 3, 4, 7 CWL = 6, 7 tCK(AVG) Reserved ns 4 CWL = 5 tCK(AVG) ns 1, 2, 3, 7 CWL = 6 tCK(AVG) Reserved ns 1, 2, 3, 4, 7 CWL = 7 tCK(AVG) Reserved ns 4 CWL = 5 tCK(AVG) Reserved ns 4 CWL = 6 tCK(AVG) ns 1, 2, 3, 4, 7 CWL = 7 tCK(AVG) ns 1, 2, 3, 4, 7 CWL = 8 tCK(AVG) ns 4 CWL = 5 tCK(AVG) ns 4 CWL = 6 tCK(AVG) ns 1, 2, 3, 7 CWL = 7 tCK(AVG) CWL = 8 tCK(AVG) CWL = 5, 6 tCK(AVG) CWL = 7 tCK(AVG) CWL = 8 tCK(AVG) tCK(AVG) tCK(AVG) CWL = 7 tCK(AVG) CWL = 8 CWL = 5, 6,7 tCK(AVG) CL = 11 tCK(AVG) CWL = 8 2.5 1.875 < 2.5 Reserved Reserved Reserved 1.875 < 2.5 Reserved Reserved Reserved 1.5 <1.875 Reserved Reserved CWL = 5, 6 CL = 10 3.3 1.5 <1.875 Reserved Reserved 1.25 <1.5 ns 1, 2, 3, 4, 7 ns 1, 2, 3, 4 ns 4 ns 1, 2, 3, 4, 7 ns 1, 2, 3, 4 ns 4 ns ns 1, 2, 3, 7 1,2,3,4 ns 4 ns 1, 2, 3 Supported CL Settings 6, (7), 8, (9), 10, 11 nCK Supported CWL Settings 5, 6, 7, 8 nCK Rev. 0.2 / Jun. 2010 *182fd049-db40* 29 B48614/178.104.2.80/2010-06-08 13:32 APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 Speed Bin Table Notes Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V); 1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK (AVG), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting. 2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard tCK (AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK (AVG) [ns], rounding up to the next `Supported CL'. 3. tCK(AVG).MAX limits: Calculate tCK (AVG) = tAA.MAX / CLSELECTED and round the resulting tCK (AVG) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX corresponding to CLSELECTED. 4. `Reserved' settings are not allowed. User must program a different value. 5. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 6. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 7. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 8. Any DDR3-1866 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 9. Hynix DDR3 SDRAM devices support down binning to CL=7 and CL=9, tAA/tRCD/tRPmin must be 13.125 ns or lower. SPD settings must be programmed to match. For example, DDR3 1333H devices supporting down binning to DDR3-1066F should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600K devices supporting down binning to DDR3-1333H or DDR3 1600F should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be programmed accordingly. For example, 49.125ns (tRASmin + tRPmin = 36 ns + 13.125 ns) for DDR3-1333H and 48.125ns (tRASmin + tRPmin = 35 ns + 13.125 ns) for DDR3-1600K. Rev. 0.2 / Jun. 2010 *182fd049-db40* 30 B48614/178.104.2.80/2010-06-08 13:32 APCPCWM_4828539:WP_0000001WP_000000 APCPCWM_4828539:WP_0000001WP_0000001 Package Dimensions Package Dimension(x4/x8); 82Ball Fine Pitch Ball Grid Array Outline 9.900 0.100 A1 CORNER INDEX AREA 1.250 0.100 (2.475) 11.100 0.100 (2.750) 0.290 0.050 3.0 X 5.0 MIN FLAT AREA TOP VIEW SIDE VIEW 0.800 X 10 = 8.000 0.800 0.950 0.100 A1 BALL MARK 11 10 9 8 4 3 2 1 A B C 0.800 E F G H J 0.800 X 12 = 9.600 D K L N 82 x 0.400 0.050 1.600 1.600 0.700 0.100 M BOTTOM VIEW Rev. 0.2 / Jun. 2010 *182fd049-db40* 31 B48614/178.104.2.80/2010-06-08 13:32