Dear customers, About the change in the name such as "Oki Electric Industry Co. Ltd." and "OKI" in documents to OKI Semiconductor Co., Ltd. The semiconductor business of Oki Electric Industry Co., Ltd. was succeeded to OKI Semiconductor Co., Ltd. on October 1, 2008. Therefore, please accept that although the terms and marks of "Oki Electric Industry Co., Ltd.", "Oki Electric", and "OKI" remain in the documents, they all have been changed to "OKI Semiconductor Co., Ltd.". It is a change of the company name, the company trademark, and the logo, etc. , and NOT a content change in documents. October 1, 2008 OKI Semiconductor Co., Ltd. 550-1 Higashiasakawa-cho, Hachioji-shi, Tokyo 193-8550, Japan http://www.okisemi.com/en/ FEDD56V16800F-01 1Semiconductor MSM56V16800F This version: November. 2000 Previous version : 2-Bank x 1,048,576-Word x 8-Bit SYNCHRONOUS DYNAMIC RAM DESCRIPTION The MSM56V16800F is a 2-Bank x 1,048,576-word x 8-bit Synchronous dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The device operates at 3.3V. The inputs and outputs are LVTTL compatible. FEATURES Silicon gate, quadruple polysilicon CMOS, 1-transistor memory cell 2-Bank x 1,048,576-word x 8-bit configuration Single 3.3V power supply, 0.3V tolerance Input : LVTTL compatible Output : LVTTL compatible Refresh : 4096 cycles/64ms Programmable data transfer mode - CAS Latency (1,2,3) - Burst Length (1,2,4,8,Full Page) - Data scramble (sequential, interleave) CBR auto-refresh, Self-refresh capability Packages: 44-pin 400mil plastic TSOP (TypeII) (TSOPII44-P-400-0.80-1K)(Product : MSM56V16800F-xxTS-K) xx indicates speed rank. PRODUCT FAMILY Family Max. Frequency Access Time (Max.) tAC2 tAC3 MSM56V16800F-8A 125MHz 6ns 6ns MSM56V16800F-10 100MHz 9ns 9ns 1/31 FEDD56V16800F-01 1Semiconductor MSM56V16800F PIN CONFIGURATION (TOP VIEW) VCC 1 DQ1 2 VSSQ 3 DQ2 4 VCCQ 5 DQ3 6 VSSQ 7 DQ4 8 VCCQ 9 NC 10 NC 11 WE 12 CAS 13 RAS 14 CS 15 A11 16 A10 17 A0 18 A1 19 A2 20 A3 21 VCC 22 44 VSS 43 DQ8 42 VSSQ 41 DQ7 40 VCCQ 39 DQ6 38 VSSQ 37 DQ5 36 VCCQ 35 NC 34 NC 33 DQM 32 CLK 31 CKE 30 NC 29 A9 28 A8 27 A7 26 A6 25 A5 24 A4 23 VSS 44-Pin Plastic TSOP (K Type) Pin Name Function Pin Name Function CLK System Clock DQM Data Input/ Output Musk CS Chip Select DQi Data Input/ Output CKE Clock Enable VCC Power Supply (3.3V) A0-A10 Address VSS Ground (0V) A11 Bank Select Address VCCQ Data Output Power Supply (3.3V) RAS Row Address Strobe VSSQ Data Output Ground (0V) CAS Column Address Strobe NC No Connection WE Write Enable Note : The same power supply voltage must be provided to every VCC pin and VCCQ pin. The same GND voltage level must be provided to every VSS pin and VSSQ pin. 2/31 FEDD56V16800F-01 1Semiconductor MSM56V16800F PIN DESCRIPTION CLK Fetches all inputs at the "H" edge. CS Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE, DQM. CKE Masks system clock to deactivate the subsequent CLK operation. If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is deactivated. CKE should be asserted at least one cycle prior to a new command. Address Row & column multiplexed. Row address : RA0 - RA10 Column Address : CA0 - CA8 A11 Slects bank to be activated during row address latch time and selects bank for precharge and read/write during column address latch time. A11="L" : Bank A, A11="H" : Bank B RAS CAS Functionality depends on the combination. For details, see the function truth table. WE DQM Masks the read data of two clocks later when DQM is set "H" at the "H" edge of the clock signal. Masks the write data of the same clock when DQM is set "H" at the "H" edge of the clock signal. DQi Data inputs/outputs are multiplexed on the same pin. 3/31 FEDD56V16800F-01 1Semiconductor MSM56V16800F BLOCK DIAGRAM CKE CLK CS RAS CAS WE DQM Programing Register Timing Register Latency & Burst Controller I/O Controller Bank Controller A11 Internal Col. Address Counter Input Data Register A0 - A11 Input Buffers 8 98 Column Address Buffers 9 Column Decoders Sense Amplifiers Internal Row Address Counter 12 Row Address Buffers 12 8 Row Decoders Word Drivers 8Mb Memory Cells Row Decoders Word Drivers 8Mb Memory Cells 8 Read Data Register 8 Output Buffers 8 DQ1 - DQ8 Sense Amplifiers Column Decoders 4/31 FEDD56V16800F-01 1Semiconductor MSM56V16800F ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (Voltages referenced to VSS) Parameter Symbol Value Unit VIN, VOUT -0.5 to VCC+ 0.5 V VCC , VCCQ -0.5 to 4.6 V Storage Temperature Tstg -55 to 150 C Power Dissipation PD* 600 mW Short Circuit Output Current IOS 50 mA Operating Temperature Topr 0 to 70 C Voltage on Any Pin Relative to VSS VCC Supply Voltage *: Ta = 25C RECOMMENDED OPERATIING CONDITIONS (Voltages referenced to VSS = 0V) Parameter Symbol Min. Typ. Max. Unit VCC, VCCQ 3.0 3.3 3.6 V Input High Voltage VIH 2.0 VCC + 0.2 V Input Low Voltage VIL - 0.3 0.8 V Power Supply Voltage PIN CAPACITANCE (VBIAS = 1.4V, Ta = 25C, f = 1 MHz) Parameter Input Capacitance (CLK) Input Capacitance (RAS, CAS, WE, CS, CKE, DQM, A0 - A11) Input/Output Capacitance (DQ1 - DQ8) Symbol Min. Max. Unit CCLK 2.5 4 pF CIN 2.5 5 pF COUT 4 6.5 pF 5/31 FEDD56V16800F-01 1Semiconductor MSM56V16800F DC CHARACTERISTICS MSM56V16800 Unit Note Condition Parameter F-8A Symbol F-10 Bank CKE Others Min. Max. Min. Max. Output High Voltage VOH IOH = -2.0mA 2.4 2.4 V Output Low Voltage VOL IOL = 2.0mA 0.4 0.4 V Input Leakage Current ILI - 10 10 - 10 10 A Output Leakage Current ILO - 10 10 - 10 10 A tCC = Min. tRC = Min. No Burst 80 70 mA 1,2 tCC = Min. tRC = Min. tRRD = Min. No Burst 115 95 mA 1,2 tCC = Min. 35 30 mA 3 CKEVIL tCC = Min. 3 3 mA 2 One Bank CKEVIH Active tCC = Min. 40 35 mA 3 CKEVIH tCC = Min. 125 100 mA 1,2 One Bank CKEVIH Active tCC = Min. tRC = Min. 80 70 mA 2 Both CKE VIL ICC6 Banks Precharge tCC = Min. 2 2 mA Both CKEVIL ICC7 Banks Precharge tCC = Min. 2 2 mA ICC1 Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (Clock Suspension) Average Power Supply Current Both ICC1D Banks Active Power Supply Current (Auto-Refresh) Average Power Supply Current (Self-Refresh) Average Power Supply Current (Power Down) CKEVIH Both ICC2 Banks CKEVIH Precharge Both ICC3S Banks Active ICC3 (Active Standby) Power Supply Current (Burst) One Bank CKEVIH Active Both ICC4 Banks Active ICC5 Notes: 1. Measured with outputs open. 2. The address and data can be changed once or left unchanged during one cycle. 3. The address and data can be changed once or left unchanged during two cycle. 6/31 FEDD56V16800F-01 1Semiconductor MSM56V16800F Mode Set Address Keys CAS Latency Burst Type Burst Length A6 A5 A4 CL A3 BT A2 A1 A0 BT = 0 BT = 1 0 0 0 Reserved 0 Sequential 0 0 0 1 1 0 0 1 1 1 Interleave 0 0 1 2 2 0 1 0 2 0 1 0 4 4 0 1 1 3 0 1 1 8 8 1 0 0 Reserved 1 0 0 Reserved Reserved 1 0 1 Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved 1 1 0 Reserved Reserved 1 1 1 Reserved 1 1 1 Full Page Reserved Notes: A7, A8, A9, A10 and A11 should stay "L" during mode set cycle. MSM56V16800F support two methods of Power on Sequence. POWER ON SEQUENCE 1 1. With inputs in NOP state, turn on the power supply and start the system clock. 2. After the VCC voltage has reached the specified level, pause for 200s or more with the input kept in NOP state. 3. Issue the precharge all bank command. 4. Apply a CBR auto-refresh eight or more times. 5. Enter the mode register setting command. POWER ON SEQUENCE 2 1. With inputs in NOP state, turn on the power supply and start the system clock. 2. After the VCC voltage has reached the specified level, pause for 200s or more with the input kept in NOP state. 3. Issue the precharge all bank command. 4. Enter the mode register setting command. 5. Apply a CBR auto-refresh eight or more times. 7/31 FEDD56V16800F-01 1Semiconductor MSM56V16800F AC CHARACTERISTICS (1/2) Note1,2 Parameter Symbol MSM56V16800 F-8A MSM56V16800 F-10 Min. Max. Min. Max. Unit Note CL = 3 tCC3 8 10 ns CL = 2 tCC2 10 15 ns CL = 1 tCC1 20 30 ns CL = 3 tAC3 6 9 ns 3,4 CL = 2 tAC2 6 9 ns 3,4 CL = 1 tAC1 16 27 ns 3,4 Clock High Pulse Time tCH 3 3 ns 4 Clock Low Pulse Time tCL 3 3 ns 4 Input Setup Time tSI 2 3 ns Input Hold Time tHI 1 1 ns Output Low Impedance Time from Clock tOLZ 3 3 ns Output High Impedance Time from Clock tOHZ 8 8 ns Output Hold from Clock tOH 3 3 ns Random Read or Write Cycle Time tRC 70 90 ns RAS Precharge Time tRP 20 30 ns RAS Pulse Width tRAS 48 100,000 60 100,000 ns RAS to CAS Delay Time tRCD 20 30 ns Write Recovery Time tWR 8 15 ns RAS to CAS Bank Active Delay Time tRRD 20 20 ns Refresh Time tREF 64 64 ms Power-down Exit setup Time tRDE tSI +1CLK tSI +1CLK ns tT 3 3 ns Clock Cycle Time Access Time from Clock Input Level Transition Time CAS to CAS Delay Time (Min.) tCCD 1 1 Cycle Clock Disable Time from CKE tCKE 1 1 Cycle Data Output High Impedance Time from DQM tDOZ 2 2 Cycle Dada Input Mask Time from DQM tDOD 0 0 Cycle 3 8/31 FEDD56V16800F-01 1Semiconductor MSM56V16800F AC CHARACTERISTICS (2/2) Note1,2 Parameter Symbol MSM56V16800 F-8A Min. Max. MSM56V16800 F-10 Min. Unit Note Max. Data Input Mask Time from Write Command tDWD 0 0 Cycle Data Output High Impedance Time from Precharge Command tROH CL CL Cycle Active Command Input Time from Mode Register Set Command Input (Min.) tMRD 2 2 Cycle Write Command Input Time from Outpput tOWD 2 2 Cycle Notes: 1. AC measurements assume that tT = 1ns. 2. The reference level for timing of input signals is 1.4V. 3. Output load. Z=50 Output 50pF (External Load) 4. The access time is defined at 1.4V. 5. If tT is longer than 1ns, then the reference level for timing of input signals is VIH and VIL. 9/31 FEDD56V16800F-01 1Semiconductor MSM56V16800F TIMING CHART Read & Write Cycle (Same Bank) @CAS Latency= =2, Burst Length= =4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK tRC CKE CS tRP RAS tRCD CAS ADDR Ra Rb Ca0 Cb0 A11 A10 Ra Rb tOH Qa0 Qa1 Qa2 Qa3 DQ tAC tOHZ Db0 Db1 Db2 Db3 tWR WE DQM Row Active Read Command Precharge Command Row Active Write Command Precharge Command 10/31 FEDD56V16800F-01 1Semiconductor MSM56V16800F Single Bit Read-Write-Read Cycle (Same Page) @CAS Latency= =2, Burst Length=4 0 1 2 3 4 tCH 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK tCC tCL High CKE CS tHI tSI RAS tSI ICCD tHI CAS tSI tSI ADDR Ra tSI Ca tHI A11 BS A10 Ra Cb Cc BS BS tHI BS BS tHI tOHZ tAC Qa DQ Db tOLZ Qc tSI tOH tHI lOWD WE tSI DQM Row Active Read Command Write Command Precharge Command Read Command 11/31 FEDD56V16800F-01 1Semiconductor MSM56V16800F *Note: 1. When CS is set "High" at a clock transition from "Low" to "High", all inputs except CKE and DQM are invalid. 2. When issuing an active, read or write command, the bank is selected by A11. A11 Active, read or write 0 Bank A 1 Bank B 3. The auto precharge function is enabled or disabled by the A10 input when the read or write command is issued. A10 A11 Operation 0 0 After the end of burst, bank A holds the idle status. 1 0 After the end of burst, bank A is precharged automatically. 0 1 After the end of burst, bank B holds the idle status. 1 1 After the end of burst, bank B is precharged automatically. 4. When issuing a precharge command, the bank to be precharged is selected by the A10 and A11 inputs. A10 A11 Operation 0 0 Bank A is precharged. 0 1 Bank B is precharged. 1 X Both banks A and B are precharged. 5. The input data and the write command are latched by the same clock (Write latency=0). 6. The output is forced to high impedance by (1CLK+ tOHZ ) after DQM entry. 12/31 FEDD56V16800F-01 1Semiconductor MSM56V16800F Page Read & Write Cycle (Same Bank) @CAS Latency= =2, Burst Length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 tWR Note 2 15 16 17 18 19 CLK High CKE CS Bank A Active RAS CAS ICCD ADDR Ca0 Cb0 Cc0 Cd0 Dc0 Dc1 Dd0 A11 A10 DQ Qa0 Qa1 Qb0 Qb1 lOWD WE Note 1 DQM Read Command Read Command Write Command Precharge Command Write Command *Note: 1. To write data before a burst read ends, DQM should be asserted three cycles prior to the write command to avoid bus contention. 2. To assert row precharge before a burst write ends, wait tWR after the last write data input. Input data during the precharge input cycle will be masked internally. 13/31 FEDD56V16800F-01 1Semiconductor MSM56V16800F Read & Write Cycle with Auto Precharge @ Burst Length= =4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS tRRD CAS ADDR Ra Rb Ra Rb Ca Cb A11 A10 WE CAS Latency=1 Qa0 Qa1 Qa2 Qa3 DQ Db0 Db1 Db2 Db3 A-Bank Precharge Start DQM CAS Latency=2 Qa0 Qa1 Qa2 Qa3 DQ Db0 Db1 Db2 Db3 A-Bank Precharge Start DQM CAS Latency=3 Qa0 Qa1 Qa2 Qa3 DQ Db0 Db1 Db2 Db3 tWR A-Bank Precharge Start DQM Row Active (A-Bank) Row Active (B-Bank) A Bank Read with Auto Precharge B Bank Write with Auto Precharge B Bank Precharge Start Point 14/31 FEDD56V16800F-01 1Semiconductor MSM56V16800F Bank Interleave Random Row Read Cycle @CAS Latency=2, Burst Length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS tRC RAS tRRD CAS ADDR RAa CAa RBb CBb RAc CAc A11 A10 DQ RAa RBb QAa0 QAa1 QAa2 QAa3 RAc QBb1 QBb2 QBb3 QBb4 QAc0 QAc1 QAc2 QAc3 WE DQM Row Active Read Command Read Command Row Active (A-Bank) (A-Bank) (B-Bank) (B-Bank) Row Active Read Command Precharge Command (A-Bank) Precharge Command (A-Bank) (A-Bank) (B-Bank) 15/31 FEDD56V16800F-01 1Semiconductor MSM56V16800F Bank Interleave Random Row Write Cycle @CAS Latency=2, Burst Length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS CAS ADDR RAa CAa RBb CBb RAc CAc A11 A10 RAa RBb RAc DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DQ DAc0 DAc1 WE DQM Row Active (A-Bank) Row Active (B-Bank) Precharge Command (A-Bank) Write Command (A-Bank) Write Command (B-Bank) Write Command (A-Bank) Precharge Command (B-Bank) Row Active (A-Bank) Precharge Command (A-Bank) 16/31 FEDD56V16800F-01 1Semiconductor MSM56V16800F Bank Interleave Page Read Cycle @CAS Latency=2, Burst Length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE Note 1 CS RAS CAS ADDR RAa CAa RBb CBb CAc CBd CAe A11 A10 RAa RBb QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 DQ IROH WE DQM Row Active (A-Bank) Row Active (B-Bank) Read Command (A-Bank) Read Command (B-Bank) Read Command (B-Bank) Read Command (A-Bank) Precharge Command (A-Bank) Read Command (A-Bank) *Note: 1. CS is ignored when RAS, CAS and WE are high at the same cycle. 17/31 FEDD56V16800F-01 1Semiconductor MSM56V16800F Bank Interleave Page Write Cycle @CAS Latency=2, Burst Length= =4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS CAS ADDR RAa CAa RBb CBb CAc CBd A11 A10 RAa RBb DQ DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 WE DQM Row Active (A-Bank) Row Active (B-Bank) Write Command (A-Bank) Write Command (B-Bank) Write Command (B-Bank) Precharge Command (Both Bank) Write Command (A-Bank) 18/31 FEDD56V16800F-01 1Semiconductor MSM56V16800F Bank Interleave Random Row Read/Write Cycle @CAS Latency=2, Burst Length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS CAS ADDR RAa CAa RBb CBb RAc CAc A11 A10 RAa RBb RAc QAa0 QAa1 QAa2 QAa3 DQ QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QAc2 QAc3 WE DQM Row Active (A-Bank) Read Command (A-Bank) Row Active (B-Bank) Write Command (B-Bank) Precharge Command (A-Bank) Read Command (A-Bank) Row Active (A-Bank) 19/31 FEDD56V16800F-01 1Semiconductor MSM56V16800F Bank Interleave Page Read/Write Cycle @CAS Latency=2, Burst Length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS CAS ADDR CAa0 CBb0 CAc0 A11 A10 QAa0 QAa1 QAa2 QAa3 DQ DBb0 DBb1 DBb2 DBb3 QAc0 QAc1 QAc2 QAc3 WE DQM Read Command (A-Bank) Write Command (B-Bank) Read Command (A-Bank) 20/31 FEDD56V16800F-01 1Semiconductor MSM56V16800F Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK Note 1 Note 1 CKE CS RAS CAS ADDR Ra Ca Cb Cc A11 A10 Ra Qa0 Qa1 DQ Note 2 Qa2 Qb0 Qb1 tOHZ tOHZ Dc2 Dc0 Note 3 WE DQM Row Active CLOCK Suspension Read Command Read DQM Read Command Write DQM Read DQM Write Command Write DQM CLOCK Suspension *Note: 1. When Clock Suspension is asserted, the next clock cycle is ignored. 2. When DQM are asserted, the read data after two clock cycles is masked. 3. When DQM are asserted, the write data in the same clock cycle is masked. 21/31 FEDD56V16800F-01 1Semiconductor MSM56V16800F Read to Write Cycle (Same Bank) @CAS Latency=2, Burst Length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE CS Note 1 RAS tRCD CAS ADDR Ra Ca0 Cb0 A11 A10 Ra DQ Da0 Db0 Db1 Db2 Db3 tWR WE DQM Precharge Command Row Active Read Command Write Command *Note: 1. In Case CAS latency is 3, READ can be interrupted by WRITE. The minimum command interval is [burst length + 1] cycles. DQM must be high at least 3 clocks prior to the write command. 22/31 FEDD56V16800F-01 1Semiconductor MSM56V16800F Read Interruption by Precharge Command @Burst Length= =8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS CAS ADDR Ra Ca A11 A10 Ra WE CAS Latency=1 Note 1 Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 DQ lROH DQM CAS Latency=2 Note 1 Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 DQ lROH DQM CAS Latency=3 Note 1 Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 DQ lROH DQM Row Active Read Command Precharge Command *Note: 1. if row precharge is asserted before a burst read ends, then the read data will not output after lROH equals CAS latency. 23/31 FEDD56V16800F-01 1Semiconductor MSM56V16800F Burst Stop Command @Burst Length=8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS CAS ADDR Ca Cb A11 A10 WE CAS Latency=1 Qa0 Qa1 Qa2 Qa3 Qa4 DQ Qb0 Qb1 Qb2 Qb3 Qb4 DQM CAS Latency=2 DQ Qa0 Qa1 Qa2 Qa3 Qa4 Qb0 Qb1 Qb2 Qb3 Qb4 DQM CAS Latency=3 DQ Qa0 Qa1 Qa2 Qa3 Qa4 Qb0 Qb1 Qb2 Qb3 Qb4 DQM Read Command Burst Stop Command Write Command Burst Stop Command 24/31 FEDD56V16800F-01 1Semiconductor MSM56V16800F Power Down Mode @CAS Latency=2, Burst Length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK tSI Note 1 tPDE Note 2t tSI SI CKE tREF (min.) CS RAS CAS Ra ADDR Ca A11 Ra A10 Qa0 Qa1 Qa2 DQ WE DQM Power-down Entry Row Active Clock Power-down Suspension Exit Entry Read Command Clock Suspension Exit Precharge Command *Note: 1. When both banks are in precharge state, and if CKE is set low, then the MSM56V16800F enters power-down mode and maintains the mode while CKE is low. 2. To release the circuit from power-down mode, CKE has to be set high for longer than tPDE (tSI + 1CLK). 25/31 FEDD56V16800F-01 1Semiconductor MSM56V16800F Self Refresh Cycle 0 1 2 CLK tRC CKE tSI CS RAS CAS ADDR Ra A11 BS A10 Ra Hi-Z DQ WE DQM Self Refresh Entry Self Refresh Exit Row Active 26/31 FEDD56V16800F-01 1Semiconductor MSM56V16800F Mode Register Set Cycle 0 1 2 Auto Refresh Cycle 3 4 5 6 0 1 2 3 4 5 6 7 8 9 10 11 CLK High CKE High CS lMRD tRC RAS CAS ADDR Key Ra Hi - Z DQ Hi - Z WE DQM MRS New Command Auto Refresh Auto Refresh 27/31 FEDD56V16800F-01 1Semiconductor MSM56V16800F FUNCTION TRUTH TABLE (Table 1) (1/2) Current State1 CS Idle H X X X X X NOP L H H H X X NOP L H H L BA X L H L X BA CA ILLEGAL 2 ILLEGAL 2 L L H H BA RA L L H L BA A10 L L L H X X L L L L L OP Code Row Active Read Write Read with Auto Precharge Write with Auto Precharge RAS CAS WE BA ADDR Action Row Active NOP 4 Auto-Refresh or Self-Refresh 5 Mode Register Write H X X X X X NOP L H H X X X NOP L H L H BA CA, A10 Read L H L L BA CA, A10 Write L L H H BA RA L L H L BA A10 L L L X X X ILLEGAL H X X X X X NOP (Continue Row Active after Burst ends) L H H H X X NOP (Continue Row Active after Burst ends) L H H L X X Term Burst --> Row Active L H L H BA CA, A10 L H L L BA CA, A10 L L H H BA RA L L H L BA A10 L L L X X X ILLEGAL H X X X X X NOP (Continue Row Active after Burst ends) L H H H X X NOP (Continue Row Active after Burst ends) L H H L X X Term Burst --> Row Active L H L H BA CA, A10 L H L L BA CA, A10 L L H H BA RA ILLEGAL 2 L L H L BA A10 ILLEGAL 2 Precharge Term Burst, start new Burst Read 3 Term Burst, start new Burst Write 3 ILLEGAL 2 Term Burst, execute Row Precharge Term Burst, start new Burst Read 3 Term Burst, start new Burst Write 3 L L L X X X Term Burst, execute Row Precharge 3 ILLEGAL H X X X X X NOP (Continue Burst to End and enter Row Precharge) L H H H X X L H H L BA X NOP (Continue Burst to End and enter Row Precharge) ILLEGAL 2 L H L H BA CA, A10 L H L L X X L L H X BA RA, A10 ILLEGAL 2 ILLEGAL ILLEGAL 2 L L L X X X H X X X X X ILLEGAL NOP (Continue Burst to End and enter Row Precharge) L H H H X X L H H L BA X NOP (Continue Burst to End and enter Row Precharge) ILLEGAL 2 L H L H BA CA, A10 ILLEGAL 2 28/31 FEDD56V16800F-01 1Semiconductor MSM56V16800F FUNCTION TRUTH TABLE (Table 2) (2/2) Current State1 CS RAS Write with Auto Precharge L H L L X X L L H X BA RA, A10 L L L X X X Precharge H X X X X X ILLEGAL 2 ILLEGAL NOP --> Idle after tRP L H H H X X NOP --> Idle after tRP L H H L BA X L H L X BA CA ILLEGAL 2 ILLEGAL 2 L L H H BA RA L L H L BA A10 L L L X X X ILLEGAL H X X X X X NOP L H H H X X NOP L H H L BA X L H L X BA CA ILLEGAL 2 ILLEGAL 2 L L H H BA RA L L H L BA A10 Write Recovery Row Active Refresh Mode Register Access CAS WE BA ADDR Action ILLEGAL ILLEGAL 2 NOP 4 ILLEGAL 2 ILLEGAL 2 L L L X X X H X X X X X ILLEGAL NOP --> Row Active after tRCD L H H H X X NOP --> Row Active after tRCD L H H L BA X L H L X BA CA ILLEGAL 2 ILLEGAL 2 L L H H BA RA L L H L BA A10 L L L X X X ILLEGAL 2 ILLEGAL 2 ILLEGAL NOP --> Idle after tRC H X X X X X L H H X X X NOP --> Idle after tRC L H L X X X ILLEGAL L L H X X X ILLEGAL L L L X X X ILLEGAL H X X X X X NOP L H H H X X NOP L H H L X X ILLEGAL L H L X X X ILLEGAL L L X X X X ILLEGAL ABBREVIATIONS RA = Row Address BA = Bank Address NOP = No OPeration command CA = Column Address AP = Auto Precharge Notes :1. All inputs are enabled when CKE is set high for at least 1 cycle prior to the inputs. 2. Illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. Satisfy the timing of lCCD and tWR to prevent bus contention. 4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A10. 5. Illegal if any bank is not idle. 29/31 FEDD56V16800F-01 1Semiconductor MSM56V16800F FUNCTION TRUTH TABLE for CKE (Table 2) Current State (n) CKEn-1 Self Refresh Power Down All Banks Idle (ABI) 6 Any State Other than Listed Above CKEn CS RAS CAS WE ADDR Action H X X X X X X INVALID L H H X X X X Exit Self Refresh --> ABI L H L H H H X Exit Self Refresh --> ABI L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP (Maintain Self Refresh) H X X X X X X INVALID L H H X X X X Exit Power Down --> ABI L H L H H H X Exit Power Down --> ABI L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL 6 L L X X X X X NOP (Continue power down mode) H H X X X X X Refer to Table 1 H L H X X X X Enter Power Down H L L H H H X Enter Power Down H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L H L X ILLEGAL H L L L L H X Enter Self Refresh H L L L L L X ILLEGAL L L X X X X X NOP H H X X X X X Refer to Operations in Table 1 H L X X X X X Begin Clock Suspend Next Cycle L H X X X X X Enable Clock of Next Cycle L L X X X X X Continue Clock Suspension *Notes :6. Power-down and self-refresh can be entered only when all the banks are in an idle state. 30/31 FEDD56V16800F-01 1Semiconductor MSM56V16800F NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2001 Oki Electric Industry Co., Ltd. 31/31