Dear customers,
About the change in the name such as "Oki Electric Industry Co. Ltd." and
"OKI" in documents to OKI Semiconductor Co., Ltd.
The semiconductor business of Oki Electric Industry Co., Ltd. was succeeded to OKI
Semiconductor Co., Ltd. on October 1, 2008. Therefore, please accept that although
the terms and marks of "Oki Electric Industry Co., Ltd.", “Oki Electric”, and "OKI"
remain in the documents, they all have been changed to "OKI Semiconductor Co., Ltd.".
It is a change of the company name, the company trademark, and the logo, etc. , and
NOT a content change in documents.
October 1, 2008
OKI Semiconductor Co., Ltd.
550-1 Higashiasakawa-cho, Hachioji-shi, Tokyo 193-8550, Japa n
http://www.okisemi.com/en/
FEDD56V16800F-01
1
Semiconductor This version: November. 2000
Previous version :
MSM56V16800F
2-Bank ×
××
× 1,048,576-Word ×
××
× 8-Bit SYNCHRONOUS DYNAMIC RAM
1/31
DESCRIPTION
The MSM56V16800F is a 2-Bank × 1,048,576-word × 8-bit Synchronous dynamic RAM fabricated in
Oki’s silicon-gate CMOS technology. The device operates at 3.3V. The inputs and outputs are LVTTL
compatible.
FEATURES
∙ Silicon gate, quadruple polysilicon CMOS, 1-transistor memory cell
∙ 2-Bank × 1,048,576-word × 8-bit configuration
∙ Single 3.3V power supply, ±0.3V tolerance
∙ Input : LVTTL compatible
∙ Output : LVTTL compatible
∙ Refresh : 4096 cycles/64ms
∙ Programmable data transfer mode
- CAS Latency (1,2,3)
- Burst Length (1,2,4,8,Full Page)
- Data scramble (sequential, interleave)
∙ CBR auto-refresh, Self-refresh capability
∙ Packages:
44-pin 400mil plastic TSOP (TypeII) (TSOPII44-P-400-0.80-1K)(Product : MSM56V16800F-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
Access Time (Max.)
Family Max.
Frequency tAC2 tAC3
MSM56V16800F-8A 125MHz 6ns 6ns
MSM56V16800F-10 100MHz 9ns 9ns
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PIN CONFIGURATION (TOP VIEW)
Pin Name Function Pin Name Function
CLK System Clock DQM Data Input/ Output Musk
CS Chip Select DQi Data Input/ Output
CKE Clock Enable VCC Power Supply (3.3V)
A0–A10 Address VSS Ground (0V)
A11 Bank Select Address VCCQ Data Output Power Supply (3.3V)
RAS Row Address Strobe VSSQ Data Output Ground (0V)
CAS Column Address Strobe NC No Connection
WE Write Enable
Note : The same power supply voltage must be provided to every VCC pin and VCCQ pin.
The same GND voltage level must be provided to every VSS pin and VSSQ pin.
44-Pin Plastic TSOP
(K Type)
1
2
3
4
5
9
10
11
12
13
42
41
40
39
38
DQ1
DQ2
DQ3
VCC VSS
DQ8
DQ7
NC NC
DQM
A
9
6
7
8
14
15
RA
S
DQ4
19
20
21
22 23
A0
A1
A2
A3
A11 16
17
18
24
25
C
S
W
E
A10
CA
S
44
43
DQ6
DQ5
37
36
32
31
30
29
28
A
8
A
7
A
6
A
5
A
4
35
34
33 CLK
CKE
NC
27
26
VSS
VCC
NC
VCCQ
VSSQV
SSQ
VCCQ
NC
VSSQ
VCCQ
VSSQ
VCCQ
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PIN DESCRIPTION
CLK Fetches all inputs at t he “H” edge.
CS Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE,
DQM.
CKE Masks system clock to deactivate the subsequent CLK operation.
If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is
deactivated. CKE should be asserted at least one cycle prior to a new command.
Address Row & column multiplexed.
Row address : RA0 – RA10
Column Address : CA0 – CA8
A11 Slects bank to be activated during row address latch time and selects bank for precharge and
read/write during column address latch time. A11=”L” : Bank A, A11=”H” : Bank B
RAS
CAS
WE
Functionality depends on the combination. For details, see the function truth table.
DQM Masks the read data of two clocks later when DQM is set “H” at the “H” edge of the clock signal.
Masks the write data of the same clock when DQM is set “H” at the “H” edge of the clock signal.
DQi Data inputs/outputs are multiplexed on the same pin.
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BLOCK DIAGRAM
Timing
Register
Column
Decoders
Sense
Amplifiers D
Q
1
- DQ8
RA
S
CA
S
A0
-
A11
Progra-
ming
Register
Bank
Controller
Latency
& Burst
Controller
Internal
Col.
Address
Counter
I/O
C
ontroller
Column
Address
Buffers
Internal
Row
Address
Counter
Row
Address
Buffers
8
Row
Decoders
Row
Decoders
12 Word
Drivers
Word
Drivers
8Mb
Memory
Cells
8Mb
Memory
Cells
Read
Data
Register
Output
Buffers
Column
Decoders
Sense
Amplifiers
Input
Data
Register
Input
Buffers
CK
E
CL
K
C
S
W
E
D
Q
M
A11
9
12
8
88
8
8
9
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ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to VSS)
Parameter Symbol Value Unit
Voltage on Any Pin Relative to VSS VIN, VOUT –0.5 to VCC+ 0.5 V
VCC Supply Voltage VCC , VCCQ –0.5 to 4.6 V
Storage Temperature Tstg –55 to 150 °C
Powe r Dissipation PD* 600 mW
Short Circuit Output Current IOS 50 mA
Operating Temperature Topr 0 to 70 °C
*: Ta = 25°C
RECOMM ENDED OPERATIING CONDITIONS
(Voltages referenced to VSS = 0V)
Parameter Symbol Min. Typ. Max. Unit
Power Supply Vo ltage VCC, VCCQ 3.0 3.3 3.6 V
Input High Voltage VIH 2.0 VCC + 0.2 V
Input Low Voltage VIL − 0.3 0.8 V
PIN CAPACITANCE
(VBIAS = 1.4V, Ta = 25°C, f = 1 MHz)
Parameter Symbol Min. Max. Unit
Input Capacitance (CLK) CCLK 2.5 4 pF
Input Capacitance
(RAS, CAS, WE, CS, CKE, DQM, A0 - A11) CIN 2.5 5 pF
Input/Output Capacitance (DQ1 - DQ8) COUT 46.5pF
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DC CHARACTERISTICS
MSM56V16800 Unit Note
Condition F-8A F-10
Parameter Symbol
Bank CKE Others Min. Max. Min. Max.
Output High
Voltage VOH
IOH =
−2.0mA 2.4 2.4 V
Output Low
Voltage VOL
IOL =2.0mA 0.4 0.4 V
Input Leakage
Current ILI − 10 10 − 10 10 µA
Output Leakage
Current ILO − 10 10 − 10 10 µA
ICC1 One Bank
Active CKE≥VIH
tCC = Min.
tRC = Min.
No Burst 80 70 mA 1,2
Average Power
Supply Current
(Operating) ICC1D
Both
Banks
Active CKE≥VIH
tCC = Min.
tRC = Min.
tRRD = Min.
No Burst
115 95 mA 1,2
Power Supply
Current
(Standby) ICC2
Both
Banks
Precharge CKE≥VIH tCC = Min. 35 30 mA 3
Average Power
Supply Current
(Clock
Suspension)
ICC3S
Both
Banks
Active CKE≤VIL tCC = Min. 33mA 2
Average Power
Supply Current
(Active Standby) ICC3 One Bank
Active CKE≥VIH tCC = Min. 40 35 mA 3
Power Supply
Current (Burst) ICC4 Both
Banks
Active CKE≥VIH tCC = Min. 125 100 mA 1,2
Power Supply
Current
(Auto-Refresh) ICC5 One Bank
Active CKE≥VIH tCC = Min.
tRC = Min. 80 70 mA 2
Average Power
Supply Current
(Self-Refresh) ICC6 Both
Banks
Precharge CKE≤ VIL tCC = Min. 22mA
Average Power
Supply Current
(Power Down) ICC7 Both
Banks
Precharge CKE≤VIL tCC = Min. 22mA
Notes: 1. Measured with outputs open.
2. The address and data can be changed once or left unchanged during one cycle.
3. The address and data can be changed once or left unchanged during two cycle.
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Mode Set Address K eys
CAS Latency Burst Type Burst Length
A6 A5 A4 CL A3 BT A2 A1 A0 BT = 0 BT = 1
0 0 0 Reserved 0 Sequential 0 0 0 1 1
001 1 1Interleave001 2 2
010 2 010 4 4
011 3 011 8 8
1 0 0 Reserved 1 0 0 Reserved Reserved
1 0 1 Reserved 1 0 1 Reserved Reserved
1 1 0 Reserved 1 1 0 Reserved Reserved
1 1 1 Reserved 1 1 1 Full Page Reserved
Notes: A7, A8, A9, A10 and A11 should stay “L” during mode set cycle.
MSM56V16800F support two methods of Power on Sequence.
POWER ON SEQUENCE 1
1. With inputs in NOP state, turn on the power supply and start the system clock.
2. After the VCC voltage has reached the specified level, pause for 200µs or more with the input kept in
NOP state.
3. Issue the precharge all bank command.
4. Apply a CBR auto-refresh eight or more times.
5. Enter the mode register setting command.
POWER ON SEQUENCE 2
1. With inputs in NOP state, turn on the power supply and start the system clock.
2. After the VCC voltage has reached the specified level, pause for 200µs or more with the input kept in
NOP state.
3. Issue the precharge all bank command.
4. Enter the mode register setting command.
5. Apply a CBR auto-refresh eight or more times.
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AC CHARACTERISTICS (1/2) Note1,2
MSM56V16800
F-8A MSM56V16800
F-10
Parameter Symbol Min. Max. Min. Max. Unit Note
CL = 3 tCC3 810 ns
CL = 2 tCC2 10 15 nsCloc k Cycle Time
CL = 1 tCC1 20 30 ns
CL = 3 tAC3 69ns 3,4
CL = 2 tAC2 69ns 3,4
Access Time from
Clock CL = 1 tAC1 16 27 ns 3,4
Clock High Pulse Time tCH 33ns 4
Clock Low Pulse Time tCL 33ns 4
Input Setup Time tSI 23ns
Input Hold Time tHI 11ns
Output Low Im pedanc e Time
from Clock tOLZ 33ns
Output High Impedance Time
from Clock tOHZ 88ns
Output Hold from Clock tOH 33ns 3
Random Read or Write Cycle Time tRC 70 90 ns
RAS Precharge Time tRP 20 30 ns
RAS Pulse Width tRAS 48 100,000 60 100,000 ns
RAS to CAS De la y Time tRCD 20 30 ns
Write Recovery Time tWR 815 ns
RAS to CAS Bank Active Delay
Time tRRD 20 20 ns
Refresh Time tREF 64 64 ms
Power-down Exit setup Time tRDE tSI +1CLK tSI +1CLK ns
Input Level Transition Time tT33ns
CAS to CAS Delay Time (Min.) tCCD 11Cycle
Clock Disable Time from CKE tCKE 11Cycle
Data Output High Impedance Time
from DQM tDOZ 22Cycle
Dada Input Mask Time from DQM tDOD 00Cycle
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AC CHARACTERISTICS (2/2) Note1,2
MSM56V16800
F-8A MSM56V16800
F-10
Parameter Symbol Min. Max. Min. Max. Unit Note
Data Input Mask Time from Write
Command tDWD 00Cycle
Data Output High Impedance Time
from Precharge Command tROH CL CL Cycle
Active Command Input Time from
Mode Register Set Command Input
(Min.) tMRD 22Cycle
Write Command Input Time from
Outpput tOWD 22Cycle
Notes: 1. AC measurements assume that tT = 1ns.
2. The reference level for timing of input signals is 1.4V.
3. Output load.
4. The access time is defined at 1.4V.
5. If tT is longer than 1ns, then the reference level for timing of input signals is VIH and VIL.
Output Z=50Ω
50pF (External Load)
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TIMING CHART
Read & Write Cycle (Same Bank) @CAS Latency=
==
=2, Burst Length=
==
=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
C
S
R
AS
C
AS
ADDR
A11
A10
DQ
W
E
DQM
tOH
Ra Ca0
tRP
tRC
Qa1
Cb0Rb
RbRa
Qa0 Qa2 Qa3 Db0 Db1 Db2 Db3
tAC tOHZ tWR
Row ActiveRead Command Prechar
g
e Command Row Act ive
Write Command Prechar
g
e Command
tRCD
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Single Bit Read-Write-Read Cycle (Same Page) @CAS Latency=
==
=2, Burs t Len gth= 4
CLK
CKE
C
S
R
AS
C
AS
ADDR
A11
A10
DQ
W
E
DQM
Row Active
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
High
tOLZ
Db
tSI
Qc
tHI
Qa
tOH
Ra
lOWD
BS BS BSBSBS
Ra CcCbCa
tOHZ
tAC tHI
tSI
tSI
tHI
tHI
tSI
tSI
tHI
tHI
tSI
ICCD
tSI
tCL
tCC
tCH
Read Command
Write Command
Read Command
Prechar
g
e Command
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*Note: 1. When CS is set “High” at a clock tra nsition fro m “Low” to “High”, all inp uts e xcept CKE and DQM
are invalid.
2. When issuing an active, read or write command, the bank is selected by A11.
A11 Active, read or write
0 Bank A
1 Bank B
3. The auto prechar g e fun ction is en abled or disabled by the A10 inpu t when the read or write com m and
is issued.
A10 A11 Operation
0 0 After the end of burst, bank A holds the idle status.
1 0 After the end of burst, bank A is precharged automatically.
0 1 After the end of burst, bank B holds the idle status.
1 1 After the end of burst, bank B is precharged automatically.
4. When issuing a prech arge comm and, the bank to be prechar ged is s elected by the A10 an d A11 inputs.
A10 A11 Operation
0 0 Bank A is precharged.
0 1 Bank B is precharged.
1 X Both banks A and B are precharged.
5. The input data and the write command are latched by the same clock (Write latency=0).
6. The output is forced to high impedance by (1CLK+ tOHZ ) after DQM entry.
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Page Read & Write Cycle (Same Bank) @CAS Late ncy=
==
=2, Burs t Len gth= 4
*Note: 1. To write data before a burst read ends, DQM should be asserted three cycles prior to the write
command to avoid bus contention.
2. To assert row precharge before a burst write ends, wait tWR after the last write data input.
Input data during the precharge input cycle will be masked internally.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
C
S
R
AS
C
AS
ADDR
A11
A10
DQ
W
E
DQM
Read Command
Read Command Write Command
Write Command
Prechar
g
e Command
Qa0 Qa1 Qb0 Qb1 Dc0 Dc1 Dd0
Cc0 Cd0Ca0 Cb0
tWR
ICCD
∗Note 2
∗Note 1
Bank A Active
lOWD
High
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Read & Write Cycle with Auto Precharge @ Burst Length=
==
=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
C
S
R
AS
C
AS
ADDR
A11
A10
DQ
W
E
DQM
A
-Bank Prechar
g
e Start
Row Active
(B-Bank) A Bank Read with
Auto Precharge
B Bank Write with
Auto Precharge B Bank Prec harge
Start Point
A
-Bank Prechar
g
e Start
A
-Bank Prechar
g
e Start
High
Ra
tRRD
Qa0
tWR
Rb
Ra
Rb
Ca
Cb
Qa1
Qa2 Qa3 Db0 Db1 Db2 Db3
Db0 Db1 Db2 Db3 Qa0
Qa1
Qa2 Qa3
Qa0
Qa1
Qa2 Qa3 Db0 Db1 Db2 Db3
C
AS Latenc
y
=2
C
AS Latenc
y
=3
C
AS Latenc
y
=1
Row Active
(A-Bank)
DQ
DQ
DQM
DQM
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Bank Interleave Random Row Read Cycle @CAS Latency=2, Burst Length=4
CLK
CKE
C
S
R
AS
C
AS
ADDR
A11
A10
DQ
W
E
DQM
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
RAa
CAa
RBb CBb RAc CAc
RAa
RBb RAc
QAa0
QAa1 QAa2 QAa3 QBb1
QBb2 QBb3 QBb4 QAc0
QAc1 QAc2 QAc3
Row Active
(A-Bank) Read Command
(A-Bank) Precharge Comm and
(A-Bank)
Row Active
(B-Bank) Read Command
(B-Bank)
Precharge Comm and
(B-Bank)
Row Active
(A-Bank)
Read Command
(A-Bank)
tRRD
tRC
High
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Bank Interleave Random Row Write Cycle @CAS Latency=2, Burst Length=4
CLK
CKE
C
S
R
AS
C
AS
ADDR
A11
A10
DQ
W
E
DQM
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
RAa
CAa
RBb CBb RAc CAc
RAa
RBb RAc
DAa0
DAa1 DAa2 DAa3
Row Active
(A-Bank) Write Command
(A-Bank)
Precharge Comm and
(A-Bank)
Row Active
(B-Bank)
Write Command
(B-Bank)
Precharge Comm and
(B-Bank)
Row Active
(A-Bank)
Write Command
(A-Bank)
DBb0
DBb1 DBb2 DBb3 DAc0
DAc1
High
Precharge Comm and
(A-Bank)
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Bank Interleave Page Read Cycle @CAS Latency=2, Burst Length=4
*Note: 1. CS is ignored when RAS, CAS and WE are high at the same cycle.
CLK
CKE
C
S
R
AS
C
AS
ADDR
A11
A10
DQ
W
E
DQM
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
RAa
CAa
RBb CBb CAc CBd CAe
RAa
RBb
QAa0 QAa1 QAa2 QAa3 QBb0
QBb1 QBb2 QBb3 QAc0
QAc1 QBd0 QBd1 QAe0
QAe1
∗Note 1
Row Active
(A-Bank) Read Command
(A-Bank)
Row Active
(B-Bank)
Read Command
(B-Bank)
Precharge Comm and
(A-Bank)
Read Command
(A-Bank) Read Command
(A-Bank)
Read Command
(B-Bank)
IROH
High
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Bank Interleave Page Write Cycle @CAS Latency=2, Burst Length=
==
=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
C
S
R
AS
C
AS
ADDR
A11
A10
DQ
W
E
DQM
Row Active
(A-Bank) Row Active
(B-Bank)
Write Command
(A-Bank)
Precharge Command
(Both Bank)
High
RAa CAa
RAa RBb
RBb CBd
DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0
Write Command
(B-Bank) Write Command
(A-Bank)
Write Command
(B-Bank)
DAa2DAa1DAa0
CAcCBb
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Bank Interleave Random Row Read/Write Cycle @CAS Latency=2, Burst Length=4
CLK
CKE
C
S
R
AS
C
AS
ADDR
A11
A10
DQ
W
E
DQM
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
RAa CAa RBb CBb RAc CAc
RAa RBb RAc
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QAc2 QAc3
Row Active
(A-Bank)Read Command
(A-Bank) Precharge Command
(A-Bank)
Row Active
(B-Bank) Write Command
(B-Bank) Row Active
(A-Bank)
Read Command
(A-Bank)
High
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Bank Interleave Page Read/Write Cycle @CAS Latency=2, Burst Length=4
CLK
CKE
C
S
R
AS
C
AS
ADDR
A11
A10
DQ
W
E
DQM
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CAa0 CBb0 CAc0
QAa0 QAa1 QAa2 QAa3
Read Command
(A-Bank) Write Command
(B-Bank) Read Com mand
(A-Bank)
DBb0 DBb1 DBb2 DBb3 QAc0 QAc1
High
QAc2 QAc3
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Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4
*Note: 1. When Clock Suspension is asserted, the next clock cycle is ignored.
2. When DQM are asserted, the read data after two clock cycles is masked.
3. When DQM are asserted, the write data in the same clock cycle is masked.
CLK
CKE
C
S
R
AS
C
AS
ADDR
A11
A10
DQ
W
E
DQM
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Ra Ca Cb Cc
Ra
Qa0 Qa1 Qa2 Qb0 Qb1 Dc0
∗Note 1
Row Active
Read Command
CLOCK
Suspension
Read DQM CLOCK Suspension
Read Command
Write
Command
Read DQM
∗Note 1
∗Note 2 ∗Note 3
tOHZ
Write
DQM Write DQM
tOHZ
Dc2
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Read to Write Cycle (Same Bank) @CAS Latency=2, Burst Length=4
*Note: 1. In Case CAS latency is 3, READ can be interrupted by WRITE.
The minimum command interval is [burst length + 1] c ycles.
DQM must be high at least 3 clocks prior to the write command.
CLK
CKE
C
S
R
AS
C
AS
ADDR
A11
A10
DQ
W
E
DQM
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Ra Ca0 Cb0
Ra
Db0 Db1
∗Note 1
Row Active
Read Command Write Command
Precharge Command
tWR
tRCD
Db2 Db3Da0
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Semiconductor MSM56V16800F
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Read Interruption by Precharge Command @Burst Length=
==
=8
*Note: 1. if row precharge is asserted before a burst read ends, then the read data will not output after lROH
equals CAS latency.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
C
S
R
AS
C
AS
ADDR
A11
A10
DQ
W
E
DQM
CAS Latenc
y
=2
CAS Latenc
y
=3
Ra
Ca
∗Note 1
Qa0
Qa1
Ra
Qa2
∗Note 1
Qa3
Qa4 Qa5
Qa0
Qa1 Qa2 Qa3
Qa4 Qa5
∗Note 1
Qa0
Qa1 Qa2 Qa3
Qa4
Row Active Read Command Prec harge Command
lROH
lROH
Qa5
lROH
High
CAS Latenc
y
=1
DQ
DQM
DQ
DQM
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Semiconductor MSM56V16800F
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Burst Sto p Command @Burst Length=8
CLK
CKE
C
S
R
AS
C
AS
ADDR
A11
A10
DQ
W
E
DQM
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CAS Latenc
y
=2
CAS Latenc
y
=3
Qa0
Qa1 Qa2 Qa3
Qa4
Qa0
Qa1 Qa2 Qa3
Qa4
Qa0
Qa1 Qa2 Qa3
Qa4
CAS Latenc
y
=1
Read Command
Cb
Qb0
Qb1 Qb2 Qb3
Qb4
Qb0
Qb1 Qb2 Qb3
Qb4
Qb0
Qb1 Qb2 Qb3
Qb4
Burst Sto
p
Command Write Command Burst S top Com mand
High
Ca
DQ
DQM
DQ
DQM
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Power Down Mode @CAS Lat e ncy=2, Burst Length=4
*Note: 1. When both banks are in precharge state, and if CKE is set low, then the MSM56V16800F enters
power-down mode and maintains the mode while CKE is low.
2. T o release the circuit from power-down mode, CKE has to be set high for longer than tPDE (tSI + 1CL K).
CLK
CKE
C
S
R
AS
C
AS
ADDR
A11
A10
DQ
W
E
DQM
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Ra Ca
Ra
Qa0 Qa1 Qa2
∗Note 2
Power-down
Entry Row
Active
Power-down
Exit Precharge Comm and
Read Command
Clock
Suspens i on E xit
tSI ∗Note 1
Clock
Suspension
Entry
tPDE tSI
tSI
tREF (min.)
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Semiconductor MSM56V16800F
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Self Refresh Cycle
0
1
2
CLK
CKE
C
S
R
AS
C
AS
ADDR
A11
A10
DQ
W
E
DQM
Ra
BS
Ra
Self Refresh Entry Self Refresh Exit Row Active
tSI
tRC
Hi-Z
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Mode Register Set Cycle Auto Refresh Cycle
0
1
2
3
4
5
6
7
8
9
10
11
CLK
CKE
C
S
R
AS
C
AS
ADDR
DQ
W
E
DQM
New Command
lMRD
Auto Refresh
tRC
MRS Auto Refresh
Key Ra
Hi - Z Hi - Z
High High
0
1
2
3
4
5
6
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FUNCTION TRUTH TABLE (Table 1) (1/2)
Current
State1CS RAS CAS WE BA ADDR Action
HXXXX X NOP
LHHHX X NOP
LHHLBA X ILLEGAL 2
LHLXBA CAILLEGAL 2
L L H H BA RA Row Act ive
L L H L BA A10 NOP 4
LLLHX XAuto-Refresh or Self-Refresh 5
Idle
LLLLLOP CodeMode Re gist er Write
HXXXX X NOP
LHHXX X NOP
LHLHBACA, A10Read
L H L L BA CA, A10 Write
LLHHBARAILLEGAL 2
L L H L BA A10 Precharge
Row Active
LLLXX XILLEGAL
H X X X X X NOP (Continue Row Active af ter Bur st ends)
L H H H X X NOP (Continue Row Active after Burst ends)
L H H L X X Term Burst --> Row Active
LHLHBACA, A10
Term Burst, start new Burst Read 3
L H L L BA CA, A10 Term Burst, start new Burst Write 3
LLHHBARAILLEGAL 2
L L H L BA A10 Term Bur st, execute Row Prec harge
Read
LLLXX XILLEGAL
H X X X X X NOP (Continue Row Active af ter Bur st ends)
L H H H X X NOP (Continue Row Active after Burst ends)
L H H L X X Term Burst --> Row Active
LHLHBACA, A10
Term Burst, start new Burst Read 3
L H L L BA CA, A10 Term Burst, start new Burst Write 3
LLHHBARAILLEGAL 2
L L H L BA A10 Term Burst , execute Row Precharge 3
Write
LLLXX XILLEGAL
H X X X X X NOP (Continue Burst to End and e nter Row Precharge)
L H H H X X NOP (Continue Burst to End and ente r Row Precharge)
LHHLBA X ILLEGAL 2
LHLHBACA, A10
ILLEGAL 2
L H L L X X ILLEGAL
L L H X BA RA, A10 ILLEGAL 2
Read with
Auto
Precharge
LLLXX XILLEGAL
H X X X X X NOP (Continue Burst to End and enter Row Precharge)
L H H H X X NOP (Continue Burst to End and enter Row Precharge)
LHHLBA X ILLEGAL 2
Write with
Auto
Precharge
LHLHBACA, A10
ILLEGAL 2
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FUNCTION TRUTH TAB LE (Table 2) (2/2)
Current
State1CS RAS CAS WE BA ADDR Action
L H L L X X ILLEGAL
L L H X BA RA, A10 ILLEGAL 2
Write with
Auto
Precharge LLLXX XILLEGAL
HXXXX X NOP --> Idle after tRP
LHHHX X NOP --> Idle after tRP
LHHLBA X ILLEGAL 2
LHLXBA CAILLEGAL 2
LLHHBARAILLEGAL 2
L L H L BA A10 NOP 4
Precharge
LLLXX XILLEGAL
HXXXX X NOP
LHHHX X NOP
LHHLBA X ILLEGAL 2
LHLXBA CAILLEGAL 2
LLHHBARAILLEGAL 2
L L H L BA A10 ILLEGAL 2
Write
Recovery
LLLXX XILLEGAL
HXXXX X NOP --> Row Active after tRCD
LHHHX X NOP --> Row Active after tRCD
LHHLBA X ILLEGAL 2
LHLXBA CAILLEGAL 2
LLHHBARAILLEGAL 2
L L H L BA A10 ILLEGAL 2
Row Acti ve
LLLXX XILLEGAL
HXXXX X NOP --> Idle after tRC
LHHXX X NOP --> Idle after tRC
L H L X X X ILLEGAL
L L H X X X ILLEGAL
Refresh
LLLXX XILLEGAL
HXXXX X NOP
LHHHX X NOP
L H H L X X ILLEGAL
L H L X X X ILLEGAL
Mode
Register
Access
L L X X X X ILLEGAL
ABBREVIATIONS
RA = Row Address BA = Bank Address NOP = No OPeration command
CA = Column Address AP = Auto Precharge
∗Notes :1. All inputs are enabled when CKE is set high for at least 1 cycle prior to the inputs.
2. Illegal to bank in specified state, but may be legal in some cases depending on the state of bank
selection.
3. Satisfy the timing of lCCD and tWR to prevent bus contention.
4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A10.
5. Illegal if any bank is not idle.
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FUNCTION TRUTH TAB LE for CKE (Table 2)
Current State (n) CKEn-1 CKEn CS RAS CAS WE ADDR Action
H X XXXX XINVALID
L H H X X X X Exit Self Refresh --> ABI
L H L H H H X E xit Self Refresh --> ABI
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L L X X X ILLEGAL
Self Refresh
L L X X X X X NOP (Maintain Self Refresh)
H X XXXX XINVALID
L H H X X X X Exit Power Down --> ABI
L H L H H H X Exit Power Down --> ABI
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
LHLLXXX
ILLEGAL 6
Power Down
L L X X X X X NOP (Continue power down mode)
H H X X X X X Refer to Table 1
H L H X X X X Enter Power Down
H L L H H H X Enter Power Down
H L L H H L X ILLEGAL
H L L H L X X ILLEGAL
H L L L H L X ILLEGAL
H L L L L H X Enter Self Refresh
H L LLLL XILLEGAL
All Banks Idle 6
(ABI)
L L XXXX XNOP
H H X X X X X Refer to Operations in Table 1
H L X X X X X Begin Clock Suspend Next Cycle
L H X X X X X Enable Clock of Next Cycle
Any State Other
than Listed
Above
L L X X X X X Continue Clock Suspension
*Notes :6. Power-down and self-refresh can be entered only when all the banks are in an idle state.
FEDD56V16800F-01
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MSM56V16800F
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NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an explanation
for the standard action and performance of the product. When planning to use the product, please ensure that
the external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted
by us in connection with the use of the product and/or the information and drawings contained herein. No
responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for use in any system or application that requires special or
enhanced quality and reliability characteristics nor in any system or application where the failure of such
system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products and
will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2001 Oki Electric Industry Co., Ltd.
