General Description
The MAX691A/MAX693A/MAX800L/MAX800M micro-
processor (μP) supervisory circuits are pin-compatible
upgrades to the MAX691, MAX693, and MAX695. They
improve performance with 30μA supply current, 200ms
typ reset active delay on power-up, and 6ns chip-enable
propagation delay. Features include write protection
of CMOS RAM or EEPROM, separate watchdog out-
puts, backup-battery switchover, and a RESET output
that is valid with VCC down to 1V. The MAX691A/
MAX800L have a 4.65V typical reset-threshold voltage,
and the MAX693A/MAX800Ms’ reset threshold is 4.4V
typical. The MAX800L/MAX800M guarantee power-fail
accuracies to ±2%.
Applications
● Computers
● Controllers
● Intelligent Instruments
● Critical μP Power Monitoring
Features
● 200ms Power-OK/Reset Timeout Period
● 1μA Standby Current, 30μA Operating Current
● On-Board Gating of Chip-Enable Signals, 10ns max
Delay
● MaxCap® or SuperCap Compatible
● Guaranteed RESET Assertion to VCC = +1V
● Voltage Monitor for Power-Fail or Low-Battery
Warning
● Power-Fail Accuracy Guaranteed to ±2%
(MAX800L/M)
● Available in 16-Pin Narrow SO, Plastic DIP, and
TSSOP Packages
Ordering Information continued at end of data sheet.
19-0094; Rev 12; 9/14
MaxCap is a registered trademark of Kanthal Globar, Inc.
*Dice are specified at TA = +25°C, DC parameters only.
Devices in PDIP, SO, and TSSOP packages are available in
both leaded and lead-free packaging. Specify lead free by add-
ing the + symbol at the end of the part number when ordering.
Lead free not available for CERDIP package.
PART TEMP RANGE PIN-
PACKAGE
MAX691ACUE -0°C to +70°C 16 TSSOP
MAX691ACSE -0°C to +70°C 16 Narrow SO
MAX691ACWE -0°C to +70°C 16 Wide SO
MAX691ACPE -0°C to +70°C 16 Plastic DIP
MAX691AC/D -0°C to +70°C Dice*
MAX691AEUE -0°C to +70°C 16 TSSOP
MAX691AESE -40°C to +85°C 16 Narrow SO
MAX691AEWE -40°C to +85°C 16 Wide SO
MAX691AEPE -40°C to +85°C 16 Plastic DIP
MAX691A
MAX693A
MAX800L
MAX800M
VOUT
VCC BATT ON
CE OUT
CE IN
WDI
PFO
RESET
VBATT
PFI
GND
OSC IN
OSC SEL
1
9
4
7
8
ADDRESS
DECODE
AUDIBLE
ALARM
5V
REGULATOR
+8V
0.1µF
CMOS RAM
2
12
11
10
15
13
5
3
A0-A15
I/O
NMI
RESET
µP
LOW LINE WDO
SYSTEM STATUS INDICATORS
NO
CONNECTION
0.47F*
1N4148
*MaxCap
6 14
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
RESET
RESET
WDO
CE IN
GND
VCC
VOUT
VBATT
TOP VIEW
MAX691A
MAX693A
MAX800L
MAX800M CE OUT
WDI
PFO
PFI
OSC SEL
OSC IN
LOW LINE
BATT ON
DIP/SO/TSSOP
MAX691A/MAX693A/
MAX800L/MAX800M
Microprocessor Supervisory Circuits
Ordering Information
Typical Operating Circuit
Pin Conguration
Terminal Voltage (with respect to GND)
VCC......................................................................-0.3V to +6V
VVBATT.................................................................-0.3V to +6V
All Other Inputs....................................-0.3V to (VOUT + 0.3V)
Input Current
VCC Peak..........................................................................1.0A
VCC Continuous............................................................250mA
VBATT Peak..................................................................250mA
VBATT Continuous..........................................................25mA
GND, BATT ON.............................................................100mA
All Other Outputs ............................................................25mA
Continuous Power Dissipation (TA = +70°C)
TSSOP (derate 6.70mW/°C above +70°C)..................533mW
Narrow SO (derate 8.70mW/°C above +70°C) ...........696mW
Wide SO (derate 9.52mW/°C above +70°C)...............762mW
Plastic DIP (derate 10.53mW/°C above +70°C) ..........842mW
CERDIP (derate 10.00mW/°C above +70°C)..............800mW
Operating Temperature Ranges
MAX69_AC_ _/MAX800_C_ _............................0°C to +70°C
MAX69_AE_ _/MAX800_E_ _.........................-40°C to +85°C
MAX69_AMJE................................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
(MAX691A, MAX800L: VCC = +4.75V to +5.5V; MAX693A, MAX800M: VCC = +4.5V to +5.5V; VVBATT = 2.8V, TA = TMIN to TMAX,
unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Operating Voltage Range,
VCC, VVBATT (Note 1) 05.5 V
VOUT Output VCC = 4.5V
IOUT = 25mA VCC - 0.02 VCC - 0.05
V
IOUT = 250mA
MAX69_AC VCC - 0.2 VCC - 0.3
MAX69_AE,
MAX800_C/E VCC - 0.2 VCC -
0.35
MAX69_A/M VCC - 0.40
IOUT = 210mA MAX69_AC/AE,
MAX800_C/E VCC -
0.17 VCC -
0.3V
VCC-to-VOUT On-Resistance VCC = 4.5V
MAX69_AC, MAX800_C 0.8 1.2
ΩMAX69_AE, MAX800_E 0.8 1.4
MAX69_A/M 0.8 1.6
VOUT in Battery-Backup
Mode
VVBATT = 4.5V, IOUT = 20mA VVBATT - 0.3
VVVBATT = 2.8V, IOUT = 10mA VVBATT - 0.25
VVBATT = 2.0V, IOUT = 5mA VVBATT - 0.15
VBATT-to-VOUT
On-Resistance
VVBATT = 4.5V 15
ΩVVBATT = 2.8V 25
VVBATT = 2.0V 30
Supply Current in Normal
Operating Mode (excludes
IOUT)VCC > VVBATT - 1V 30 100 µA
Supply Current in Battery-
Backup Mode (excludes
IOUT) (Note 2)
VCC < VVBATT -
1.2V, VVBATT =
2.8V
TA = +25°C 0.04 1µA
TA = TMIN + TMIN 5
VBATT Standby Current
(Note 3) VVBATT + 0.2V ≤
VCC
TA = +25°C -0.1 0.02 µA
TA = TMIN + TMIN -1.0 0.02
Battery Switchover
Threshold
Power-up VVBATT + 0.3 V
Power-down VVBATT - 0.3
MAX691A/MAX693A/
MAX800L/MAX800M
Microprocessor Supervisory Circuits
www.maximintegrated.com Maxim Integrated
│
2
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(MAX691A, MAX800L: VCC = +4.75V to +5.5V; MAX693A, MAX800M: VCC = +4.5V to +5.5V; VVBATT = 2.8V, TA = TMIN to TMAX,
unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Battery Switchover
Hysteresis 60 mV
BATT ON Output Low
Voltage
ISINK = 3.2mA 0.1 0.4 V
ISINK = 25mA 0.7 1.5
BATT ON Output
Short-Circuit Current
Sink current 60 100 mA
Source current 115 100 µA
RESET AND WATCHDOG TIMER
Reset Threshold Voltage
MAX691A, MAX800L 4.50 4.65 4.75
V
MAX693A, MAX800M 4.25 4.40 4.50
MAX800L, TA = +25°C, VCC falling 4.55 4.70
MAX800M, TA = +25°C, VCC falling 4.30 4.45
Reset Threshold Hysteresis 15 mV
VCC to RESET Delay Power-down 80 µs
LOW LINE-to-RESET Delay 800 ns
Reset Active Timeout Period,
Internal Oscillator Power-up 140 200 280 ms
Reset Active Timeout Period,
External Clock (Note 4) Power-up 2048 Clock
Cycles
Watchdog Timeout Period,
Internal Oscillator
Long period 1.0 1.6 2.25 sec
Short period 70 100 140 ms
Watchdog Timeout Period,
External Clock (Note 4)
Long period 4096 Clock
Cycles
Short period 1024
Minimum Watchdog Input
Pulse Width VIL = 0.8V, VIH = 0.75 x VCC 100 ns
RESET Output Voltage
ISINK = 50μA, VCC = 1V, VBATT = 0V, VCC falling 0.004 0.3
VISINK = 3.2mA, VCC = 4.25V 0.1 0.4
ISOURCE = 1.6mA, VCC = 5V 3.5
RESET Output
Short-Circuit Current Output source current 7 20 mA
RESET Output Voltage Low
(Note 5) ISINK = 3.2mA 0.1 0.4 V
LOW LINE Output Voltage ISINK = 3.2mA, VCC = 4.25V 0.4 V
ISOURCE = 1μA, VCC = 5V 3.5
LOW LINE Output
Short-Circuit Current Output source current 115 100 µA
WDO Output Voltage ISINK = 3.2mA 0.4
ISOURCE = 500μA, VCC = 5V 3.5
WDO Output
Short-Circuit Current Output source current 3 10 mA
WDI Threshold Voltage
(Note 6)
VIH 0.75 x VCC V
VIL 0.8
WDI Input Current WDI = 0V -50 -10 µA
WDI = VOUT 20 50
MAX691A/MAX693A/
MAX800L/MAX800M
Microprocessor Supervisory Circuits
www.maximintegrated.com Maxim Integrated
│
3
Electrical Characteristics (continued)
(MAX691A, MAX800L: VCC = +4.75V to +5.5V; MAX693A, MAX800M: VCC = +4.5V to +5.5V; VVBATT = 2.8V, TA = TMIN to TMAX,
unless otherwise noted.
Note 1: Either VCC or VBATT can go to 0V, if the other is greater than 2.0V.
Note 2: The supply current drawn by the MAX691A/MAX800L/MAX800M from the battery excluding IOUT typically goes to 10μA
when (VBATT - 1V) < VCC < VBATT. In most applications, this is a brief period as VCC falls through this region.
Note 3: “+” = battery-discharging current, “--” = battery-charging current.
Note 4: Although presented as typical values, the number of clock cycles for the reset and watchdog timeout periods are fixed and
do not vary with process or temperature.
Note 5: RESET is an open-drain output and sinks current only.
Note 6: WDI is internally connected to a voltage divider between VOUT and GND. If unconnected, WDI is driven to 1.6V (typ), dis-
abling the watchdog function.
Note 7: The chip-enable resistance is tested with VCC = +4.75V for the MAX691A/MAX800L and VCC = +4.5V for the MAX693A/
MAX800M. CE IN = CE OUT = VCC/2.
Note 8: The chip-enable propagation delay is measured from the 50% point at CE IN to the 50% point at CE OUT.
PARAMETER CONDITIONS MIN TYP MAX UNITS
POWER-FAIL COMPARATOR
PFI Input Threshold MAX69_AC/AE/AM, VCC = 5V 1.2 1.25 1.3 V
MAX800_C/E, VCC = 5V 1.225 1.25 1.275
PFI Leakage Current ±0.01 ±25 nA
PFO Output Voltage ISINK = 3.2mA 0.4 V
ISOURCE = 1μA, VCC = 5V 3.5
PFO Output Short-Circuit
Current Output source current 115 100 µA
PFI-to-PFO Delay VIN = -20mV, VOD = 15mV 25 µs
VIN = 20mV, VOD = 15mV 60
CHIP-ENABLE GATING
CE IN Leakage Current Disable mode ±0.005 ±1 μA
CE IN-to- CE OUT
Resistance (Note 7) Enable mode 75 150 Ω
CE OUT Short-Circuit
Current (Reset Active) Disable mode, CE OUT = 0V 0.1 0.75 2.0 mA
CE IN-to- CE OUT
Propagation Delay (Note 8) 50Ω source impedance driver, CLOAD = 50pF 6 10 ns
CE OUT Output-Voltage
High (Reset Active)
VCC = 5V, IOUT = -100μA 3.5 V
VCC = 0V, VBATT = 2.8V, IOUT = 1μA 2.7
RESET-to-CE OUT Delay Power-down 12 µs
INTERNAL OSCILLATOR
OSC IN Leakage Current OSC SEL = 0V 0.10 ±5 µA
OSC IN Input Pullup Current OSC SEL = VOUT or oating, OSC IN = 0V 10 100 μA
OSC SEL Input Pullup
Current OSC SEL = 0V 10 100 μA
OSC IN Frequency Range OSC SEL = 0V 50 kHz
OSC IN External Oscillator
Threshold Voltage
VIH VOUT -
0.3 VOUT -
0.6 V
VIL 3.65 2.00
OSC IN Frequency with
External Capacitor OSC SEL = 0V, COSC = 47pF 100 kHz
MAX691A/MAX693A/
MAX800L/MAX800M
Microprocessor Supervisory Circuits
www.maximintegrated.com Maxim Integrated
│
4
Electrical Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
0
-60 120 150
BATTERY SUPPLY CURRENT
vs. TEMPERATURE
(BATTERY-BACKUP MODE)
2
MAX691A TOC-02
TEMPERATURE (°C)
BATTERY SUPPLY CURRENT (µA)
30
1
0.5
-30 0 90
1.5
60
VCC = 5V
VBATT = 2.8V
NO LOAD
120
-60 120 150 180
CHIP-ENABLE ON-RESISTANCE
vs. TEMPERATURE
100
MAX691A toc03
TEMPERATURE (°C)
CE ON-RESISTANCE (Ω)
30
60
40
-30 0 90
80
60
VCC = 4.75V
VBATT = 2.8V
VCE IN = VCC/2
20
5
-60 120 150
VBATT to VOUT ON-RESISTANCE
vs. TEMPERATURE
MAX691A toc04
TEMPERATURE (°C)
VBATT-to-VOUT ON-RESISTANCE (Ω)
30
10
-30 0 90
15
60
VCC = 0V
VBATT = 2.8V
VBATT = 2.0V
VBATT = 4.5V
1.2
0.6
-60 120 150
VCC to VOUT ON-RESISTANCE
vs. TEMPERATURE
MAX691A toc05
TEMPERATURE (°C)
VCC-to-VOUT ON-RESISTANCE (Ω)
30
0.8
-30 0 90
1.0
0.7
0.9
1.1
60
VCC = 5V,
VBATT = 0V
1.50
0
-60 120 150
PFI THRESHOLD
vs. TEMPERATURE
MAX691A toc06
TEMPERATURE (°C)
PFI THRESHOLD (V)
30
0.50
-30 0 90
1.00
0.25
0.75
1.25
60
VCC = +5V,
VBATT = 0V
NO LOAD ON PFO
4.75
4.30
-60 120 150
RESET THRESHOLD
vs. TEMPERATURE
MAX691A toc07
TEMPERATURE (°C)
RESET THRESHOLD (V)
30
4.45
-30 0 90
4.65
4.40
4.35
4.50
4.70
4.55
4.60
60
VBATT = 2.8V
MAX691A
MAX800L
MAX693A
MAX800M
36
26
-60 120 150
VCC SUPPLY CURRENT
vs. TEMPERATURE
(NORMAL OPERATING MODE)
34
MAX691A toc01
TEMPERATURE (°C)
VCC SUPPLY CURRENT (µA)
30
30
28
-30 0 90
32
60
VCC = 5V
VBATT = 2.8V
PFI, CE IN = 0V
600
0
-60 120 150
RESET OUTPUT RESISTANCE
vs. TEMPERATURE
MAX691A toc08
TEMPERATURE (°C)
RESET OUTPUT RESISTANCE (Ω)
30
200
-30 0 90
100
500
300
400
60
VCC = 5V, VBATT = 2.8V
SOURCING CURRENT
VCC = 0V, VBATT = 2.8V
SINKING CURRENT
-60 120 150
RESET DELAY
vs. TEMPERATURE
230
MAX691A toc09
TEMPERATURE (°C)
RESET DELAY (ms)
30
190
170
-30 0 90
210
220
180
200
60
VCC = 0V TO 5V STEP
VBATT = 2.8V
Maxim Integrated
│
5
www.maximintegrated.com
MAX691A/MAX693A/
MAX800L/MAX800M
Microprocessor Supervisory Circuits
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
20
0
0
BATTERY CURRENT
vs. INPUT SUPPLY VOLTAGE
16
MAX691A toc10
VCC (V)
IBATT (µA)
3
8
4
1 2 5
12
4
VBATT = 2.8V
IOUT = 0A
100
0.1
WATCHDOG AND RESET TIMEOUT PERIOD
vs. OSC IN TIMING CAPACITOR (COSC)
10
MAX691A toc11
COSC (pF)
WATCHDOG AND RESET TIMEOUT PERIOD (sec)
100
1
10 1000
VCC = 5V
VBATT = 2.8V LONG WATCHDOG
TIMEOUT PERIOD
SHORT WATCHDOG
TIMEOUT PERIOD
RESET ACTIVE
TIMEOUT PERIOD
0 300
CHIP-ENABLE PROPAGATION DELAY
vs. CE OUT LOAD CAPACITANCE
MAX691A toc12
CLOAD (pF)
PROPAGATION DELAY (ns)
150
8
0
50 100 250
16
20
4
12
200
VCC = 5V
CE IN = 0V TO 5V
DRIVER SOURCE
1000
1
1
VCC TO VOUT vs. OUTPUT CURRENT
(NORMAL OPERATING MODE)
100
MAX691A toc13
IOUT (mA)
VCC TO VOUT (mV)
100
10
10 1000
VCC = 4.5V
VBATT = 0V
SLOPE = 0.8Ω
1000
1
VBATT TO VOUT vs. OUTPUT CURRENT
(BATTERY-BACKUP MODE)
100
MAX691A toc14
IOUT (mA)
VBATT to VOUT (mV)
10
10
1 100
VCC = 0V
VBATT = 4.5V
SLOPE = 8Ω
LO
VCC TO LOW LINE
AND CE OUT DELAY
MAX691A toc15
LOW LINE
5V
VCC RESET
THRESHOLD
LO
HI
HI
HI
LO
CE OUT
RESET
12µs
800ns
80ms
Maxim Integrated
│
6
www.maximintegrated.com
MAX691A/MAX693A/
MAX800L/MAX800M
Microprocessor Supervisory Circuits
Typical Operating Characteristics (continued)
Detailed Description
RESET and RESET Outputs
The MAX691A/MAX693A/MAX800L/MAX800M’s
RESET
and RESET outputs ensure that the μP (with reset inputs
asserted either high or low) powers up in a known state,
and prevents code-execution errors during power-down
or brownout conditions.
The RESET output is active low, and typically sinks 3.2mA
at 0.1V saturation voltage in its active state. When deas-
serted, RESET sources 1.6mA at typically VOUT - 0.5V.
RESET output is open drain, active high, and typically
sinks 3.2mA with a saturation voltage of 0.1V. When no
backup battery is used, RESET output is guaranteed to be
valid down to VCC = 1V, and an external 10kΩ pulldown
resistor on RESET insures that it will be valid with VCC
down to GND (Figure 1). As VCC goes below 1V, the gate
drive to the RESET output switch reduces accordingly,
increasing the RDS(ON) and the saturation voltage. The
10kΩ pulldown resistor insures the parallel combination
of switch plus resistor is around 10kΩ and the output
saturation voltage is below 0.4V while sinking 40μA. When
using a 10kΩ external pulldown resistor, the high state for
RESET output with VCC = 4.75V will be 4.5V typical.
PIN
NAME
FUNCTION
1
VBATT
Battery-Backup
Input. Connect to external battery or
capacitor
and
charging
circuit. If backup battery is
not
used, connect to GND.
2
VOUT
Output Supply Voltage. When VCC is greater than VBATT and above the reset threshold, VOUT connects
to
VCC. When VCC falls below VBATT and is below the reset threshold, VOUT connects to VBATT. Connect
a
0.1µF
capacitor from VOUT to GND. Connect VOUT to VCC if no backup battery is
used.
3
V
CC Input Supply Voltage, 5V
Input.
4
GND Ground. 0V reference for all
signals.
5
BATT
ON
Battery-On Output.
When
VOUT switches to
VBATT, BATT
ON goes high.
When
VOUT switches to VCC,
BATT
ON goes low. Connect the base of a PNP through a
current-limiting
resistor to BATT ON for VOUT current
require-
ments greater than
250mA.
6
LOW LINE LOW LINE output goes low when VCC falls below the reset threshold. It returns high as soon as VCC rises above
the reset threshold.
7
OSC
IN
External
Oscillator Input. When OSC
SEL
is unconnected or driven high, a 10µA pull-up connects from VOUT to
OSC IN, the internal oscillator sets the reset and
watchdog
timeout periods, and OSC IN selects between
fast
and slow watchdog timeout periods. When OSC
SEL
is driven low, the reset and watchdog timeout periods
may be set either by a
capacitor
from OSC IN to ground or by an external clock at OSC IN (Figure
3).
8
OSC SEL Oscillator Select. When OSC SEL is
unconnected
or driven high, the internal oscillator sets the reset
delay
and
watchdog timeout period. When OSC
SEL
is low, the external oscillator input (OSC IN) is enabled
(Table 1). OSC SEL has a 10µA internal
pull-up.
9
PFI
Power-Fail Input. This is the noninverting input to the power-fail
comparator.
When PFI is less than 1.25V,
PFO goes low. When PFI is not used, connect PFI to GND or VOUT
.
10
PFO
Power-Fail
Output. This is the output of the power-fail comparator.
PFO
goes low when
PFI
is less than 1.25V.
This is an uncommitted comparator, and has no effect on any other internal
circuitry.
11
WDI
Watchdog Input. WDI is a three-level input. If WDI remains either high or low for longer than the
watchdog
time-
out period, WDO goes low and reset is asserted for the reset timeout period. WDO remains low until
the next
tran-
sition at WDI. Leaving WDI unconnected disables the watchdog function. WDI connects to an
internal voltage divider between VOUT and GND, which sets it to
mid-supply
when left
unconnected.
12 CE
OUT
Chip-Enable Output. CE OUT goes low only when CE IN is low and VCC is above the reset threshold. If CE
IN
is
low when reset is asserted, CE OUT will stay low for 15µs or until CE IN goes high, whichever occurs rst.
13 CE
IN
Chip-Enable Input. The input to
chip-enable
gating circuit. If CE IN is not used, connect CE IN to GND or
VOUT.
14
WDO
Watchdog Output. If WDI remains high or low longer than the watchdog timeout period, WDO goes low and reset
is asserted for the reset timeout period. WDO returns high on the next transition at WDI. WDO remains high
if
WDI
is
unconnected.
15 RESET RESET Output goes low whenever VCC falls below the reset threshold.
RESET
will remain low typically
for
200ms after VCC crosses the reset threshold on
power-up.
16 RESET
RESET
is an
active-high
output. It is open drain, and the inverse of RESET.
MAX691A/MAX693A/
MAX800L/MAX800M
Microprocessor Supervisory Circuits
www.maximintegrated.com Maxim Integrated
│
7
Pin Description
For battery voltages ≥ 2V connected to VBATT, RESET
and RESET remain valid for VCC from 0V to 5.5V.
RESET and RESET are asserted when VCC falls below
the reset threshold (4.65V for the MAX691A/MAX800L,
4.4V for the MAX693A/MAX800M) and remain asserted
for 200ms typ after VCC rises above the reset threshold
on power-up (Figure 5). The devices’ batteryswitchover
comparator does not affect reset assertion. However, both
reset outputs are asserted in batterybackup mode since
VCC must be below the reset threshold to enter this mode.
Watchdog Function
The watchdog monitors μP activity via the Watchdog Input
(WDI). If the μP becomes inactive, RESET and RESET
are asserted. To use the watchdog function, connect WDI
to a bus line or μP I/O line. If WDI remains high or low for
longer than the watchdog timeout period (1.6s nominal),
WDO, RESET, and RESET are asserted (see RESET
and RESET Outputs section, and the Watchdog Output
discussion on this page).
Watchdog Input
A change of state (high to low, low to high, or a minimum
100ns pulse) at the WDI during the watchdog period
resets the watchdog timer. The watchdog default timeout
is 1.6s.
To disable the watchdog function, leave WDI floating. An
internal resistor network (100kΩ equivalent impedance
at WDI) biases WDI to approximately 1.6V. Internal com-
parators detect this level and disable the watchdog timer.
When VCC is below the reset threshold, the watchdog
function is disabled and WDI is disconnected from its
internal resistor network, thus becoming high impedance.
Watchdog Output
The Watchdog Output (WDO) remains high if there is a
transition or pulse at WDI during the watchdog timeout
period. The watchdog function is disabled and WDO
is a logic high when VCC is below the reset threshold,
battery-backup mode is enabled, or WDI is an open
circuit. In watchdog mode, if no transition occurs at WDI
during the watchdog timeout period, RESET and RESET
are asserted for the reset timeout period (200ms typical).
WDO goes low and remains low until the next transition
at WDI (Figure 2). If WDI is held high or low indefinitely,
RESET and RESET will generate 200ms pulses every
1.6s. WDO has a 2 x TTL output characteristic.
Selecting an Alternative
Watchdog and Reset Timeout Period
The OSC SEL and OSC IN inputs control the watchdog
and reset timeout periods. Floating OSC SEL and OSC
IN or tying them both to VOUT selects the nominal 1.6s
watchdog timeout period and 200ms reset timeout period.
Connecting OSC IN to GND and floating or connecting
OSC SEL to VOUT selects the 100ms normal watchdog
timeout delay and 1.6s delay immediately after reset. The
reset timeout delay remains 200ms (Figure 2). Select alter-
native timeout periods by connecting OSC SEL to GND
and connecting a capacitor between OSC IN and GND, or
by externally driving OSC IN (Table 1 and Figure 3). OSC
IN is internally connected to a ±100nA (typ) current source
that charges and discharges the timing capacitor to create
the oscillator frequency, which sets the reset and watch-
Figure 1. Adding an external pulldown resistor ensures RESET
is valid with VCC down to GND.
Figure 2. Watchdog Timeout Period and Reset Active Time
MAX691A
MAX693A
TO µP RESET
1kΩ
15
RESET
WDI
WDO
RESET t1t1t3
t2
t1 = RESET TIMEOUT PERIOD
t2 = NORMAL WATCHDOG TIMEOUT PERIOD
t3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY AFTER RESET
MAX691A/MAX693A/
MAX800L/MAX800M
Microprocessor Supervisory Circuits
www.maximintegrated.com Maxim Integrated
│
8
dog timeout periods (see Connecting a Timing Capacitor
at OSC IN in the Applications Information section).
Chip-Enable Signal Gating
The MAX691A/MAX693A/MAX800L/MAX800M provide
internal gating of chip-enable (CE) signals to prevent
erroneous data from being written to CMOS RAM in the
event of a power failure. During normal operation, the
CE gate is enabled and passes all CE transitions. When
reset is asserted, this path becomes disabled, preventing
erroneous data from corrupting the CMOS RAM. All these
parts use a series transmission gate from CE IN to CE
OUT (Figure 4).
The 10ns max CE propagation delay from CE IN to CE
OUT enables the parts to be used with most μPs.
Chip-Enable Input
The Chip-Enable Input (CE IN) is high impedance (dis-
abled mode) while RESET and RESET are asserted.
During a power-down sequence where VCC falls below
the reset threshold or a watchdog fault, CE IN assumes
a high-impedance state when the voltage at CE IN goes
high or 15μs after reset is asserted, whichever occurs first
(Figure 5).
During a power-up sequence, CE IN remains high imped-
ance, regardless of CE IN activity, until reset is deas-
serted following the reset timeout period.
In the high-impedance mode, the leakage currents into
this terminal are ±1μA max over temperature. In the low-
impedance mode, the impedance of CE IN appears as a
75Ω resistor in series with the load at CE OUT.
The propagation delay through the CE transmission gate
depends on both the source impedance of the drive to
CE IN and the capacitive loading on the Chip-Enable
Output (CE OUT) (see Chip-Enable Propagation Delay
vs. CE OUT Load Capacitance in the Typical Operating
Characteristics). The CE propagation delay is production
tested from the 50% point of CE IN to the 50% point of
CE OUT using a 50Ω driver and 50pF of load capacitance
(Figure 6). For minimum propagation delay, minimize
the capacitive load at CE OUT, and use a low output-
impedance driver.
Chip-Enable Output
In the enabled mode, the impedance of CE OUT is
equivalent to 75Ω in series with the source driving CE IN.
In the disabled mode, the 75Ω transmission gate is off and
CE OUT is actively pulled to VOUT. This source turns off
when the transmission gate is enabled.
LOW LINE Output
LOW LINE is the buffered output of the reset threshold
comparator. LOW LINE typically sinks 3.2mA at 0.1V. For
normal operation (VCC above the LOW LINE threshold),
LOW LINE is pulled to VOUT.
Power-Fail Comparator
The power-fail comparator is an uncommitted compara-
tor that has no effect on the other functions of the IC.
Common uses include low-battery indication (Figure
7), and early power-fail warning (see Typical Operating
Circuit).
Figure 3. Oscillator Circuits
Table 1. Reset Pulse Width and Watchdog Timeout Selections
OSC SEL OSC IN WATCHDOG TIMEOUT PERIOD RESET TIMEOUT
PERIOD
NORMAL IMMEDIATELY AFTER RESET
Low External Clock Input 1024 clks 4096 clks 2048 clks
Low External Capacitor (600/47pF x C)ms (2.4/47pF x C)sec (1200/47pF x C)ms
Floating Low 100ms 1.6s 200ms
Floating Floating 1.6s 1.6s 200ms
OSC SEL
OSC IN
7
8
EXTERNAL
OSCILLATOR
OSC SEL
OSC IN
7
8
EXTERNAL
CLOCK
OSC SEL
OSC IN
7
8
INTERNAL OSCILLATOR
100ms WATCHDOG
OSC SEL
OSC IN
7
8
INTERNAL OSCILLATOR
1.6s WATCHDOG
MAX691A
MAX693A
MAX800L
MAX800M
N.C. N.C.
N.C.
50kHz
MAX691A/MAX693A/
MAX800L/MAX800M
Microprocessor Supervisory Circuits
www.maximintegrated.com Maxim Integrated
│
9
Figure 4. MAX691A/MAX693A/MAX800L/MAX800M Block Diagram
Figure 5. Reset and Chip-Enable Timing
MAX691A
MAX693A
MAX800L
MAX800M
CHIP-ENABLE
OUTPUT
CONTROL
VCC 3
1
13
7
11
9
VBATT
CE IN
OSC IN
WDI
PFI
RESET
GENERATOR
TIMEBASE FOR
RESET AND
WATCHDOG
WATCHDOG
TRANSITION
DETECTOR
WATCHDOG
TIMER
8
OSC SEL
1.25V
GND
4
4.65V* 6LOW LINE
5
2
12
15
16
14
PFO
WDO
RESET
RESET
CE OUT
10
VOUT
BATT ON
* 4.4V FOR THE MAX693A/MAX800M
VCC
CE IN
RESET
THRESHOLD
CE OUT
RESET
RESET
100µs
15µs
100µs
5.0V
4.0V
5.0V
0V
5V
0V
5V
0V
0V
5V
LOGIC LEVELS SHOWN ARE FROM 0V TO 5V.
MAX691A/MAX693A/
MAX800L/MAX800M
Microprocessor Supervisory Circuits
www.maximintegrated.com Maxim Integrated
│
10
Power-Fail Input
Power-Fail Input (PFI) is the input to the power-fail com-
parator. It has a guaranteed input leakage of ±25nA max
over temperature. The typical comparator delay is 25μs
from VIL to VOL (power failing), and 60μs from VIH to
VOH (power being restored). If PFI is not used, connect
it to ground.
Power-Fail Output
The Power-Fail Output (PFO) goes low when PFI goes
below 1.25V. It typically sinks 3.2mA with a saturation
voltage of 0.1V. With PFI above 1.25V, PFO is actively
pulled to VOUT.
Battery-Backup Mode
Two conditions are required to switch to battery-backup
mode: 1) VCC must be below the reset threshold, and 2)
VCC must be below VBATT. Table 2 lists the status of the
inputs and outputs in battery-backup mode.
Battery-On Output
The Battery-On (BATT ON) output indicates the status
of the internal VCC/battery-switchover comparator, which
controls the internal VCC and VBATT switches. For
VCC greater than VBATT (ignoring the small hysteresis
effect), BATT ON typically sinks 3.2mA at 0.1V saturation
voltage. In battery-backup mode, this terminal sources
approximately 10μA from VOUT. Use BATT ON to indi-
cate battery-switchover status or to supply base drive to
an external pass transistor for higher-current applications
(see Typical Operating Circuit).
Input Supply Voltage
The Input Supply Voltage (VCC) should be a regulated
5V. VCC connects to VOUT via a parallel diode and a
large PMOS switch. The switch carries the entire cur-rent
*VCC must be below the reset threshold to enter battery-back-
up mode.
Table 2. Input and Output Status in
Battery-Backup Mode
Figure 6. CE Propagation Delay Test Circuit Figure 7. Low-Battery Indicator
PIN NAME STATUS
1VBATT Supply current is 1µA max.
2VOUT VOUT is connected to VBATT through
an internal PMOS switch.
3VCC Battery switchover comparator
monitors VCC for active switchover.
4 GND GND 0V, 0V reference for all signals.
5BATT ON Logic high. The open-circuit output is
equal to VOUT.
6LOWLINE Logic low*
7 OSC IN OSC IN is ignored.
8OSC SEL OSC SEL is ignored.
9PFI The power-fail comparator remains
active in the battery-backup mode for
VCC ≥ VBATT - 1.2V typ.
10 PFO
The power-fail comparator remains
active in the battery-backup mode for
VCC ≥ VBATT - 1.2V typ. Below this
volt- age, PFO is forced low.
11 WDI Watchdog is ignored.
12 CE OUT Logic high. The open-circuit voltage is
equal to VOUT.
13 CE IN High impedance
14 WDO Logic high. The open-circuit voltage is
equal to VOUT.
15 RESET Logic low*
16 RESET High impedance*
MAX691A
MAX693A
MAX800L
MAX800M
CE IN
CLOAD
CE OUT
GND
+5V
50Ω
OUTPUT
IMPEDANCE
VCC
VBATT
2.8V MAX691A
MAX693A
MAX800L
MAX800M
PFI PFO
GND
+5V
VCC
VBATT
2.0V to 5.5V LOW BATT
MAX691A/MAX693A/
MAX800L/MAX800M
Microprocessor Supervisory Circuits
www.maximintegrated.com Maxim Integrated
│
11
load for currents less than 250mA. The parallel diode
carries any current in excess of 250mA. Both the switch
and the diode have impedances less than 1Ω each. The
maximum continuous current is 250mA, but power-on
transients may reach a maximum of 1A.
Battery-Backup Input
The Battery-Backup Input (VBATT) is similar to the VCC
input except the PMOS switch and parallel diode are
much smaller. Accordingly, the on-resistances of the diode
and the switch are each approximately 10Ω. Continuous
current should be limited to 25mA and peak currents (only
during power-up) limited to 250mA. The reverse leakage
of this input is less than 1μA over temperature and supply
voltage (Figure 8).
Output Supply Voltage
The Output Supply Voltage (VOUT) pin is internally con-
nected to the substrate of the IC and supplies current to
the external system and internal circuitry. All opencircuit
outputs will, for example, assume the VOUT voltage in their
high states rather than the VCC voltage. At the maximum
source current of 250mA, VOUT will typically be 200mV
below VCC. Decouple this terminal with a 0.1μF capacitor.
Applications Information
The MAX691A/MAX693A/MAX800L/MAX800M are not
short-circuit protected. Shorting VOUT to ground, other
than power-up transients such as charging a decoupling
capacitor, destroys the device.
All open-circuit outputs swing between VOUT and GND
rather than VCC and GND.
If long leads connect to the chip inputs, insure that these
leads are free from ringing and other conditions that
would forward bias the chip’s protection diodes.
There are three distinct modes of operation:
1) Normal operating mode with all circuitry powered up.
Typical supply current from VCC is 35μA while only
leakage currents flow from the battery.
2) Battery-backup mode where VCC is typically within
0.7V below VBATT. All circuitry is powered up and the
supply current from the battery is typically less than
60μA.
3) Battery-backup mode where VCC is less than VBATT
by at least 0.7V. VBATT supply current is 1μA max.
Using SuperCap or MaxCap with the
MAX691A/MAX693A/MAX800L/MAX800M
VBATT has the same operating voltage range as VCC,
and the battery switchover threshold voltages are typically
±30mV centered at VBATT, allowing use of a SuperCap
and a simple charging circuit as a backup source
(Figure 9).
If VCC is above the reset threshold and VBATT is 0.5V
above VCC, current flows to VOUT and VCC from VBATT
until the voltage at VBATT is less than 0.5V above VCC.
For example, with a SuperCap connected to VBATT and
through a diode to VCC, if VCC quickly changes from 5.4V
to 4.9V, the capacitor discharges through VOUT and VCC
until VBATT reaches 5.1V typ. Leakage current through
the SuperCap charging diode and the internal power
diode eventually discharges the SuperCap to VCC. Also,
if VCC and VBATT start from 0.1V above the reset thresh-
Figure 8. VCC and VBATT to VOUT Switch Figure 9. SuperCap or MaxCap on VBATT
MAX691A
MAX693A
MAX800L
MAX800M
VBATT
VCC
0.1µF
VOUT MAX691A
MAX693A
MAX800L
MAX800M
1
0.47F*
1N4148
+5V
2
3
VCC
GND
VBATT
4
VOUT
* MaxCap
MAX691A/MAX693A/
MAX800L/MAX800M
Microprocessor Supervisory Circuits
www.maximintegrated.com Maxim Integrated
│
12
old and power is lost at VCC, the SuperCap on VBATT
discharges through VCC until VBATT reaches the reset
threshold; then the battery-backup mode is initiated and
the current through VCC goes to zero.
Using Separate Power Supplies
for VBATT and VCC
If using separate power supplies for VCC and VBATT,
VBATT must be less than 0.3V above VCC when VCC is
above the reset threshold. As described in the previous
section, if VBATT exceeds this limit and power is lost at
VCC, current flows continuously from VBATT to VCC via
the VBATT-to-VOUT diode and the VOUT-to-VCC switch
until the circuit is broken (Figure 8).
Alternate Chip-Enable Gating
Using memory devices with both CE and CE inputs allows
the CE loop to be bypassed. To do this, connect CE IN to
ground, pull up CE OUT to VOUT, and connect CE OUT to
the CE input of each memory device (Figure 10). The CE
input of each part then connects directly to the chip-select
logic, which does not have to be gated.
Figure10. Alternate CE Gating Figure 11. Adding Hysteresis to the Power-Fail Comparator
Figure 12. Monitoring a Negative Voltage
MAX691A
MAX693A
MAX800L
MAX800M
VOUT
GND
CE IN
CE
CE
CE OUT
CE
CE
CE
CE
CE
CE
*MAXIMUM Rp VALUE DEPENDS ON
THE NUMBER OF RAMS.
MINIMUM Rp VALUE IS 1kΩ.
ACTIVE-HIGH
CE LINES
FROM LOGIC
RAM 1
RAM 2
RAM 3
RAM 4
Rp*
MAX691A
MAX693A
MAX800L
MAX800M
VCC
GND
PFI
*OPTIONAL
R2
R3
R1
VIN +5V
C1*
TO µP
PFO
VTRIP = 1.25 R1 + R2
R2
VH = 1.25/ R2 I I R3 VL - 1.25 + 5 - 1.25 = 1.25
R1 + R2 I I R3 R1 R3 R2
PFO
5V
0V
0V VH
VTRIP
VIN
VL
MAX691A
MAX693A
MAX800L
MAX800M
VCC
GND
PFI
R2
R1
+5V
PFO
PFO
5V
0V
NOTE: VTRIP IS NEGATIVE.
0V
VTRIP
V-
5 - 1.25 = 1.25 - VTRIP
R1 R2
V-
MAX691A/MAX693A/
MAX800L/MAX800M
Microprocessor Supervisory Circuits
www.maximintegrated.com Maxim Integrated
│
13
Adding Hysteresis to the
Power-Fail Comparator
Hysteresis adds a noise margin to the power-fail compar-
ator and prevents repeated triggering of PFO when VIN is
near the power-fail comparator trip point. Figure 11 shows
how to add hysteresis to the power-fail comparator. Select
the ratio of R1 and R2 such that PFI sees 1.25V when
VIN falls to the desired trip point (VTRIP). Resistor R3
adds hysteresis. It will typically be an order of magnitude
greater than R1 or R2. The current through R1 and R2
should be at least 1μA to ensure that the 25nA (max) PFI
input current does not shift the trip point. R3 should be
larger than 10kΩ to prevent it from loading down the PFO
pin. Capacitor C1 adds noise rejection.
Monitoring a Negative Voltage
The power-fail comparator can be used to monitor a
negative supply voltage using Figure 12’s circuit. When
the negative supply is valid, PFO is low. When the nega-
tive supply voltage drops, PFO goes high. This circuit’s
accuracy is affected by the PFI threshold tolerance, the
VCC voltage, and resistors R1 and R2.
Backup-Battery Replacement
The backup battery may be disconnected while VCC is
above the reset threshold. No precautions are necessary
to avoid spurious reset pulses.
Negative-Going VCC Transients
While issuing resets to the μP during power-up, power-
down, and brownout conditions, these supervisors are
relatively immune to short-duration, negative-going VCC
transients (glitches). It is usually undesirable to reset the
μP when VCC experiences only small glitches.
Figure 13 shows maximum transient duration vs. reset-
comparator overdrive, for which reset pulses are not
generated. The graph was produced using negativegoing
VCC pulses, starting at 5V and ending below the reset
threshold by the magnitude indicated (reset comparator
overdrive). The graph shows the maximum pulse width a
negative-going VCC transient may typically have without
causing a reset pulse to be issued. As the amplitude of
the transient increases (i.e., goes farther below the reset
threshold), the maximum allowable pulse width decreas-
es. Typically, a VCC transient that goes 100mV below the
reset threshold and lasts for 40μs or less will not cause a
reset pulse to be issued.
A 100nF bypass capacitor mounted close to the VCC pin
provides additional transient immunity.
Connecting a Timing Capacitor at OSC IN
When OSC SEL is connected to ground, OSC IN discon-
nects from its internal 10μA (typ) pullup and is internally
connected to a ±100nA current source. When a capacitor
is connected from OSC IN to ground (to select alternative
reset and watchdog timeout periods), the current source
charges and discharges the timing capacitor to create the
oscillator that controls the reset and watchdog timeout
period. To prevent timing errors or oscillator startup prob-
Figure 13. Maximum Transient Duration without Causing a
Reset Pulse vs. Reset Comparator Overdriv
100
0
10 1000 10000
40
20
80
60
MAX791-16
RESET COMPARATOR OVERDRIVE,
(Reset Threshold Voltage - VCC) (mV)
MAXIMUM TRANSIENT DURATION (µs)
100
VCC = 5V
TA = +25°C
0.1µF CAPACITOR
FROM VOUT TO GND
MAX691A/MAX693A/
MAX800L/MAX800M
Microprocessor Supervisory Circuits
www.maximintegrated.com Maxim Integrated
│
14
lems, minimize external current leakage sources at this
pin, and locate the capacitor as close to OSC IN as pos-
sible. The sum of PC-board leakage plus OSC capacitor
leakage must be small compared to ±100nA.
Maximum VCC Fall Time
The VCC fall time is limited by the propagation delay of
the battery switchover comparator and should not exceed
0.03V/μs. A standard rule of thumb for filter capacitance
on most regulators is on the order of 100μF per amp of
current. When the power supply is shut off or the main
battery is disconnected, the associated initial VCC fall rate
is just the inverse or 1A/100μF = 0.01V/μs. The VCC fall
rate decreases with time as VCC falls exponentially, which
more than satisfies the maximum fall-time requirement.
Watchdog Software Considerations
A way to help the watchdog timer keep a closer watch
on software execution involves setting and resetting the
watchdog input at different points in the program, rather
than “pulsing” the watchdog input high-low-high or low-
high-low. This technique avoids a “stuck” loop where the
watchdog timer continues to be reset within the loop,
keeping the watchdog from timing out. Figure 14 shows
an example flow diagram where the I/O driving the watch-
dog input is set high at the beginning of the program, set
low at the beginning of every subroutine or loop, then set
high again when the program returns to the beginning. If
the program should “hang” in any subroutine, the I/O is
continually set low and the watchdog timer is allowed to
time out, causing a reset or interrupt to be issued.
Figure 14. Watchdog Flow Diagram
START
SET
WDI
LOW
RETURN
END
SUBROUTINE
OR PROGRAM LOOP
SET WDI
HIGH
MAX691A/MAX693A/
MAX800L/MAX800M
Microprocessor Supervisory Circuits
www.maximintegrated.com Maxim Integrated
│
15
*Dice are specified at TA = +25°C, DC parameters only.
**Contact factory for availability and processing to MIL-STD-883B.
Devices in PDIP, SO and TSSOP packages are available in
both leaded and lead-free packaging. Specify lead free by add-
ing the + symbol at the end of the part number when ordering.
Lead free not available for CERDIP package.
PART TEMP RANGE PIN-
PACKAGE
MAX691AEJE -40°C to +85°C 16 CERDIP
MAX691AMJE -55°C to +125°C 16 CERDIP**
MAX691AMSE/PR -55°C to +125°C 16 Wide SO**
MAX691AMSE/PR-T -55°C to +125°C 16 Wide SO**
MAX693ACUE -0°C to +70°C 16 TSSOP
MAX693ACSE -0°C to +70°C 16 Narrow SO
MAX693ACWE -0°C to +70°C 16 Wide SO
MAX693ACPE -0°C to +70°C 16 Plastic DIP
MAX693AC/D -0°C to +70°C Dice*
MAX693AEUE -40°C to +85°C 16 TSSOP
MAX693AESE -40°C to +85°C 16 Narrow SO
MAX693AEWE -40°C to +85°C 16 Wide SO
MAX693AEPE -40°C to +85°C 16 Plastic DIP
MAX693AEJE -40°C to +85°C 16 CERDIP
MAX693AMJE -55°C to +125°C 16 CERDIP
MAX800LCUE -0°C to +70°C 16 TSSOP
MAX800LCSE -0°C to +70°C 16 Narrow SO
MAX800LCPE -0°C to +70°C 16 Plastic DIP
MAX800LEUE -40°C to +85°C 16 TSSOP
MAX800LESE -40°C to +85°C 16 Narrow SO
MAX800LEPE -40°C to +85°C 16 Plastic DIP
MAX800MCUE -0°C to +70°C 16 TSSOP
MAX800MCSE -0°C to +70°C 16 Narrow SO
MAX800MCPE -0°C to +70°C 16 Plastic DIP
MAX800MEUE -40°C to +85°C 16 TSSOP
MAX800MESE -40°C to +85°C 16 Narrow SO
MAX800MEPE -40°C to +85°C 16 Plastic DIP
PACKAGE
TYPE
PKG
CODE
OUTLINE
NO.
LAND
PATTERN NO.
16 TSSOP
U16-1
21-0066 90-0117
16 CERDIP
J16-3
21-0045 —
16 Narrow SO
S16-3
21-0041 90-0097
16 Plastic
DIP
P16-1
21-0043 —
16 Wide SO
W16-1
21-0042 90-0107
WDI
CE IN
CE OUT
VCC
GND
WDO
BATT ON
LOW LINE
VOUT VBATT RESET RESET
PFI PFO
OSC SEL
SUBSTRATE CONNECTED TO VOUT
OSC IN
0.11"
(2.794mm)
0.07"
(1.778mm)
MAX691A/MAX693A/
MAX800L/MAX800M
Microprocessor Supervisory Circuits
www.maximintegrated.com Maxim Integrated
│
16
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
Chip Topography
Ordering Information (continued)
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
009/92 Initial release —
112/92 Update Electrical Characteristics table. 2, 3, 4
2 5/93 Update Electrical Characteristics table, Tables 1 and 2. 2, 3, 4, 9, 11
312/93 Update Electrical Characteristics table. 2, 3, 4
4 3/94 Update Electrical Characteristics table. 2, 3, 4
5 8/94 Correction to Figure 4. 10
61/95 Update to new revision and correct errors. —
7 12/96 Update Electrical Characteristics table. 2, 3, 4
812/99 Updated Ordering Information, Pin Conguration, Absolute Maximum
Ratings, and Package Information.1, 2, 16
94/02 Corrected Ordering Information.1
10 11/05 Added lead-free information. 1, 16
11 8/08 Updated Ordering Information. 1, 16
12 9/14 No /V OPNs; removed automotive reference from Applications section;
updated Package Information table 1, 16
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2014 Maxim Integrated Products, Inc.
│
17
MAX691A/MAX693A/
MAX800L/MAX800M
Microprocessor Supervisory Circuits
Revision History
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Maxim Integrated:
MAX691ACPE+ MAX691ACSE+ MAX691ACWE+ MAX691AEPE+ MAX691AESE+ MAX691AEWE+
MAX693ACPE+ MAX693ACSE+ MAX693AEPE+ MAX800LCPE+ MAX800LCSE+ MAX800LCSE+T
MAX800LCUE+ MAX800LCUE+T MAX800LEUE+ MAX800LEUE+T MAX800MCPE+ MAX800MCSE+
MAX800MCSE+T MAX800MCUE+ MAX800MCUE+T MAX800MEUE+ MAX800MEUE+T MAX691ACSE+T
MAX691ACUE+ MAX691ACUE+T MAX691ACWE+T MAX691AESE+T MAX691AEUE+ MAX691AEUE+T
MAX691AEWE+T MAX693ACSE+T MAX693ACUE+ MAX693ACUE+T MAX693ACWE+ MAX693ACWE+T
MAX693AESE+ MAX693AESE+T MAX693AEUE+ MAX693AEUE+T MAX693AEWE+ MAX693AEWE+T
MAX693AMJE MAX691AMSE/PR-T MAX691AMSE/PR MAX691AEJE MAX800LESE+ MAX691AMJE/883B
MAX693ACUE MAX800LESE MAX691ACUE