HM534253B Series
262,144-word × 4-bit Multiport CMOS Video RAM
ADE-203-204C (Z)
Rev. 3.0
Apr. 24, 1995
Description
The HM534253B is a 1-Mbit multiport video RAM equipped with a 256-kword × 4-bit dynamic RAM and a
512-word × 4-bit SAM (serial access memory). Its RAM and SAM operate independently and
asynchronously. It can transfer data between RAM and SAM. In addition, it has two modes to realize fast
writing in RAM. Block write and flash write modes clear the data of 4-word × 4-bit and the data of one row
(512-word × 4-bit) respectively in one cycle of RAM. And the HM534253B makes split transfer cycle
possible by dividing SAM into two split buffers equipped with 256-word × 4-bit each. This cycle can transfer
data to SAM which is not active, and enables a continuous serial access.
Features
• Multiport organization
Asynchronous and simultaneous operation of RAM and SAM capability
RAM: 256-kword × 4-bit
SAM: 512-word × 4-bit
• Access time
RAM: 60 ns/70 ns/80 ns/100 ns max
SAM: 20 ns/22 ns/25 ns/25 ns max
• Cycle time
RAM: 125 ns/135 ns/150 ns/180 ns min
SAM: 25 ns/25 ns/30 ns/30 ns min
• Low power
Active RAM: 413 mW max
SAM: 275 mW max
Standby 38.5 mW max
• High-speed page mode capability
• Mask write mode capability
• Bidirectional data transfer cycle between RAM and SAM capability
• Split transfer cycle capability
• Block write mode capability
• Flash write mode capability
HM534253B Series
2
• 3 variations of refresh (8 ms/512 cycles)
RAS-only refresh
CAS-before-RAS refresh
Hidden refresh
• TTL compatible
Ordering Information
Type No. Access Time Package
HM534253BJ-6
HM534253BJ-7
HM534253BJ-8
HM534253BJ-10
60 ns
70 ns
80 ns
100 ns
400-mil 28-pin plastic SOJ (CP-28D)
HM534253BZ-6
HM534253BZ-7
HM534253BZ-8
HM534253BZ-10
60 ns
70 ns
80 ns
100 ns
400-mil 28-pin plastic ZIP (ZP-28)
Pin Arrangement
SC
SI/O0
SI/O1
DT/OE
I/O0
I/O1
WE
NC
RAS
A8
A6
A5
A4
V
V
SI/O3
SI/O2
SE
I/O3
I/O2
DSF
CAS
QSF
A0
A1
A2
A3
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CC
SS
(Top View)
1
3
5
7
9
11
13
15
17
19
21
23
25
27
2
4
6
8
10
12
14
16
18
20
22
24
26
28
DSF
I/O3
SI/O2
V
SI/O0
DT/OE
I/O1
NC
A8
A5
V
A3
A1
QSF
I/O2
SE
SI/O3
SC
SI/O1
I/O0
WE
RAS
A6
A4
A7
A2
A0
CAS
CC
SS
(Bottom View)
HM534253BJ Series HM534253BZ Series
HM534253B Series
3
Pin Description
Pin Name Function
A0 – A8 Address inputs
I/O0 – I/O3 RAM port data inputs/outputs
SI/O0 – SI/O3 SAM port data inputs/outputs
RAS Row address strobe
CAS Column address strobe
WE Write enable
DT/OE Data transfer/output enable
SC Serial clock
SE SAM port enable
DSF Special function input flag
QSF Special function output flag
VCC Power supply
VSS Ground
NC No connection
HM534253B Series
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Block Diagram
A0 – A8
SI/O0 – SI/O3
I/O0 – I/O3
RAS
CAS
DT/OE
WE
DSF
SC
SE
Timing Generator
Output
Buffer
Input
Buffer
Mask
Register
Input Data
Control Serial Output
Buffer Serial Input
Buffer
Column Decoder
Sense Amplifier & I/O Bus
SAM I/O Bus
SAM Column Decoder
Data
Register
Serial Address
Counter
Refresh
Counter
Row Address
Buffer
Column Address
Buffer
Row Decoder
Memory Array
Data
Register
Transfer
Gate
Transfer
Gate
Flash Write
Control
Block Write
Control
Color
Register
Address Mask
Register
QSF
HM534253B Series
5
Pin Functions
RAS (input pin): RAS is a basic RAM signal. It is active in low level and standby in high level. Row
address and signals as shown in table 1 are input at the falling edge of RAS. The input level of these signals
determine the operation cycle of the HM534253B.
Table 1 Operation Cycles of the HM534253B
Input Level At The Falling Edge Of RAS
CAS DT/OE WE SE DSF DSF At The Falling Edge Of CAS Operation Mode
L X X X X — CBR refresh
H L L L L X Write transfer
H L L H L X Pseudo transfer
H L L X H X Split write transfer
H L H X L X Read transfer
H L H X H X Split read transfer
HHLXLL Read/mask write
HHLXLH Mask block write
H H L X H X Flash write
H H H X L L Read/write
H H H X L H Block write
H H H X H X Color register read/write
Note: X: H or L.
CAS (input pin): Column address and DSF signals are fetched into chip at the falling edge of CAS , which
determines the operation mode of the HM534253B. CAS controls output impedance of I/O in RAM.
A0 – A8 (input pins): Row address is determined by A0 – A8 level at the falling edge of RAS. Column
address is determined by A0 – A8 level at the falling edge of CAS. In transfer cycles, row address is the
address on the word line which transfers data with SAM data register, and column address is the SAM start
address after transfer.
WE (input pin): WE pin has two functions at the falling edge of RAS and after. When WE is low at the
falling edge of RAS, the HM534253B turns to mask write mode. According to the I/O level at the time, write
on each I/O can be masked. (WE level at the falling edge of RAS is don’t care in read cycle.) When WE is
high at the falling edge of RAS, a normal write cycle is executed. After that, WE switches read/write cycles
as in a standard DRAM. In a transfer cycle, the direction of transfer is determined by WE level at the falling
edge of RAS. When WE is low, data is transferred from SAM to RAM (data is written into RAM), and when
WE is high, data is transferred from RAM to SAM (data is read from RAM).
HM534253B Series
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I/O0 – I/O3 (input/output pins): I/O pins function as mask data at the falling edge of RAS (in mask write
mode). Data is written only to high I/O pins. Data on low I/O pins are masked and internal data are retained.
After that, they function as input/output pins as those of a standard DRAM. In block write cycle, they
function as address mask data at the falling edges of CAS.
DT/OE (input pin): DT/OE pin functions as DT (data transfer) pin at the falling edge of RAS and as OE
(output enable) pin after that. When DT is low at the falling edge of RAS , this cycle becomes a transfer cycle.
When DT is high at the falling edge of RAS , RAM and SAM operate independently.
SC (input pin): SC is a basic SAM clock. In a serial read cycle, data outputs from an SI/O pin
synchronously with the rising edge of SC. In a serial write cycle, data on an SI/O pin at the rising edge of SC
is fetched into the SAM data register.
SE(input pin): SE pin activates SAM. When SE is high, SI/O is in the high impedance state in serial read
cycle and data on SI/O is not fetched into the SAM data register in serial write cycle. SE can be used as a
mask for serial write because internal pointer is incremented at the rising edge of SC.
SI/O0 – SI/O3 (input/output pins): SI/Os are input/output pins in SAM. Direction of input/output is
determined by the previous transfer cycle. When it was a read transfer cycle, SI/O outputs data. When it was
a pseudo transfer cycle or write transfer cycle, SI/O inputs data.
DSF (input pin): DSF is a special function data input flag pin. It is set to high at the falling edge of RAS
when new functions such as color register read/write, split transfer, and flash write, are used. DSF is set to
high at the falling edge of CAS when block write is executed.
QSF (output pin): QSF outputs data of address A8 in SAM. QSF is switched from low to high by accessing
address 255 in SAM and from high to low by accessing 511 address in SAM.
HM534253B Series
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Operation of HM534253B
RAM Port Operation
RAM Read Cycle (DT/OE high, CAS high and DSF low at the falling edge of RAS, DSF low at the falling
edge of CAS)
Row address is entered at the RAS falling edge and column address at the CAS falling edge to the device as in
standard DRAM. Then, when WE is high and DT/OE is low while CAS is low, the selected address data
outputs through I/O pin. At the falling edge of RAS, DT/OE and CAS become high to distinguish RAM read
cycle from transfer cycle and CBR refresh cycle. Address access time (tAA) and RAS to column address delay
time (tRAD) specifications are added to enable high-speed page mode.
RAM Write Cycle (Early Write, Delayed Write, Read-Modify-Write) (DT/OE high, CAS high and DSF
low at the falling edge of RAS, DSF low at the falling edge of CAS)
• Normal Mode Write Cycle (WE high at the falling edge of RAS )
When CAS and WE are set low after driving RAS low, a write cycle is executed and I/O data is written in
the selected addresses. When all 4 I/Os are written, WE should be high at the falling edge of RAS to
distinguish normal mode from mask write mode.
If WE is set low before the CAS falling edge, this cycle becomes an early write cycle and all I/O become
in high impedance. Data is entered at the CAS falling edge.
If WE is set low after the CAS falling edge, this cycle becomes a delayed write cycle. Data is input at the
WE falling. I/O does not become high impedance in this cycle, so data should be entered with OE in high.
If WE is set low after tCWD (min) and tAWD (min) after the CAS falling edge, this cycle becomes a read-
modify-write cycle and enables read/write at the same address in one cycle. In this cycle also, to avoid I/O
contention, data should be input after reading data and driving OE high.
• Mask Write Mode (WE low at the falling edge of RAS)
If WE is set low at the falling edge of RAS, the cycle becomes a mask write mode which writes only to
selected I/O. Whether or not an I/O is written depends on I/O level (mask data) at the falling edge of
RAS. Then the data is written in high I/O pins and masked in low ones and internal data is retained. This
mask data is effective during the RAS cycle. So, in high-speed page mode, the mask data is retained
during the page access.
HM534253B Series
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High-Speed Page Mode Cycle (DT/OE high, CAS high and DSF low at the falling edge of RAS)
High-speed page mode cycle reads/writes the data of the same row address at high speed by toggling CAS
while RAS is low. Its cycle time is one third of the random read/write cycle. In this cycle, read, write, and
block write cycles can be mixed. Note that address access time (tAA), RAS to column address delay time
(tRAD), and access time from CAS precharge (tACP) are added. In one RAS cycle, 512-word memory cells of the
same row address can be accessed. It is necessary to specify access frequency within tRASP max (100 µs).
Color Register Set/Read Cycle (CAS high, DT/OE high, WE high and DSF high at the falling edge of RAS)
In color register set cycle, color data is set to the internal color register used in flash write cycle or block write
cycle. 4 bits of internal color register are provided at each I/O. This register is composed of static circuits, so
once it is set, it retains the data until reset. Color register set cycle is just as same as the usual write cycle
except that DSF is set high at the falling edge of RAS, and read, early write and delayed write cycle can be
executed. In this cycle, the HM534253B refreshes the row address fetched at the falling edge of RAS.
Flash Write Cycle (CAS high, DT/OE high, WE low, and DSF high at the falling edge of RAS)
In a flash write cycle, a row of data (512-word × 4-bit) is cleared to 0 or 1 at each I/O according to the data of
color register mentioned before. It is also necessary to mask I/O in this cycle. When CAS and DT/OE is set
high, WE is low, and DSF is high at the falling edge of RAS, this cycle starts. Then, the row address to clear
is given to row address and mask data is given to I/O. Mask data is as same as that of a RAM write cycle.
High I/O is cleared, low I/O is not cleared and the internal data is retained. Cycle time is the same as those of
RAM read/write cycles, so all bits can be cleared in 1/512 of the usual cycle time. (See figure 1.)
HM534253B Series
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RAS
CAS
Address
WE
DT/OE
DSF
I/O
Color Register Set Cycle Flash Write Cycle Flash Write Cycle
Row Xi Xj
*1 *1Color Data
Set color register Execute flash write into each
I/O on row address Xi using
color resister.
Execute flash write into
each I/O on row address
Xj using color resister.
Note: 1. I/O Mask Data
Low: Mask
High: Non Mask
Figure 1 Use of Flash Write
Block Write Cycle (CAS high, DT/OE high and DSF low at the falling edge of RAS, DSF high at the falling
edge of CAS)
In a block write cycle, 4 columns of data (4-word × 4-bit) is cleared to 0 or 1 at each I/O according to the data
of color register. Column addresses A0 and A1 are disregarded. The data on I/Os and addresses can be
masked. I/O level at the falling edge of CAS determines the address to be cleared. (See figure 2.) In a page
mode cycle, mixed cycle of normal Read/Write and block write can be allowed by controlling DSF.
• Normal Mode Block Write Cycle (WE high at the falling edge of RAS)
The data on 4 I/Os are all cleared when WE is high at the falling edge of RAS.
• Mask Block Write Mode (WE low at the falling edge of RAS)
When WE is low at the falling edge of RAS, the HM534253B starts mask block write mode to clear the
data on an optional I/O. The mask data is the same as that of a RAM write cycle. High I/O is cleared, low
I/O is not cleared and the internal data is retained. The mask data is available in the RAS cycle. In page
mode block write cycle, the mask data is retained during the page access.
HM534253B Series
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Color Register Set Cycle Block Write Cycle Block Write Cycle
Row Row
Column A2–A8
Row
Column A2–A8
*1 *1
*1*1
Color Data
Address Mask Address Mask
RAS
CAS
Address
WE
DT/OE
DSF
I/O
*1
I/O Mask Data
Low: Mask
High: Non Mask
Address Mask Data
Low: Mask
High: Non Mask
I/O0
I/O1
I/O2
I/O3
Column0 (A0 = 0, A1 = 0) Mask Data
Column1 (A0 = 1, A1 = 0) Mask Data
Column2 (A0 = 0, A1 = 1) Mask Data
Column3 (A0 = 1, A1 = 1) Mask Data
WE
Low
High
I/O
I/O Mask Data
Don't care Non mask
Mask
Mode
Figure 2 Use of Block Write
Transfer Operation
The HM534253B provides the read transfer cycle, split read transfer cycle,pseudo transfer cycle, write
transfer cycle, and split write transfer cycle as data transfer cycles. These transfer cycles are set by driving
CAS high and DT/OE low at the falling edge of RAS. They have following functions:
(1) Transfer data between row address and SAM data register (except for pseudo transfer cycle)
Read transfer cycle and split read transfer cycle: RAM to SAM
Write transfer cycle and split write transfer cycle: SAM to RAM
(2) Determine SI/O state (except for split read transfer cycle and split write transfer cycle)
Read transfer cycle: SI/O output
Pseudo transfer cycle and write transfer cycle: SI/O input
(3) Determine first SAM address to access after transferring at column address (SAM start address).
HM534253B Series
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SAM start address must be determined by read transfer cycle or pseudo transfer cycle (split transfer cycle
isn’t available) before SAM access, after power on, and determined for each transfer cycle.
Read Transfer Cycle (CAS high, DT/OE low, WE high and DSF low at the falling edge of RAS)
This cycle becomes read transfer cycle by driving DT/OE low, WE high and DSF low at the falling edge of
RAS. The row address data (512 × 4 bits) determined by this cycle is transferred to SAM data register
synchronously at the rising edge of DT/OE. After the rising edge of DT/OE, the new address data outputs
from SAM start address determined by column address. In read transfer cycle, DT/OE must be risen to
transfer data from RAM to SAM.
This cycle can access SAM even during transfer (real time read transfer). In this case, the timing tSDD (min)
specified between the last SAM access before transfer and DT/OE rising edge and tSDH (min) specified
between the first SAM access and DT/OE rising edge must be satisfied. (See figure 3.)
When read transfer cycle is executed, SI/O becomes output state by first SAM access. Input must be set high
impedance before tSZS (min) of the first SAM access to avoid data contention.
RAS
CAS
Address
DT/OE
SC
SI/O
SAM Data before Transfer SAM Data after Transfer
tSDD tSDH
L
Xi Yj
Yj Yj + 1
DSF
Figure 3 Real Time Read Transfer
Pseudo Transfer Cycle (CAS high, DT/OE low, WE low, SE high and DSF low at the falling edge of RAS)
Pseudo transfer cycle switches SI/O to input state and set SAM start address without data transfer to RAM.
This cycle starts when CAS is high, DT/OE low, WE low, SE high and DSF low at the falling edge of RAS.
Data should be input to SI/O later than tSID (min) after RAS becomes low to avoid data contention. SAM
access becomes enabled after t SRD (min) after RAS becomes high. In this cycle, SAM access is inhibited
during RAS low, therefore, SC must not be risen.
HM534253B Series
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Write Transfer Cycle (CAS high, DT/OE low, WE low, SE low, and DSF low at the falling edge of RAS)
Write transfer cycle can transfer a row of data input by serial write cycle to RAM. The row address of data
transferred into RAM is determined by the address at the falling edge of RAS. The column address is
specified as the first address for serial write after terminating this cycle. Also in this cycle, SAM access
becomes enabled after tSRD (min) after RAS becomes high. SAM access is inhibited during RAS low. In this
period, SC must not be risen. Data transferred to SAM by read transfer cycle or split read transfer cycle can
be written to other addresses of RAM by write transfer cycle. However, the address to write data must be the
same MSB of row address (AX8) as that of the read transfer cycle. Figure 4 shows the example of row bit
data transfer. In case AX8 is 0, data cannot be transferred RAM address within the range of 100000000 to
111111111. Same as the case of AX8 = 1.
A8 A0
000000000
100000000
011111111
111111111
(Row address)
........
A8 A0
000000000
100000000
011111111
111111111
........ Possible
Impossible
(Read transfer cycle) (Write transfer cycle)
SAM
RAM
RAM
SAM
(Row address) SAM
RAM
RAM
SAM
........
Figure 4 Example of Row Bit Data Transfer
Split Read Transfer Cycle (CAS high, DT/OE low, WE high and DSF high at the falling edge of RAS)
To execute a continuous serial read by real time read transfer, the HM534253B must satisfy SC and DT/OE
timings and requires an external circuit to detect SAM last address. Split read transfer cycle makes it possible
to execute a continuous serial read without the above timing limitation. Figure 5 shows the block diagram for
a split transfer. SAMdata register (DR) consists of 2 split buffers, whose organizations are 256-word × 4-bit
each. Let us suppose that data is read from upper data register DR1 (The row address AX8 is 0 and SAM
address A8 is 1.). When split read transfer is executed setting row address AX8 0 and SAM start addresses
A0 to A7, 256-word × 4-bit data are transferred from RAM to the lower data register DR0 (SAM address A8
is 0) automatically. After data are read from data register DR1, data start to be read from SAM start addresses
of data register DR0. If the next split read transfer isn’t executed while data are read from data register DR0,
data start to be read from SAM start address 0 of DR1 after data are read from data register DR0. If split read
transfer is executed setting row address AX8 1 and SAM start addresses A0 to A7 while data are read from
data register DR1, 256-word × 4-bit data are transferred to data register DR2. After data are read from data
register DR1, data start to be read from SAM start addresses of data register DR2. If the next split read
transfer isn’t executed while data is read from data register DR2, data start to be read from SAM start address
0 of data register DR3 after data are read from data register DR2. In this time, SAM data is the one
transferred to data register DR3 finally while row address AX8 is 1. In split read data transfer, the SAM start
address A8 is automatically set in the data register which isn’t used.
HM534253B Series
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The data on SAM address A8, which will be accessed next, outputs to QSF. QSF is switched from low to
high by accessing SAM last address 255 and from high to low by accessing address 511.
Split read transfer cycle is set when CAS is high, DT/OE is low, WE is high and DSF is high at the falling
edge of RAS. The cycle can be executed asyncronously with SC. However, tSTS (min) timing specified
between SC rising and RAS falling must be satisfied. SAM last address must be accessed, satisfying tRST
(min), tCST (min), and tAST (min) timings specified between RAS or CAS falling and column address. (See
figure 6.)
In split read transfer, SI/O isn't switched to output state. Therefore, read transfer must be executed to switch
SI/O to output state when the previous transfer cycle is pseudo transfer or write transfer cycle.
Memory
Array
AX8 = 0
Memory
Array
DR1
SAM I/O Bus
SAM Column Decoder
DR0
SAM I/O Bus
DR3DR2
SAM I/O Buffer
SI/O
AX8 = 1
Figure 5 Block Diagram for Split Transfer
HM534253B Series
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RAS
CAS
Address
DT/OE
DSF
SC
t (min)
STS t (min)
RST
t (min)
CST
t (min)
AST
511
(255) n
(n + 255) 255
(511) 255 + Yj
(Yj)
Xi Yj
Figure 6 Limitation in Split Transfer
Split Write Transfer Cycle (CAS high, DT/OE low, WE low and DSF high at the falling edge of RAS)
A continuous serial write cannot be executed because accessing SAM is inhibited during RAS low in write
transfer. Split write transfer cycle makes it possible. In this cycle, tSTS (min), tRST (min), tCST (min) and tAST
(min) timings must be satisfied like split read transfer cycle. And it is impossible to switch SI/O to input state
in this cycle. If SI/O is in output state, pseudo transfer cycle should be executed to switch SI/O into input
state. Data transferred to SAM by read transfer cycle or split read transfer cycle can be written to other
addresses of RAM by split write transfer cycle. However, pseudo transfer cycle must be executed before split
write transfer cycle. And the MSB of row address (AX8) to write data must be the same as that of the read
transfer cycle or the split read transfer cycle.
SAM Port Operation
Serial Read Cycle
SAM port is in read mode when the previous data transfer cycle is read transfer cycle. Access is
synchronized with SC rising, and SAM data is output from SI/O. When SE is set high, SI/O becomes high
impedance, and the internal pointer is incremented by the SC rising. After indicating the last address (address
511), the internal pointer indicates address 0 at the next access.
HM534253B Series
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Serial Write Cycle
If previous data transfer cycle is pseudo transfer cycle or write transfer cycle, SAM port goes into write mode.
In this cycle, SI/O data is fetched into data register at the SC rising edge like in the serial read cycle. If SE is
high, SI/O data isn’t fetched into data register. Internal pointer is incremented by the SC rising, so SE high
can be used as mask data for SAM. After indicating the last address (address 511), the internal pointer
indicates address 0 at the next access.
Refresh
RAM Refresh
RAM, which is composed of dynamic circuits, requires refresh to retain data. Refresh is executed by
accessing all 512 row addresses within 8 ms. There are three refresh cycles: (1) RAS -only refresh cycle, (2)
CAS-before-RAS (CBR) refresh cycle, and (3) Hidden refresh cycle. Besides them, the cycles which activate
RAS such as read/write cycles or transfer cycles can refresh the row address. Therefore, no refresh cycle is
required when all row addresses are accessed within 8 ms.
(1) RAS-Only Refresh Cycle: RAS-only refresh cycle is executed by activating only RAS cycle with CAS
fixed to high after inputting the row address (= refresh address) from external circuits. To distinguish this
cycle from data transfer cycle, DT/OE must be high at the falling edge of RAS.
(2) CBR Refresh Cycle: CBR refresh cycle is set by activating CAS before RAS. In this cycle, refresh
address need not to be input through external circuits because it is input through an internal refresh
counter. In this cycle, output is in high impedance and power dissipation is lowered because CAS circuits
don’t operate.
(3) Hidden Refresh Cycle: Hidden refresh cycle executes CBR refresh with the data output by reactivating
RAS when DT/OE and CAS keep low in normal RAM read cycles.
SAM Refresh
SAM parts (data register, shift resister and selector), organized as fully static circuitry, require no refresh.
Absolute Maximum Ratings
Parameter Symbol Value Unit Note
Voltage on any pin relative to VSS VT–1.0 to +7.0 V 1
Supply voltage relative to VSS VCC –0.5 to +7.0 V 1
Short circuit output current Iout 50 mA
Power dissipation PT1.0 W
Operating temperature Topr 0 to +70 °C
Storage temperature Tstg –55 to +125 °C
Note: 1. Relative to VSS.
HM534253B Series
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Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter Symbol Min Typ Max Unit Notes
Supply voltage VCC 4.5 5.0 5.5 V 1
Input high voltage VIH 2.4 — 6.5 V 1
Input low voltage VIL –0.5*2 — 0.8 V 1
Notes: 1. All voltage referred to VSS
2 –3.0 V for pulse width ≤ 10 ns.
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)
HM534253B
-6 -7 -8 -10
Parameter Symbol Min Max Min Max Min Max Min Max Unit Test Conditions
Operating
current ICC1 — 75 — 70 — 60 — 55 mA RAS, CAS cycling
tRC = min SC = VIL,
SE = VIH
ICC7 — 125 — 120 — 100 — 95 mA SE = VIL,
SC cycling
tSCC = min
Standby
current ICC2 —7 —7 —7 —7 mARAS, CAS = VIH SC = VIL,
SE = VIH
ICC8 — 50 — 50 — 40 — 40 mA SE = VIL,
SC cycling
tSCC = min
RAS-only
refresh
current
ICC3 — 75 — 70 — 60 — 55 mA RAS cycling
CAS = VIH
tRC = min
SC = VIL,
SE = VIH
ICC9 — 125 — 120 — 100 — 95 mA SE = VIL,
SC cycling
tSCC = min
Page mode
current ICC4 — 80 — 80 — 70 — 65 mA CAS cycling
RAS = VIL
tPC = min
SC = VIL,
SE = VIH
ICC10 — 130 — 130 — 110 — 105 mA SE = VIL,
SC cycling
tSCC = min
CAS-before-
RAS refresh
current
ICC5 — 50 — 45 — 40 — 35 mA RAS cycling
tRC = min SC = VIL,
SE = VIH
ICC11 — 100 — 95 — 80 — 75 mA SE = VIL,
SC cycling
tSCC = min
HM534253B Series
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DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V) (cont)
HM534253B
-6 -7 -8 -10
Parameter Symbol Min Max Min Max Min Max Min Max Unit Test Conditions
Data
transfer
current
ICC6 — 80 — 75 — 65 — 60 mA RAS, CAS cycling
tRC = min SC = VIL,
SE = VIH
ICC12 — 130 — 125 — 105 — 100 mA SE = VIL,
SC cycling
tSCC = min
Input
leakage
current
ILI –10 10 –10 10 –10 10 –10 10 µA
Output
leakage
current
ILO –10 10 –10 10 –10 10 –10 10 µA
Output high
voltage VOH 2.4 — 2.4 — 2.4 — 2.4 — V IOH = –2 mA
Output low
voltage VOL — 0.4 — 0.4 — 0.4 — 0.4 V IOL = 4.2 mA
Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the output
open condition.
2. Address can be changed once while RAS is low and CAS is high.
Capacitance (Ta = 25°C, VCC = 5 V, f = 1 MHz, Bias: Clock, I/O = VCC, address =VSS)
Parameter Symbol Typ Max Unit Note
Input capacitance (Address) CI1 — 5 pF 1
Input capacitance (Clocks) CI2 — 5 pF 1
Output capacitance (I/O, SI/O, QSF) CI/O — 7 pF 1
Note: 1. This parameter is sampled and not 100% tested.
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)*1, *16
Test Conditions
• Input rise and fall time: 5 ns
• Input pulse levels: VSS to 3.0 V
• Input timing reference levels: 0.8 V, 2.4 V
• Output timing reference levels: 0.8 V, 2.0 V
• Output load: See figures
HM534253B Series
18
Test Conditions (cont)
I = – 2 mA
OH
I = 4.2 mA
OL
+ 5 V
I / O * 1
100 pF
I = – 2 mA
I = 4.2 mA
OL
+ 5 V
SI / O * 1
50 pF
OH
Output Load (B)Output Load (A)
Note: 1. Including scope & jigs
Common Parameter
HM534253B
-6 -7 -8 -10
Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes
Random read or write cycle
time tRC 125 — 135 — 150 — 180 — ns
RAS precharge time tRP 55 — 55 — 60 — 70 — ns
RAS pulse width tRAS 60 10000 70 10000 80 10000 100 10000 ns
CAS pulse width tCAS 20 — 20 — 20 — 25 — ns
Row address setup time tASR 0— 0— 0— 0— ns
Row address hold time tRAH 10 — 10 — 10 — 10 — ns
Column address setup time tASC 0— 0— 0— 0— ns
Column address hold time tCAH 15 — 15 — 15 — 15 — ns
RAS to CAS delay time tRCD 20 40 20 50 20 60 20 75 ns 2
RAS hold time referred to
CAS tRSH 20 — 20 — 20 — 25 — ns
CAS hold time referred to
RAS tCSH 60 — 70 — 80 — 100 — ns
CAS to RAS precharge time tCRP 10 — 10 — 10 — 10 — ns
Transition time (rise to fall) tT3 50 3 50 3 50 3 50 ns 3
Refresh period tREF —8 —8 —8 —8 ms
DT to RAS setup time tDTS 0— 0— 0— 0— ns
DT to RAS hold time tDTH 10 — 10 — 10 — 10 — ns
DSF to RAS setup time tFSR 0— 0— 0— 0— ns
DSF to RAS hold time tRFH 10 — 10 — 10 — 10 — ns
HM534253B Series
19
Common Parameter (cont)
HM534253B
-6 -7 -8 -10
Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes
DSF to CAS setup time tFSC 0— 0— 0— 0— ns
DSF to CAS hold time tCFH 15 — 15 — 15 — 15 — ns
Data-in to CAS delay time tDZC 0— 0— 0— 0— ns4
Data-in to OE delay time tDZO 0— 0— 0— 0— ns4
Output buffer turn-off delay
referred to CAS tOFF1 — 20 — 20 — 20 — 20 ns 5
Output buffer turn-off delay
referred to OE tOFF2 — 20 — 20 — 20 — 20 ns 5
Read Cycle (RAM), Page Mode Read Cycle
HM534253B
-6 -7 -8 -10
Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes
Access time from RAS tRAC — 60 — 70 — 80 — 100 ns 6, 7
Access time from CAS tCAC — 20 — 20 — 20 — 25 ns 7, 8
Access time from OE tOAC — 20 — 20 — 20 — 25 ns 7
Address access time tAA — 35 — 35 — 40 — 45 ns 7, 9
Read command setup time tRCS 0— 0— 0— 0— ns
Read command hold time tRCH 0— 0— 0— 0— ns10
Read command hold time
referred to RAS tRRH 10 — 10 — 10 — 10 — ns 10
RAS to column address
delay time tRAD 15 25 15 35 15 40 15 55 ns 2
Column address to RAS lead
time tRAL 35 — 35 — 40 — 45 — ns
Column address to CAS lead
time tCAL 35 — 35 — 40 — 45 — ns
Page mode cycle time tPC 45 — 45 — 50 — 55 — ns
CAS precharge time tCP 10 — 10 — 10 — 10 — ns
Access time from CAS
precharge tACP — 40 — 40 — 45 — 50 ns
Page mode RAS pulse width tRASP 60 100000 70 100000 80 100000 100 100000 ns
HM534253B Series
20
Write Cycle (RAM), Page Mode Write Cycle, Color Register Set Cycle
HM534253B
-6 -7 -8 -10
Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes
Write command setup time tWCS 0— 0— 0— 0— ns11
Write command hold time tWCH 15 — 15 — 15 — 15 — ns
Write command pulse width tWP 15 — 15 — 15 — 15 — ns
Write command to RAS lead
time tRWL 20 — 20 — 20 — 20 — ns
Write command to CAS lead
time tCWL 20 — 20 — 20 — 20 — ns
Data-in setup time tDS 0— 0— 0— 0— ns12
Data-in hold time tDH 15 — 15 — 15 — 15 — ns 12
WE to RAS setup time tWS 0— 0— 0— 0— ns
WE to RAS hold time tWH 10 — 10 — 10 — 10 — ns
Mask data to RAS setup time tMS 0— 0— 0— 0— ns
Mask data to RAS hold time tMH 10 — 10 — 10 — 10 — ns
OE hold time referred to WE tOEH 20 — 20 — 20 — 20 — ns
Page mode cycle time tPC 45 — 45 — 50 — 55 — ns
CAS precharge time tCP 10 — 10 — 10 — 10 — ns
CAS to data-in delay time tCDD 20 — 20 — 20 — 20 — ns 13
Page mode RAS pulse width tRASP 60 100000 70 100000 80 10000 100 100000 ns
HM534253B Series
21
Read-Modify-Write Cycle
HM534253B
-6 -7 -8 -10
Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes
Read-modify-write cycle time tRWC 175 — 185 — 200 — 230 — ns
RAS pulse width (read-
modify-write cycle) tRWS 110 10000 120 10000 130 10000 150 10000 ns
CAS to WE delay time tCWD 45 — 45 — 45 — 50 — ns 14
Column address to WE delay
time tAWD 60 — 60 — 65 — 70 — ns 14
OE to data-in delay time tODD 20 — 20 — 20 — 20 — ns 12
Access time from RAS tRAC — 60 — 70 — 80 — 100 ns 6, 7
Access time from CAS tCAC — 20 — 20 — 20 — 25 ns 7, 8
Access time from OE tOAC — 20 — 20 — 20 — 25 ns 7
Address access time tAA — 35 — 35 — 40 — 45 ns 7, 9
RAS to column address
delay time tRAD 15 25 15 35 15 40 15 55 ns
Read command setup time tRCS 0— 0— 0— 0— ns
Write command to RAS lead
time tRWL 20 — 20 — 20 — 20 — ns
Write command to CAS lead
time tCWL 20 — 20 — 20 — 20 — ns
Write command pulse width tWP 15 — 15 — 15 — 15 — ns
Data-in setup time tDS 0— 0— 0— 0— ns12
Data-in hold time tDH 15 — 15 — 15 — 15 — ns 12
OE hold time referred to WE tOEH 20 — 20 — 20 — 20 — ns
Refresh Cycle
HM534253B
-6 -7 -8 -10
Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes
CAS setup time (CAS-
before-RAS refresh) tCSR 10 — 10 — 10 — 10 — ns
CAS hold time (CAS-before-
RAS refresh) tCHR 10 — 10 — 10 — 10 — ns
RAS precharge to CAS hold
time tRPC 10 — 10 — 10 — 10 — ns
HM534253B Series
22
Flash Write Cycle, Block Write Cycle
HM534253B
-6 -7 -8 -10
Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes
CAS to data-in delay time tCDD 20 — 20 — 20 — 20 — ns 13
OE to data-in delay time tODD 20 — 20 — 20 — 20 — ns 13
Read Transfer Cycle
HM534253B
-6 -7 -8 -10
Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes
DT hold time referred to RAS tRDH 50 10000 60 10000 65 10000 80 10000 ns
DT hold time referred to CAS tCDH 20 — 20 — 20 — 25 — ns
DT hold time referred to
column address tADH 25 — 25 — 30 — 30 — ns
DT precharge time tDTP 20 — 20 — 20 — 30 — ns
DT to RAS delay time tDRD 65 — 65 — 70 — 80 — ns
SC to RAS setup time tSRS 25 — 25 — 30 — 30 — ns
1st SC to RAS hold time tSRH 60 — 70 — 80 — 100 — ns
1st SC to CAS hold time tSCH 25 — 25 — 25 — 25 — ns
1st SC to column address
hold time tSAH 40 — 40 — 45 — 50 — ns
Last SC to DT delay time tSDD 5— 5— 5— 5— ns
Last SC to DT delay time tSDD2 25 — 25 — 25 — 25 — ns 19
1st SC to DT hold time tSDH 10 — 10 — 15 — 15 — ns
RAS to QSF delay time tRQD — 65 — 70 — 75 — 85 ns 15
CAS to QSF delay time tCQD — 35 — 35 — 40 — 40 ns 15
DT to QSF delay time tDQD — 35 — 35 — 35 — 35 ns 15
QSF hold time referred to
RAS tRQH 20 — 20 — 20 — 25 — ns
QSF hold time referred to
CAS tCQH 5— 5— 5— 5— ns
QSF hold time referred to DT tDQH 5— 5— 5— 5— ns
Serial data-in to 1st SC delay
time tSZS 0— 0— 0— 0— ns
Serial clock cycle time tSCC 25 — 25 — 30 — 30 — ns
HM534253B Series
23
Read Transfer Cycle (cont)
HM534253B
-6 -7 -8 -10
Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes
SC pulse width tSC 5— 5— 10— 10— ns
SC precharge time tSCP 10 — 10 — 10 — 10 — ns
SC access time tSCA — 20 — 22 — 25 — 25 ns 15
Serial data-out hold time tSOH 5— 5— 5— 5— ns
Serial data-in setup time tSIS 0— 0— 0— 0— ns
Serial data-in hold time tSIH 15 — 15 — 15 — 15 — ns
RAS to column address
delay time tRAD 15 25 15 35 15 40 15 55 ns
Column address to RAS lead
time tRAL 35 — 35 — 40 — 45 — ns
RAS precharge to DT high
hold time tDTHH 10 — 10 — 10 — 10 — ns 18
HM534253B Series
24
Pseudo Transfer Cycle, Write Transfer Cycle
HM534253B
-6 -7 -8 -10
Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes
SE setup time referred to
RAS tES 0— 0— 0— 0— ns
SE hold time referred to RAS tEH 10 — 10 — 10 — 10 — ns
SC setup time referred to
RAS tSRS 25 — 25 — 30 — 30 — ns
RAS to SC delay time tSRD 20 — 20 — 25 — 25 — ns
Serial output buffer turn-off
time referred to RAS tSRZ 10 40 10 40 10 45 10 50 ns
RAS to serial data-in delay
time tSID 40 — 40 — 45 — 50 — ns
RAS to QSF delay time tRQD — 65 — 70 — 75 — 85 ns 15
CAS to QSF delay time tCQD — 35 — 35 — 40 — 40 ns 15
QSF hold time referred to
RAS tRQH 20 — 20 — 20 — 25 — ns
QSF hold time referred to
CAS tCQH 5— 5— 5— 5— ns
Serial clock cycle time tSCC 25 — 25 — 30 — 30 — ns
SC pulse width tSC 5— 5— 10— 10— ns
SC precharge time tSCP 10 — 10 — 10 — 10 — ns
SC access time tSCA — 20 — 22 — 25 — 25 ns 15
SE access time tSEA — 20 — 22 — 25 — 25 ns 15
Serial data-out hold time tSOH 5— 5— 5— 5— ns
Serial write enable setup
time tSWS 5— 5— 5— 5— ns
Serial data-in setup time tSIS 0— 0— 0— 0— ns
Serial data-in hold time tSIH 15 — 15 — 15 — 15 — ns
HM534253B Series
25
Split Read Transfer Cycle, Split Write Transfer Cycle
HM534253B
-6 -7 -8 -10
Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes
Split transfer setup time tSTS 20 — 20 — 20 — 25 — ns
Split transfer hold time
referred to RAS tRST 60 — 70 — 80 — 100 — ns
Split transfer hold time
referred to CAS tCST 20 — 20 — 20 — 25 — ns
Split transfer hold time
referred to column address tAST 35 — 35 — 40 — 45 — ns
SC to QSF delay time tSQD — 30 — 30 — 30 — 30 ns 15
QSF hold time referred to SC tSQH 5— 5— 5— 5— ns
Serial clock cycle time tSCC 25 — 25 — 30 — 30 — ns
SC pulse width tSC 5— 5— 10— 10— ns
SC precharge time tSCP 10 — 10 — 10 — 10 — ns
SC access time tSCA — 20 — 22 — 25 — 25 ns 15
Serial data-out hold time tSOH 5— 5— 5— 5— ns
Serial data-in setup time tSIS 0— 0— 0— 0— ns
Serial data-in hold time tSIH 15 — 15 — 15 — 15 — ns
RAS to column address
delay time tRAD 15 25 15 35 15 40 15 55 ns
Column address to RAS lead
time tRAL 35 — 35 — 40 — 45 — ns
HM534253B Series
26
Serial Read Cycle, Serial Write Cycle
HM534253B
-6 -7 -8 -10
Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes
Serial clock cycle time tSCC 25 — 25 — 30 — 30 — ns
SC pulse width tSC 5— 5— 10— 10— ns
SC precharge width tSCP 10 — 10 — 10 — 10 — ns
Access time from SC tSCA — 20 — 22 — 25 — 25 ns 15
Access time from SE tSEA — 20 — 22 — 25 — 25 ns 15
Serial data-out hold time tSOH 5— 5— 5— 5— ns
Serial output buffer turn-off
time referred to SE tSEZ — 20 — 20 — 20 — 20 ns 5
Serial data-in setup time tSIS 0— 0— 0— 0— ns
Serial data-in hold time tSIH 15 — 15 — 15 — 15 — ns
Serial write enable setup
time tSWS 5— 5— 5— 5— ns
Serial write enable hold time tSWH 15 — 15 — 15 — 15 — ns
Serial write disable setup
time tSWIS 5— 5— 5— 5— ns
Serial write disable hold time tSWIH 15 — 15 — 15 — 15 — ns
Notes: 1. AC measurements assume tT = 5 ns.
2. When tRCD > tRCD (max) and tRAD > tRAD (max), access time is specified by tCAC or tAA.
3. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition time tT
is measured between VIH and VIL.
4. Data input must be floating before output buffer is turned on. In read cycle, read-modify-write cycle
and delayed write cycle, either tDZC (min) or tDZO (min) must be satisfied.
5. tOFF1 (max), tOFF2 (max), and tSEZ (max) are defined as the time at which the output achieves the open
circuit condition (VOH – 100 mV, VOL + 100 mV).
6. Assume that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
7. Measured with a load circuit equivalent to 2 TTL loads and 100 pF.
8. When tRCD ≥ tRCD (max) and tRAD ≤ tRAD (max), access time is specified by tCAC.
9. When tRCD ≤ tRCD (max) and tRAD ≥ tRAD (max), access time is specified by tAA.
10.If either tRCH or tRRH is satisfied, operation is guaranteed.
11.When tWCS ≥ tWCS (min), the cycle is an early write cycle, and I/O pins remain in an open circuit (high
impedance) condition.
12.These parameters are specified by the later falling edge of CAS or WE.
13.Either tCDD (min) or tODD (min) must be satisfied because output buffer must be turned off by CAS or
OE prior to applying data to the device when output buffer is on.
14.When tAWD ≥ tAWD (min) and tCWD ≥ tCWD (min) in read-modify-write cycle, the data of the selected
address outputs to an I/O pin and input data is written into the selected address. tODD (min) must be
satisfied because output buffer must be turned off by OE prior to applying data to the device.
15.Measured with a load circuit equivalent to 2 TTL loads and 50 pF.
HM534253B Series
27
16.After power-up, pause for 100 µs or more and execute at least 8 initialization cycle (normal memory
cycle or refresh cycle), then start operation.
17.When the serial write cycle is used, at least one SC pulse is required before proper SAM operation
after VCC stabilized.
18.tDTHH (min) must be satisfied only if DT/OE rises up before RAS rises in a read transfer cycle.
19.After read transfer cycle, if split read transfer cycle is executed without SC access and SC address
is 254 or 510, tSDD2 (min) must be satisfied 25 ns. Except for those cases, tSDD (min) is effective and
satisfied 5 ns.
20.XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max))
///////: Invalid Dout
Timing Waveforms*20
Read Cycle
tRC
tRAS
tCSH
tRCD tRSHtCAS
tRAL tCAL
tCAH
tASC
tRAH
tASR
tRCS
tCAC
tAA
tRAC
tOAC
tDZC
tDZO
tDTH
tDTS
tFSR tRFH tFSC tCFH
tCDD
tOFF1
tOFF2
tRRH tRCH
tRP
tCRP
RAS
CAS
Address
WE
I/O
(Output)
DT/OE
DSF
I/O
(Input)
Row Column
tRAD
Valid Dout
HM534253B Series
28
Early Write Cycle
tRC
RAS
CAS
Address
WE
I/O
(Output)
DT/OE
DSF
I/O
(Input)
tRAS tRP
tCRP
tCSH tRSH
tCAS
tCAH
tASC
tRAH
tASR
tWS tWH tWCS tWCH
tDTS
tMH tDS tDH
tMS
tDTH
tFSR tFSC
tRFH tCFH
tRCD
High-Z
*1
Row Column
Valid DinMask Data
Note: 1. This cycle becomes a normal mode write cycle when WE is high and a mask write cycle when
WE is low.
Delayed Write Cycle
RAS
CAS
Address
WE
I/O
(Output)
DT/OE
DSF
I/O
(Input)
Row Columun
*1
Valid Din
Mask Data
tRC
tRAS tRP
tCRP
tCSH
tRSH
tRCD tCAS
tASR tRAH tCAH
tRWL tCWL
tWP
tWS tWH
tMS tMH tDS
tDZC
tDTS tDTH
tFSR tRFH tFSC tCFH
tOEH
tDH
tOFF2
tODD
tASC
Note: 1. This cycle becomes a normal mode write cycle when WE is high and a mask write cycle when
WE is low.
HM534253B Series
29
Read-Modify-Write Cycle
RAS
CAS
Address
WE
I/O
(Output)
DT/OE
DSF
I/O
(Input)
Row Columun
Valid Dout
Mask Data
tRWC
Valid Din
*1
tRWS tRP
tCRP
tRWL
tCWL
tWP
tAWD
tCWD
tRCS
tWS tWH
tCAC
tAA
tRAC
tOAC
tDZC
tMH
tMS
tOFF2
tODD
tDS tDH
tOEH
tDTS tDTH tDZO
tFSC
tRFH
tFSR tCFH
tRAD
tRCD
tASR tRAH tASC tCAH
Note: 1. This cycle becomes a normal mode write cycle when WE is high and a mask write cycle when
WE is low.
Page Mode Read Cycle
RAS
CAS
Address
WE
I/O
(Output)
DT/OE
DSF
I/O
(Input)
tRC
tRASP tRP
tCRP
tRSH
tCAS
tCP
tPC
tCP
tRCD
tCSH
tRAD tCAL
tCAH
tRAH
tASR
tRCS tRCH tRCS tRCS
tRCH
tCAH
tASC tCAL tASC
tRAL tCAL
tCAH
tRRH
tRCH
tCAS
tCAS
tAA tOFF1
tACP
tCAC
tAA
tACP tOFF1
tCDD
tOAC
tDZC
tCDD
tOAC tOFF2
tDZC
tCDD
tOFF2
tOAC
tDZC
tDZO
tDTH
tFSR
tDTS
tRFH tFSC tCFH tFSC tCFH tFSC tCFH
tRAC
tAA
tCAC
tOFF1
tASC
tCAC
Row
Columun Columun Columun
Valid
Dout Valid
Dout Valid Dout
HM534253B Series
30
Page Mode Write Cycle (Early Write)
RAS
CAS
Address
WE
I/O
(Output)
DT/OE
DSF
I/O
(Input)
tRC
tRASP
tCSH tCAS
tRCD tCP tCAS
tPC tCP tRSH
tCAS tCRP
tRP
tCAH
tASC
tCAH
tASC
tCAH
tASC
tRAH
tASR
tWS tWH tWCS tWCH tWCS tWCH tWCH
tWCS
tDS tDH
tDH
tDS
tDH
tDS
tMH
tMS
tDTS tDTH
tFSR tRFH tFSC tCFH tFSC tCFH tFSC tCFH
Row Column Column Column
*1
Valid Din Valid Din Valid Din
Mask
Data
High-Z
Note: 1. This cycle becomes a normal mode write cycle when WE is high and a mask write cycle when
WE is low.
Page Mode Write Cycle (Delayed Write)
RAS
CAS
Address
WE
I/O
(Output)
DT/OE
DSF
I/O
(Input)
tRC
tRASP
tCSH
tRCD tCAS
tPC
tCP tCAS tCP tRSH
tCAS
tRP
tCRP
tCAH
tASC
tRWL tCWL
tWP
tCWL
tWP
tCWL
tWP
tCAH
tASC
tCAH
tASC
tRAH
tASR
tWS tWH
tMH
tMS
tDTS
tFSR tRFH tCFH
tFSC tFSC tCFH tFSC tCFH
tOEH
tDH
tDS tDH tDS tDH tDS
Row Column Column Column
*1
Mask
Data Valid
Din Valid
Din Valid
Din
Note: 1. This cycle becomes a normal mode write cycle when WE is high and a mask write cycle when
WE is low.
HM534253B Series
31
RAS-Only Refresh Cycle
RAS
CAS
Address
I/O
(Output)
DT/OE
DSF
I/O
(Input)
tRC
tRAS tRP
tRPC
tASR tRAH
tCRP
tCDD
tOFF1
tOFF2 tODD
tDTS tDTH
tFSR tRFH
Row
CAS-Before-RAS Refresh Cycle
RAS
CAS
Address
I/O
(Output)
DT/OE
DSF
tRC
tRAS tRP
tRPC tCSR
tCHR
tRP
tRPC tCSR
tCP
tOFF1 High-Z
WE
Inhibit Falling Transition
HM534253B Series
32
Hidden Refresh Cycle
RAS
CAS
Address
I/O
(Output)
DT/OE
DSF
I/O
(Input)
tRC
WE
tRAS
tRCD tRSH
tRAL
tRAD
tASR tASC tCAH
tRCS tRRH
tCAC
tAA
tCHR
tRAS
tRP
tRC
tRP
tCRP
tOFF1
tOFF2
tDZC tOAC
tDZO
tDTH
tDTS
tFSR tRFH tFSC tCFH
tRAH
Row Column
tRAC Valid Dout
Color Register Set Cycle (Early Write)
RAS
CAS
Address
WE
I/O
(Output)
DT/OE
DSF
I/O
(Input)
tRC
tRAS tRP
tCRP
tCSH tRSH
tRCD tCAS
tRAH
tASR
tWS tWH tWCS tWCH
tDH
tDS
tDTS tDTH
tRFH
tFSR
Color Data
Row
High-Z
HM534253B Series
33
Color Register Set Cycle (Delayed Write)
RAS
CAS
Address
WE
I/O
(Output)
DT/OE
DSF
I/O
(Input)
tRC
tRAS
tCSH
tRCD
tRP
tCRP
tCAS
tRSH
tASR tRAH
tWS
tDTS
tFSR tRFH
tOEH
tDS tDH
tCWL
tWP
Color Data
Row
High-Z
tRWL
Color Register Read Cycle
tRC
tRAS
tCSH
tRCD tRSH
tCAS
tASR tRAH
tWH
tWS tRCS
tRP
tCRP
tRRH tRCH
tCDD
tOFF1
tODD
tOFF2
tCAC
tRAC
tDZC tOAC
tDZO
tDTH
tDTS
tFSR tRFH
RAS
CAS
Address
WE
I/O
(Output)
I/O
(Input)
DT/OE
DSF
Row
Valid Out
HM534253B Series
34
Flash Write Cycle
tRAS
RAS
CAS
Address
WE
I/O
(Output)
I/O
(Input)
DT/OE
DSF
tRC tRP
tRCD
tCRP
tASR tRAH
tWH
tWS
tCDD
tOFF2 tODD tMS
tDTS tDTH
tMH
tRFH
tFSR
High-Z
Row
Mask Data
tOFF1
Block Write Cycle
tRAS
RAS
CAS
Address
WE
I/O
(Output)
I/O
(Input)
DT/OE
DSF
tRC tRP
tCRP
tRSH
tRCD
tCSH
tCRP
tASR tRAH tASC tCAH
tWS tWH
tCDD
tOFF1
tOFF2 tODD tMS tMH
tDTH
tDS tDH
tFSR tRFH tFSC tCFH
tDTS
Row
Column A2-A8
*1
I/O Mask Data Address
Mask Data
High-Z
Note: 1. This cycle becomes a normal block write cycle when WE is high and a mask block write cycle
when WE is low.
HM534253B Series
35
Page Mode Block Write Cycle
tRC
RAS
CAS
Address
WE
I/O
(Output)
DT/OE
DSF
I/O
(Input)
tRASP tRP
tRSH
tCAS tCRP
tCP
tPC tCAS
tCP
tCAS
tRCDtCSH
tASC
tASC
tASR tRAH tCAH tCAH
tWS tWH
tMS tMH tDS tDH tDS tDH tDS tDH
tASC tCAH
tFSC tCFH
tCFH
tFSC
tCFH
tFSC
tDTH
tDTS
tFSR tRFH
Row
*1
I/O
Mask
Column
A2-A8 Column
A2-A8 Column
A2-A8
Address
Mask
Address
Mask
Address
Mask
High-Z
Note: 1. This cycle becomes a normal block write cycle when WE is high and a mask block write cycle
when WE is low.
HM534253B Series
36
Read Transfer Cycle (1)
tRC
tRAS
tCSH
tRCD tRSH
tCAS
tCAH
tASC tRAL
tRAD
tASR tRAH
tWH
tWS
tDTS tCDH
tADH
tRDH
tDRD
tDTP
tDTHH
tSCC
tSDH tSC tSCP
tSOH
tSCA tSCA
tSOH tSOH
tSCA
tSDD
tSCA tSOH
Previous Row New Row
tRP
RAS
CAS
Address
WE
I/O
(Output)
DT/OE
SC
SI/O
(Output)
SI/O
(Input)
tSOH
Valid Sout Valid Sout Valid Sout Valid Sout
High-Z
Row SAM Start
Address
tCRP
tFSR tRFH
tCQD
tCQH
tRQH
tRQD
tDQD
tDQH
SAM Address MSB
QSF *1
QSF *2
SAM Address MSB
DSF
Valid Sout
Notes: 1. This QSF timing is referred when SC is risen once or more between the previous transfer cycle
and CAS falling edge of this cycle (QSF is switched by DT rising).
2. This QSF timing is referred when SC isn't risen between the previous transfer cycle and CAS
falling edge of this cycle (QSF is switched by RAS or CAS falling).
3. After read transfer cycle, if split read transfer cycle is executed without SC access and SC
address is 254 or 510, tSDD2 (min) must be satisfied 25 ns. Except for those cases, tSDD
(min) is effective and satisfied 5 ns.
tSCC
tSCC
tSCC
tSDD2*3
HM534253B Series
37
Read Transfer Cycle (2)
tRAS
RAS
CAS
Address
WE
I/O
(Output)
DT/OE
DSF
SC
SI/O
(Output)
QSF
SI/O
(Input)
tRC
tRSH
tCAS
tCSH
tRCD
tRAD
tRAH
tASR tASC tCAH
tWH
tWS
tRP
tCRP
tRAL
tDTS
tRFH
tFSR
tDRD
tDTP
tSRS
tSC tSDH tSCC
tSC tSCP
tSCA
tSCP
tSCA
tSOH
tSZS
tDQD
tDQH
tSIH
tSIS Valid Sout
Row Sam Start
Address
High-Z
SAM Address MSB
Valid
Sin
tDTHH
Inhibit Rising Transition
tDTH
tSAH
tSCH
tSRH
tCQD
tCQH
tRQD
tRQH
HM534253B Series
38
Pseudo Transfer Cycle
RAS
CAS
Address
WE
I/O
(Output)
DT/OE
DSF
SE
SI/O
(Output)
QSF
SI/O
(Input)
SAM Address MSB
SC
tRC
tRAS tRP
tCRP
tRSH
tCAS
tRCD
tASR tRAH tASC tCAH
tWH
tWS
tDTS
tFSR
tDTH
tRFH
tSEZ
tEHtES
tSRS
tSC
tSCA
tSOH tSRZ
tSID
tCQD
tCQH
tRQD
tRQH
tSIS tSIH tSIS tSIH
tSWS
tSRD
tSCP
tSCC
tSC tSCP
Valid Sin Valid Sin
Row SAM Start
Address
Valid Sout
tCSH
High - Z
Valid
Sout
Inhibit Rising Transition
HM534253B Series
39
Write Transfer Cycle
RAS
CAS
Address
WE
I/O
(Output)
DT/OE
DSF
SE
SI/O
(Output)
QSF
SI/O
(Input)
SC
tRC
tRAS tRP
tCRP
tRSH
tCAS
tRCD
tASR tRAH tASC tCAH
tWH
tWS
tDTS
tFSR
tDTH
tRFH
Row SAM Start
Address
tES tEH
tSRS
tSWS tSC
tSIHtSIS
tCQDtCQH
tRQD
tRQH
tSWS
tSRD
tSCP
tSCC
tSC tSCP
tSIS tSIH tSIS tSIH
High-Z
Valid Sin Valid Sin Valid Sin
SAM Address MSB
tCSH
Inhibit Rising Transition
HM534253B Series
40
Split Read Transfer Cycle
tRC
RAS
CAS
Address
WE
I/O
(Output)
DT/OE
DSF
SE
SI/O
(Output)
QSF
SI/O
(Input)
SC
tRAS tRP
tCSH
tRSH
tRCD
tCAS
tASC
tRAH
tASR
tWS tWH
tOFF1
tDTS tDTH
tFSR tRFH
tRSTtAST
tCST
tSCC
tSC tSCP
tSTS
tSQD
tSQH
tSQD
tSQH
SAM Address MSB
Valid
Sout Valid
Sout
Valid
Sout
Valid
Sout
Valid Sout
511
(255) n
(n+255) n+1
(n+256) 253
(509) 254
(510) 255
(511)
n+2
(n+257)
Yi+255
(Yi)
High-Z
Low
Row SAM Start
Address Yi
tCAH tRAL
tRAD
tSCA
tSOHtSOH
tSCA
Valid
Sout
tCRP tCRP
HM534253B Series
41
Split Write Transfer Cycle
tRC
RAS
CAS
Address
WE
I/O
(Output)
DT/OE
DSF
SE
SI/O
(Output)
QSF
SI/O
(Input)
SC
tRAS tRP
tCSH
tRSH
tRCD
tCAS
tASC
tRAH
tASR
tWS tWH
tOFF1
tDTS tDTH
tFSR tRFH
tRSTtAST
tCST
tSCC
tSC tSCP
tSTS
tSIS tSIH tSIS tSIH
tSQD
tSQH
tSQD
tSQH
SAM Address MSB
Valid
Sin Valid
Sin Valid
Sin
Valid
Sin
Valid
Sin
Valid Sin
511
(255) n
(n+255) n+1
(n+256) 254
(510) 255
(511)
n+2
(n+257)
Yi+255
(Yi)
High-Z
Low
Row SAM Start
Address Yi
tCAH tRAL
tSIS tSIH
Valid Sin
n+3
(n+258)
HM534253B Series
42
Serial Read Cycle
SE
SC
SI/O
(Output)
tSCC
tSCP
tSC
tSCA
tSOH tSEZ
tSC tSCP tSC
tSEA
tSCA
tSCP tSC
tSCA
tSOH
Valid Sout Valid Sout Valid Sout Valid
Sout
tSCC
tSCC
Serial Write Cycle
SE
SC
SI/O
(Input) Valid Sin Valid Sin Valid Sin
tSWH tSWIS tSWIH tSWS
tSCC
tSC tSCP
tSIS tSIH
tSCC
tSCP
tSC
tSCC
tSCtSCP
tSC
tSIS tSIH
tSIH
tSIS
HM534253B Series
43
Package Dimensions
HM534253BJ Series (CP-28D) Unit: mm
9.40 ± 0.25
114
0.43 ± 0.10
3.50 ± 0.26
+ 0.21
– 0.24
2.40
15
28 18.54 Max
18.17
0.74
10.16 ± 0.13
11.18 ± 0.13
1.30 Max
0.10
0.80 +0.25
–0.17
1.27
HM534253BZ Series (ZP-28) Unit: mm
0.25+ 0.10
– 0.05
0.50
35.58
1.27 2.54
8.71
10.16 Max
2.80 Min
2.85
36.57 Max
1
+ 0.08
– 0.12
28
1.045 Max
0.3 M
