HM534253B Series 262,144-word x 4-bit Multiport CMOS Video RAM ADE-203-204C (Z) Rev. 3.0 Apr. 24, 1995 Description The HM534253B is a 1-Mbit multiport video RAM equipped with a 256-kword x 4-bit dynamic RAM and a 512-word x 4-bit SAM (serial access memory). Its RAM and SAM operate independently and asynchronously. It can transfer data between RAM and SAM. In addition, it has two modes to realize fast writing in RAM. Block write and flash write modes clear the data of 4-word x 4-bit and the data of one row (512-word x 4-bit) respectively in one cycle of RAM. And the HM534253B makes split transfer cycle possible by dividing SAM into two split buffers equipped with 256-word x 4-bit each. This cycle can transfer data to SAM which is not active, and enables a continuous serial access. Features * Multiport organization Asynchronous and simultaneous operation of RAM and SAM capability RAM: 256-kword x 4-bit SAM: 512-word x 4-bit * Access time RAM: 60 ns/70 ns/80 ns/100 ns max SAM: 20 ns/22 ns/25 ns/25 ns max * Cycle time RAM: 125 ns/135 ns/150 ns/180 ns min SAM: 25 ns/25 ns/30 ns/30 ns min * Low power Active RAM: 413 mW max SAM: 275 mW max Standby 38.5 mW max * High-speed page mode capability * Mask write mode capability * Bidirectional data transfer cycle between RAM and SAM capability * Split transfer cycle capability * Block write mode capability * Flash write mode capability HM534253B Series * 3 variations of refresh (8 ms/512 cycles) RAS-only refresh CAS-before-RAS refresh Hidden refresh * TTL compatible Ordering Information Type No. Access Time Package HM534253BJ-6 HM534253BJ-7 HM534253BJ-8 HM534253BJ-10 60 ns 70 ns 80 ns 100 ns 400-mil 28-pin plastic SOJ (CP-28D) HM534253BZ-6 HM534253BZ-7 HM534253BZ-8 HM534253BZ-10 60 ns 70 ns 80 ns 100 ns 400-mil 28-pin plastic ZIP (ZP-28) Pin Arrangement HM534253BJ Series SC SI/O0 SI/O1 DT/OE I/O0 I/O1 WE NC RAS A8 A6 A5 A4 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 HM534253BZ Series 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS SI/O3 SI/O2 SE I/O3 I/O2 DSF CAS QSF A0 A1 A2 A3 A7 I/O2 SE SI/O3 SC SI/O1 I/O0 WE RAS A6 A4 A7 A2 A0 CAS 2 4 6 8 10 12 14 16 18 20 22 24 26 28 1 3 5 7 9 11 13 15 17 19 21 23 25 27 (Top View) (Bottom View) 2 DSF I/O3 SI/O2 VSS SI/O0 DT/OE I/O1 NC A8 A5 VCC A3 A1 QSF HM534253B Series Pin Description Pin Name Function A0 - A8 Address inputs I/O0 - I/O3 RAM port data inputs/outputs SI/O0 - SI/O3 SAM port data inputs/outputs RAS Row address strobe CAS Column address strobe WE Write enable DT/OE Data transfer/output enable SC Serial clock SE SAM port enable DSF Special function input flag QSF Special function output flag VCC Power supply VSS Ground NC No connection 3 HM534253B Series Block Diagram A0 - A8 Refresh Counter Serial Address Counter Serial Output Buffer Color Register Mask Register Input Data Control Address Mask Register Data Register Transfer Gate Data Register Memory Array Transfer Gate Sense Amplifier & I/O Bus Column Decoder Block Write Flash Write Control Control Row Decoder Serial Input Buffer SI/O0 - SI/O3 Input Buffer Output Buffer Timing Generator RAS CAS DT/OE WE DSF SC SE I/O0 - I/O3 4 SAM Column Decoder Row Address Buffer SAM I/O Bus Column Address Buffer QSF HM534253B Series Pin Functions RAS (input pin): RAS is a basic RAM signal. It is active in low level and standby in high level. Row address and signals as shown in table 1 are input at the falling edge of RAS. The input level of these signals determine the operation cycle of the HM534253B. Table 1 Operation Cycles of the HM534253B Input Level At The Falling Edge Of RAS CAS DT/OE WE SE DSF DSF At The Falling Edge Of CAS Operation Mode L X X X X -- CBR refresh H L L L L X Write transfer H L L H L X Pseudo transfer H L L X H X Split write transfer H L H X L X Read transfer H L H X H X Split read transfer H H L X L L Read/mask write H H L X L H Mask block write H H L X H X Flash write H H H X L L Read/write H H H X L H Block write H H H X H X Color register read/write Note: X: H or L. CAS (input pin): Column address and DSF signals are fetched into chip at the falling edge of CAS, which determines the operation mode of the HM534253B. CAS controls output impedance of I/O in RAM. A0 - A8 (input pins): Row address is determined by A0 - A8 level at the falling edge of RAS. Column address is determined by A0 - A8 level at the falling edge of CAS. In transfer cycles, row address is the address on the word line which transfers data with SAM data register, and column address is the SAM start address after transfer. WE (input pin): W E pin has two functions at the falling edge of RAS and after. When WE is low at the falling edge of RAS, the HM534253B turns to mask write mode. According to the I/O level at the time, write on each I/O can be masked. (WE level at the falling edge of RAS is don't care in read cycle.) When WE is high at the falling edge of RAS, a normal write cycle is executed. After that, WE switches read/write cycles as in a standard DRAM. In a transfer cycle, the direction of transfer is determined by WE level at the falling edge of RAS. When WE is low, data is transferred from SAM to RAM (data is written into RAM), and when WE is high, data is transferred from RAM to SAM (data is read from RAM). 5 HM534253B Series I/O0 - I/O3 (input/output pins): I/O pins function as mask data at the falling edge of RAS (in mask write mode). Data is written only to high I/O pins. Data on low I/O pins are masked and internal data are retained. After that, they function as input/output pins as those of a standard DRAM. In block write cycle, they function as address mask data at the falling edges of CAS. DT/OE (input pin): D T/OE pin functions as DT (data transfer) pin at the falling edge of RAS and as OE (output enable) pin after that. When DT is low at the falling edge of RAS, this cycle becomes a transfer cycle. When DT is high at the falling edge of RAS, RAM and SAM operate independently. SC (input pin): SC is a basic SAM clock. In a serial read cycle, data outputs from an SI/O pin synchronously with the rising edge of SC. In a serial write cycle, data on an SI/O pin at the rising edge of SC is fetched into the SAM data register. SE(input pin): SE pin activates SAM. When SE is high, SI/O is in the high impedance state in serial read cycle and data on SI/O is not fetched into the SAM data register in serial write cycle. SE can be used as a mask for serial write because internal pointer is incremented at the rising edge of SC. SI/O0 - SI/O3 (input/output pins): SI/Os are input/output pins in SAM. Direction of input/output is determined by the previous transfer cycle. When it was a read transfer cycle, SI/O outputs data. When it was a pseudo transfer cycle or write transfer cycle, SI/O inputs data. DSF (input pin): DSF is a special function data input flag pin. It is set to high at the falling edge of RAS when new functions such as color register read/write, split transfer, and flash write, are used. DSF is set to high at the falling edge of CAS when block write is executed. QSF (output pin): QSF outputs data of address A8 in SAM. QSF is switched from low to high by accessing address 255 in SAM and from high to low by accessing 511 address in SAM. 6 HM534253B Series Operation of HM534253B RAM Port Operation RAM Read Cycle (DT/OE high, CAS high and DSF low at the falling edge of RAS, DSF low at the falling edge of CAS) Row address is entered at the RAS falling edge and column address at the CAS falling edge to the device as in standard DRAM. Then, when WE is high and DT/OE is low while CAS is low, the selected address data outputs through I/O pin. At the falling edge of RAS, DT/OE and CAS become high to distinguish RAM read cycle from transfer cycle and CBR refresh cycle. Address access time (tAA) and RAS to column address delay time (tRAD) specifications are added to enable high-speed page mode. RAM Write Cycle (Early Write, Delayed Write, Read-Modify-Write) (DT/OE high, CAS high and DSF low at the falling edge of RAS, DSF low at the falling edge of CAS) * Normal Mode Write Cycle (WE high at the falling edge of RAS) When CAS and WE are set low after driving RAS low, a write cycle is executed and I/O data is written in the selected addresses. When all 4 I/Os are written, WE should be high at the falling edge of RAS to distinguish normal mode from mask write mode. If WE is set low before the CAS falling edge, this cycle becomes an early write cycle and all I/O become in high impedance. Data is entered at the CAS falling edge. If WE is set low after the CAS falling edge, this cycle becomes a delayed write cycle. Data is input at the WE falling. I/O does not become high impedance in this cycle, so data should be entered with OE in high. If WE is set low after tCWD (min) and t AWD (min) after the CAS falling edge, this cycle becomes a readmodify-write cycle and enables read/write at the same address in one cycle. In this cycle also, to avoid I/O contention, data should be input after reading data and driving OE high. * Mask Write Mode (WE low at the falling edge of RAS) If WE is set low at the falling edge of RAS, the cycle becomes a mask write mode which writes only to selected I/O. Whether or not an I/O is written depends on I/O level (mask data) at the falling edge of RAS. Then the data is written in high I/O pins and masked in low ones and internal data is retained. This mask data is effective during the RAS cycle. So, in high-speed page mode, the mask data is retained during the page access. 7 HM534253B Series High-Speed Page Mode Cycle (DT/OE high, CAS high and DSF low at the falling edge of RAS) High-speed page mode cycle reads/writes the data of the same row address at high speed by toggling CAS while RAS is low. Its cycle time is one third of the random read/write cycle. In this cycle, read, write, and block write cycles can be mixed. Note that address access time (tAA), RAS to column address delay time (tRAD), and access time from CAS precharge (t ACP ) are added. In one RAS cycle, 512-word memory cells of the same row address can be accessed. It is necessary to specify access frequency within tRASP max (100 s). Color Register Set/Read Cycle (CAS high, DT/OE high, WE high and DSF high at the falling edge of RAS) In color register set cycle, color data is set to the internal color register used in flash write cycle or block write cycle. 4 bits of internal color register are provided at each I/O. This register is composed of static circuits, so once it is set, it retains the data until reset. Color register set cycle is just as same as the usual write cycle except that DSF is set high at the falling edge of RAS, and read, early write and delayed write cycle can be executed. In this cycle, the HM534253B refreshes the row address fetched at the falling edge of RAS. Flash Write Cycle (CAS high, DT/OE high, WE low, and DSF high at the falling edge of RAS) In a flash write cycle, a row of data (512-word x 4-bit) is cleared to 0 or 1 at each I/O according to the data of color register mentioned before. It is also necessary to mask I/O in this cycle. When CAS and DT/OE is set high, WE is low, and DSF is high at the falling edge of RAS, this cycle starts. Then, the row address to clear is given to row address and mask data is given to I/O. Mask data is as same as that of a RAM write cycle. High I/O is cleared, low I/O is not cleared and the internal data is retained. Cycle time is the same as those of RAM read/write cycles, so all bits can be cleared in 1/512 of the usual cycle time. (See figure 1.) 8 HM534253B Series Color Register Set Cycle Flash Write Cycle Flash Write Cycle RAS CAS Address Row Xi Xj WE DT/OE DSF I/O Color Data Set color register *1 *1 Execute flash write into each I/O on row address Xi using color resister. Execute flash write into each I/O on row address Xj using color resister. Note: 1. I/O Mask Data Low: Mask High: Non Mask Figure 1 Use of Flash Write Block Write Cycle (CAS high, DT/OE high and DSF low at the falling edge of RAS, DSF high at the falling edge of CAS) In a block write cycle, 4 columns of data (4-word x 4-bit) is cleared to 0 or 1 at each I/O according to the data of color register. Column addresses A0 and A1 are disregarded. The data on I/Os and addresses can be masked. I/O level at the falling edge of CAS determines the address to be cleared. (See figure 2.) In a page mode cycle, mixed cycle of normal Read/Write and block write can be allowed by controlling DSF. * Normal Mode Block Write Cycle (WE high at the falling edge of RAS) The data on 4 I/Os are all cleared when WE is high at the falling edge of RAS. * Mask Block Write Mode (WE low at the falling edge of RAS) When WE is low at the falling edge of RAS, the HM534253B starts mask block write mode to clear the data on an optional I/O. The mask data is the same as that of a RAM write cycle. High I/O is cleared, low I/O is not cleared and the internal data is retained. The mask data is available in the RAS cycle. In page mode block write cycle, the mask data is retained during the page access. 9 HM534253B Series Color Register Set Cycle Block Write Cycle Block Write Cycle RAS CAS Address Row Row Column A2-A8 *1 WE Row Column A2-A8 *1 DT/OE DSF Color Data I/O *1 Address Mask *1 Address Mask *1 WE Low High I/O I/O Mask Data Don't care Mode Mask Non mask I/O Mask Data Low: Mask High: Non Mask Address Mask Data I/O0 I/O1 I/O2 I/O3 Column0 (A0 = 0, A1 = 0) Mask Data Column1 (A0 = 1, A1 = 0) Mask Data Column2 (A0 = 0, A1 = 1) Mask Data Column3 (A0 = 1, A1 = 1) Mask Data Low: Mask High: Non Mask Figure 2 Use of Block Write Transfer Operation The HM534253B provides the read transfer cycle, split read transfer cycle,pseudo transfer cycle, write transfer cycle, and split write transfer cycle as data transfer cycles. These transfer cycles are set by driving CAS high and DT/OE low at the falling edge of RAS. They have following functions: (1) Transfer data between row address and SAM data register (except for pseudo transfer cycle) Read transfer cycle and split read transfer cycle: RAM to SAM Write transfer cycle and split write transfer cycle: SAM to RAM (2) Determine SI/O state (except for split read transfer cycle and split write transfer cycle) Read transfer cycle: SI/O output Pseudo transfer cycle and write transfer cycle: SI/O input (3) Determine first SAM address to access after transferring at column address (SAM start address). 10 HM534253B Series SAM start address must be determined by read transfer cycle or pseudo transfer cycle (split transfer cycle isn't available) before SAM access, after power on, and determined for each transfer cycle. Read Transfer Cycle (CAS high, DT/OE low, WE high and DSF low at the falling edge of RAS) This cycle becomes read transfer cycle by driving DT/OE low, WE high and DSF low at the falling edge of RAS. The row address data (512 x 4 bits) determined by this cycle is transferred to SAM data register synchronously at the rising edge of DT/OE. After the rising edge of DT/OE, the new address data outputs from SAM start address determined by column address. In read transfer cycle, DT/OE must be risen to transfer data from RAM to SAM. This cycle can access SAM even during transfer (real time read transfer). In this case, the timing tSDD (min) specified between the last SAM access before transfer and DT/OE rising edge and t SDH (min) specified between the first SAM access and DT/OE rising edge must be satisfied. (See figure 3.) When read transfer cycle is executed, SI/O becomes output state by first SAM access. Input must be set high impedance before t SZS (min) of the first SAM access to avoid data contention. RAS CAS Address DT/OE Xi Yj L DSF t SDD t SDH SC Yj SI/O SAM Data before Transfer Yj + 1 SAM Data after Transfer Figure 3 Real Time Read Transfer Pseudo Transfer Cycle (CAS high, DT/OE low, WE low, SE high and DSF low at the falling edge of RAS) Pseudo transfer cycle switches SI/O to input state and set SAM start address without data transfer to RAM. This cycle starts when CAS is high, DT/OE low, WE low, SE high and DSF low at the falling edge of RAS. Data should be input to SI/O later than t SID (min) after RAS becomes low to avoid data contention. SAM access becomes enabled after t SRD (min) after RAS becomes high. In this cycle, SAM access is inhibited during RAS low, therefore, SC must not be risen. 11 HM534253B Series Write Transfer Cycle (CAS high, DT/OE low, WE low, SE low, and DSF low at the falling edge of RAS) Write transfer cycle can transfer a row of data input by serial write cycle to RAM. The row address of data transferred into RAM is determined by the address at the falling edge of RAS. The column address is specified as the first address for serial write after terminating this cycle. Also in this cycle, SAM access becomes enabled after t SRD (min) after RAS becomes high. SAM access is inhibited during RAS low. In this period, SC must not be risen. Data transferred to SAM by read transfer cycle or split read transfer cycle can be written to other addresses of RAM by write transfer cycle. However, the address to write data must be the same MSB of row address (AX8) as that of the read transfer cycle. Figure 4 shows the example of row bit data transfer. In case AX8 is 0, data cannot be transferred RAM address within the range of 100000000 to 111111111. Same as the case of AX8 = 1. (Row address) A8 ........ A0 000000000 SAM ........ SAM (Row address) A8 ........A0 000000000 Possible RAM 011111111 100000000 RAM 011111111 100000000 Impossible RAM RAM 111111111 111111111 SAM (Read transfer cycle) SAM (Write transfer cycle) Figure 4 Example of Row Bit Data Transfer Split Read Transfer Cycle (CAS high, DT/OE low, WE high and DSF high at the falling edge of RAS) To execute a continuous serial read by real time read transfer, the HM534253B must satisfy SC and DT/OE timings and requires an external circuit to detect SAM last address. Split read transfer cycle makes it possible to execute a continuous serial read without the above timing limitation. Figure 5 shows the block diagram for a split transfer. SAMdata register (DR) consists of 2 split buffers, whose organizations are 256-word x 4-bit each. Let us suppose that data is read from upper data register DR1 (The row address AX8 is 0 and SAM address A8 is 1.). When split read transfer is executed setting row address AX8 0 and SAM start addresses A0 to A7, 256-word x 4-bit data are transferred from RAM to the lower data register DR0 (SAM address A8 is 0) automatically. After data are read from data register DR1, data start to be read from SAM start addresses of data register DR0. If the next split read transfer isn't executed while data are read from data register DR0, data start to be read from SAM start address 0 of DR1 after data are read from data register DR0. If split read transfer is executed setting row address AX8 1 and SAM start addresses A0 to A7 while data are read from data register DR1, 256-word x 4-bit data are transferred to data register DR2. After data are read from data register DR1, data start to be read from SAM start addresses of data register DR2. If the next split read transfer isn't executed while data is read from data register DR2, data start to be read from SAM start address 0 of data register DR3 after data are read from data register DR2. In this time, SAM data is the one transferred to data register DR3 finally while row address AX8 is 1. In split read data transfer, the SAM start address A8 is automatically set in the data register which isn't used. 12 HM534253B Series The data on SAM address A8, which will be accessed next, outputs to QSF. QSF is switched from low to high by accessing SAM last address 255 and from high to low by accessing address 511. Split read transfer cycle is set when CAS is high, DT/OE is low, WE is high and DSF is high at the falling edge of RAS. The cycle can be executed asyncronously with SC. However, tSTS (min) timing specified between SC rising and RAS falling must be satisfied. SAM last address must be accessed, satisfying tRST (min), tCST (min), and tAST (min) timings specified between RAS or CAS falling and column address. (See figure 6.) DR3 Memory Array AX8 = 1 DR2 SAM I/O Bus SAM Column Decoder DR0 AX8 = 0 SAM I/O Bus Memory Array DR1 In split read transfer, SI/O isn't switched to output state. Therefore, read transfer must be executed to switch SI/O to output state when the previous transfer cycle is pseudo transfer or write transfer cycle. SAM I/O Buffer SI/O Figure 5 Block Diagram for Split Transfer 13 HM534253B Series RAS tSTS (min) tRST (min) CAS t CST (min) Address Xi Yj t AST (min) DT/OE DSF SC 511 (255) n (n + 255) 255 (511) 255 + Yj (Yj) Figure 6 Limitation in Split Transfer Split Write Transfer Cycle (CAS high, DT/OE low, WE low and DSF high at the falling edge of RAS) A continuous serial write cannot be executed because accessing SAM is inhibited during RAS low in write transfer. Split write transfer cycle makes it possible. In this cycle, tSTS (min), tRST (min), tCST (min) and tAST (min) timings must be satisfied like split read transfer cycle. And it is impossible to switch SI/O to input state in this cycle. If SI/O is in output state, pseudo transfer cycle should be executed to switch SI/O into input state. Data transferred to SAM by read transfer cycle or split read transfer cycle can be written to other addresses of RAM by split write transfer cycle. However, pseudo transfer cycle must be executed before split write transfer cycle. And the MSB of row address (AX8) to write data must be the same as that of the read transfer cycle or the split read transfer cycle. SAM Port Operation Serial Read Cycle SAM port is in read mode when the previous data transfer cycle is read transfer cycle. Access is synchronized with SC rising, and SAM data is output from SI/O. When SE is set high, SI/O becomes high impedance, and the internal pointer is incremented by the SC rising. After indicating the last address (address 511), the internal pointer indicates address 0 at the next access. 14 HM534253B Series Serial Write Cycle If previous data transfer cycle is pseudo transfer cycle or write transfer cycle, SAM port goes into write mode. In this cycle, SI/O data is fetched into data register at the SC rising edge like in the serial read cycle. If SE is high, SI/O data isn't fetched into data register. Internal pointer is incremented by the SC rising, so SE high can be used as mask data for SAM. After indicating the last address (address 511), the internal pointer indicates address 0 at the next access. Refresh RAM Refresh RAM, which is composed of dynamic circuits, requires refresh to retain data. Refresh is executed by accessing all 512 row addresses within 8 ms. There are three refresh cycles: (1) RAS-only refresh cycle, (2) CAS-before-RAS (CBR) refresh cycle, and (3) Hidden refresh cycle. Besides them, the cycles which activate RAS such as read/write cycles or transfer cycles can refresh the row address. Therefore, no refresh cycle is required when all row addresses are accessed within 8 ms. (1) RAS-Only Refresh Cycle: RAS-only refresh cycle is executed by activating only RAS cycle with CAS fixed to high after inputting the row address (= refresh address) from external circuits. To distinguish this cycle from data transfer cycle, DT/OE must be high at the falling edge of RAS. (2) CBR Refresh Cycle: CBR refresh cycle is set by activating CAS before RAS. In this cycle, refresh address need not to be input through external circuits because it is input through an internal refresh counter. In this cycle, output is in high impedance and power dissipation is lowered because CAS circuits don't operate. (3) Hidden Refresh Cycle: Hidden refresh cycle executes CBR refresh with the data output by reactivating RAS when DT/OE and CAS keep low in normal RAM read cycles. SAM Refresh SAM parts (data register, shift resister and selector), organized as fully static circuitry, require no refresh. Absolute Maximum Ratings Parameter Symbol Value Unit Note Voltage on any pin relative to V SS VT -1.0 to +7.0 V 1 Supply voltage relative to VSS VCC -0.5 to +7.0 V 1 Short circuit output current Iout 50 mA Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 C Storage temperature Tstg -55 to +125 C Note: 1. Relative to VSS . 15 HM534253B Series Recommended DC Operating Conditions (Ta = 0 to +70C) Parameter Symbol Min Typ Max Unit Notes Supply voltage VCC 4.5 5.0 5.5 V 1 Input high voltage VIH 2.4 -- 6.5 V 1 -- 0.8 V 1 Input low voltage VIL -0.5 *2 Notes: 1. All voltage referred to VSS 2 -3.0 V for pulse width 10 ns. DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) HM534253B -6 -7 -8 -10 Parameter Symbol Min Max Min Max Min Max Min Max Unit Test Conditions Operating current I CC1 -- 75 I CC7 -- 125 -- I CC2 -- 7 I CC8 -- I CC3 Standby current RAS-only refresh current Page mode current -- 55 mA 120 -- 100 -- 95 mA -- 7 -- 7 -- 7 mA 50 -- 50 -- 40 -- 40 mA -- 75 -- 70 -- 60 -- 55 mA I CC9 -- 125 -- 120 -- 100 -- 95 mA I CC4 -- 80 80 70 65 mA I CC10 -- 130 -- 130 -- 110 -- 105 mA -- 50 -- 45 -- 40 -- 35 mA -- 100 -- 95 -- 80 -- 75 mA CAS-before- I CC5 RAS refresh current I CC11 16 -- -- 70 -- -- 60 -- RAS, CAS cycling SC = VIL, t RC = min SE = VIH SE = VIL, SC cycling t SCC = min RAS, CAS = VIH SC = VIL, SE = VIH SE = VIL, SC cycling t SCC = min RAS cycling CAS = VIH t RC = min SC = VIL, SE = VIH SE = VIL, SC cycling t SCC = min CAS cycling RAS = VIL t PC = min SC = VIL, SE = VIH SE = VIL, SC cycling t SCC = min RAS cycling t RC = min SC = VIL, SE = VIH SE = VIL, SC cycling t SCC = min HM534253B Series DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) (cont) HM534253B -6 -7 -8 -10 Parameter Symbol Min Max Min Max Min Max Min Max Unit Test Conditions Data transfer current I CC6 -- 80 I CC12 -- 130 -- Input leakage current I LI -10 10 -10 10 -10 10 -10 10 A Output leakage current I LO -10 10 -10 10 -10 10 -10 10 A Output high voltage VOH 2.4 -- 2.4 -- 2.4 -- 2.4 -- V I OH = -2 mA Output low voltage VOL -- 0.4 -- 0.4 -- 0.4 -- 0.4 V I OL = 4.2 mA -- 75 -- 125 -- 65 -- 105 -- 60 mA RAS, CAS cycling SC = VIL, t RC = min SE = VIH SE = VIL, SC cycling t SCC = min 100 mA Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once while RAS is low and CAS is high. Capacitance (Ta = 25C, VCC = 5 V, f = 1 MHz, Bias: Clock, I/O = VCC, address =VSS) Parameter Symbol Typ Max Unit Note Input capacitance (Address) CI1 -- 5 pF 1 Input capacitance (Clocks) CI2 -- 5 pF 1 Output capacitance (I/O, SI/O, QSF) CI/O -- 7 pF 1 Note: 1. This parameter is sampled and not 100% tested. AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V)*1, *16 Test Conditions * * * * * Input rise and fall time: 5 ns Input pulse levels: VSS to 3.0 V Input timing reference levels: 0.8 V, 2.4 V Output timing reference levels: 0.8 V, 2.0 V Output load: See figures 17 HM534253B Series Test Conditions (cont) I OH = - 2 mA +5V I OL = 4.2 mA I OL = 4.2 mA I/O +5V I OH = - 2 mA SI / O *1 100 pF Output Load (A) *1 50 pF Output Load (B) Note: 1. Including scope & jigs Common Parameter HM534253B -6 -7 -8 -10 Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes Random read or write cycle time t RC 125 -- 135 -- 150 -- 180 -- ns RAS precharge time t RP 55 -- 55 -- 60 -- 70 ns RAS pulse width t RAS 60 10000 70 10000 80 10000 100 10000 ns CAS pulse width t CAS 20 -- 20 -- 20 -- 25 -- ns Row address setup time t ASR 0 -- 0 -- 0 -- 0 -- ns Row address hold time t RAH 10 -- 10 -- 10 -- 10 -- ns Column address setup time t ASC 0 -- 0 -- 0 -- 0 -- ns Column address hold time t CAH 15 -- 15 -- 15 -- 15 -- ns RAS to CAS delay time t RCD 20 40 20 50 20 60 20 75 ns RAS hold time referred to CAS t RSH 20 -- 20 -- 20 -- 25 -- ns CAS hold time referred to RAS t CSH 60 -- 70 -- 80 -- 100 -- ns CAS to RAS precharge time t CRP 10 -- 10 -- 10 -- 10 -- ns Transition time (rise to fall) tT 3 50 3 50 3 50 3 50 ns Refresh period t REF -- 8 -- 8 -- 8 -- 8 ms DT to RAS setup time t DTS 0 -- 0 -- 0 -- 0 -- ns DT to RAS hold time t DTH 10 -- 10 -- 10 -- 10 -- ns DSF to RAS setup time t FSR 0 -- 0 -- 0 -- 0 -- ns DSF to RAS hold time t RFH 10 -- 10 -- 10 -- 10 -- ns 18 -- 2 3 HM534253B Series Common Parameter (cont) HM534253B -6 -7 -8 -10 Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes DSF to CAS setup time t FSC 0 -- 0 -- 0 -- 0 -- ns DSF to CAS hold time t CFH 15 -- 15 -- 15 -- 15 -- ns Data-in to CAS delay time t DZC 0 -- 0 -- 0 -- 0 -- ns 4 Data-in to OE delay time t DZO 0 -- 0 -- 0 -- 0 -- ns 4 Output buffer turn-off delay referred to CAS t OFF1 -- 20 -- 20 -- 20 -- 20 ns 5 Output buffer turn-off delay referred to OE t OFF2 -- 20 -- 20 -- 20 -- 20 ns 5 Read Cycle (RAM), Page Mode Read Cycle HM534253B -6 -7 -8 -10 Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes Access time from RAS t RAC -- 60 -- 70 -- 80 -- 100 ns 6, 7 Access time from CAS t CAC -- 20 -- 20 -- 20 -- 25 ns 7, 8 Access time from OE t OAC -- 20 -- 20 -- 20 -- 25 ns 7 Address access time t AA -- 35 -- 35 -- 40 -- 45 ns 7, 9 Read command setup time t RCS 0 -- 0 -- 0 -- 0 -- ns Read command hold time t RCH 0 -- 0 -- 0 -- 0 -- ns 10 Read command hold time referred to RAS t RRH 10 -- 10 -- 10 -- 10 -- ns 10 RAS to column address delay time t RAD 15 25 15 35 15 40 15 55 ns 2 Column address to RAS lead t RAL time 35 -- 35 -- 40 -- 45 -- ns Column address to CAS lead t CAL time 35 -- 35 -- 40 -- 45 -- ns Page mode cycle time t PC 45 -- 45 -- 50 -- 55 -- ns CAS precharge time t CP 10 -- 10 -- 10 -- 10 -- ns Access time from CAS precharge t ACP -- 40 -- 40 -- 45 -- 50 ns 60 100000 70 Page mode RAS pulse width t RASP 100000 80 100000 100 100000 ns 19 HM534253B Series Write Cycle (RAM), Page Mode Write Cycle, Color Register Set Cycle HM534253B -6 -7 -8 -10 Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes Write command setup time t WCS 0 -- 0 -- 0 -- 0 -- ns Write command hold time t WCH 15 -- 15 -- 15 -- 15 -- ns Write command pulse width t WP 15 -- 15 -- 15 -- 15 -- ns Write command to RAS lead t RWL time 20 -- 20 -- 20 -- 20 -- ns Write command to CAS lead t CWL time 20 -- 20 -- 20 -- 20 -- ns Data-in setup time t DS 0 -- 0 -- 0 -- 0 -- ns 12 Data-in hold time t DH 15 -- 15 -- 15 -- 15 -- ns 12 WE to RAS setup time t WS 0 -- 0 -- 0 -- 0 -- ns WE to RAS hold time t WH 10 -- 10 -- 10 -- 10 -- ns Mask data to RAS setup time t MS 0 -- 0 -- 0 -- 0 -- ns Mask data to RAS hold time t MH 10 -- 10 -- 10 -- 10 -- ns OE hold time referred to WE t OEH 20 -- 20 -- 20 -- 20 -- ns Page mode cycle time t PC 45 -- 45 -- 50 -- 55 -- ns CAS precharge time t CP 10 -- 10 -- 10 -- 10 -- ns CAS to data-in delay time t CDD 20 -- 20 -- 20 -- 20 -- ns 60 100000 70 10000 100 100000 ns Page mode RAS pulse width t RASP 20 100000 80 11 13 HM534253B Series Read-Modify-Write Cycle HM534253B -6 Parameter Symbol Min Max -7 -8 -10 Min Max Min Max Min Max Unit Notes Read-modify-write cycle time t RWC 175 -- 185 -- 200 -- 230 -- ns RAS pulse width (readmodify-write cycle) t RWS 110 10000 120 10000 130 10000 150 10000 ns CAS to WE delay time t CWD 45 -- 45 -- 45 -- 50 -- ns 14 Column address to WE delay t AWD time 60 -- 60 -- 65 -- 70 -- ns 14 OE to data-in delay time t ODD 20 -- 20 -- 20 -- 20 -- ns 12 Access time from RAS t RAC -- 60 -- 70 -- 80 -- 100 ns 6, 7 Access time from CAS t CAC -- 20 -- 20 -- 20 -- 25 ns 7, 8 Access time from OE t OAC -- 20 -- 20 -- 20 -- 25 ns 7 Address access time t AA -- 35 -- 35 -- 40 -- 45 ns 7, 9 RAS to column address delay time t RAD 15 25 15 35 15 40 15 55 ns Read command setup time t RCS 0 -- 0 -- 0 -- 0 -- ns Write command to RAS lead t RWL time 20 -- 20 -- 20 -- 20 -- ns Write command to CAS lead t CWL time 20 -- 20 -- 20 -- 20 -- ns Write command pulse width t WP 15 -- 15 -- 15 -- 15 -- ns Data-in setup time t DS 0 -- 0 -- 0 -- 0 -- ns 12 Data-in hold time t DH 15 -- 15 -- 15 -- 15 -- ns 12 20 -- 20 -- 20 -- 20 -- ns OE hold time referred to WE t OEH Refresh Cycle HM534253B -6 -7 -8 -10 Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes CAS setup time (CASbefore-RAS refresh) t CSR 10 -- 10 -- 10 -- 10 -- ns CAS hold time (CAS-before- t CHR RAS refresh) 10 -- 10 -- 10 -- 10 -- ns RAS precharge to CAS hold t RPC time 10 -- 10 -- 10 -- 10 -- ns 21 HM534253B Series Flash Write Cycle, Block Write Cycle HM534253B -6 -7 -8 -10 Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes CAS to data-in delay time t CDD 20 -- 20 -- 20 -- 20 -- ns 13 OE to data-in delay time t ODD 20 -- 20 -- 20 -- 20 -- ns 13 Read Transfer Cycle HM534253B -6 Parameter Symbol Min Max -7 -8 -10 Min Max Min Max Min Max Unit Notes DT hold time referred to RAS t RDH 50 10000 60 10000 65 10000 80 10000 ns DT hold time referred to CAS t CDH 20 -- 20 -- 20 -- 25 -- ns DT hold time referred to column address t ADH 25 -- 25 -- 30 -- 30 -- ns DT precharge time t DTP 20 -- 20 -- 20 -- 30 -- ns DT to RAS delay time t DRD 65 -- 65 -- 70 -- 80 -- ns SC to RAS setup time t SRS 25 -- 25 -- 30 -- 30 -- ns 1st SC to RAS hold time t SRH 60 -- 70 -- 80 -- 100 -- ns 1st SC to CAS hold time t SCH 25 -- 25 -- 25 -- 25 -- ns 1st SC to column address hold time t SAH 40 -- 40 -- 45 -- 50 -- ns Last SC to DT delay time t SDD 5 -- 5 -- 5 -- 5 -- ns Last SC to DT delay time t SDD2 25 -- 25 -- 25 -- 25 -- ns 1st SC to DT hold time t SDH 10 -- 10 -- 15 -- 15 -- ns RAS to QSF delay time t RQD -- 65 -- 70 -- 75 -- 85 ns 15 CAS to QSF delay time t CQD -- 35 -- 35 -- 40 -- 40 ns 15 DT to QSF delay time t DQD -- 35 -- 35 -- 35 -- 35 ns 15 QSF hold time referred to RAS t RQH 20 -- 20 -- 20 -- 25 -- ns QSF hold time referred to CAS t CQH 5 -- 5 -- 5 -- 5 -- ns QSF hold time referred to DT t DQH 5 -- 5 -- 5 -- 5 -- ns Serial data-in to 1st SC delay t SZS time 0 -- 0 -- 0 -- 0 -- ns Serial clock cycle time 25 -- 25 -- 30 -- 30 -- ns 22 t SCC 19 HM534253B Series Read Transfer Cycle (cont) HM534253B -6 -7 -8 -10 Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes SC pulse width t SC 5 -- 5 -- 10 -- 10 -- ns SC precharge time t SCP 10 -- 10 -- 10 -- 10 -- ns SC access time t SCA -- 20 -- 22 -- 25 -- 25 ns Serial data-out hold time t SOH 5 -- 5 -- 5 -- 5 -- ns Serial data-in setup time t SIS 0 -- 0 -- 0 -- 0 -- ns Serial data-in hold time t SIH 15 -- 15 -- 15 -- 15 -- ns RAS to column address delay time t RAD 15 25 15 35 15 40 15 55 ns Column address to RAS lead t RAL time 35 -- 35 -- 40 -- 45 -- ns RAS precharge to DT high hold time 10 -- 10 -- 10 -- 10 -- ns t DTHH 15 18 23 HM534253B Series Pseudo Transfer Cycle, Write Transfer Cycle HM534253B -6 -7 -8 -10 Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes SE setup time referred to RAS t ES 0 -- 0 -- 0 -- 0 -- ns SE hold time referred to RAS t EH 10 -- 10 -- 10 -- 10 -- ns SC setup time referred to RAS t SRS 25 -- 25 -- 30 -- 30 -- ns RAS to SC delay time t SRD 20 -- 20 -- 25 -- 25 -- ns Serial output buffer turn-off time referred to RAS t SRZ 10 40 10 40 10 45 10 50 ns RAS to serial data-in delay time t SID 40 -- 40 -- 45 -- 50 -- ns RAS to QSF delay time t RQD -- 65 -- 70 -- 75 -- 85 ns 15 CAS to QSF delay time t CQD -- 35 -- 35 -- 40 -- 40 ns 15 QSF hold time referred to RAS t RQH 20 -- 20 -- 20 -- 25 -- ns QSF hold time referred to CAS t CQH 5 -- 5 -- 5 -- 5 -- ns Serial clock cycle time t SCC 25 -- 25 -- 30 -- 30 -- ns SC pulse width t SC 5 -- 5 -- 10 -- 10 -- ns SC precharge time t SCP 10 -- 10 -- 10 -- 10 -- ns SC access time t SCA -- 20 -- 22 -- 25 -- 25 ns 15 SE access time t SEA -- 20 -- 22 -- 25 -- 25 ns 15 Serial data-out hold time t SOH 5 -- 5 -- 5 -- 5 -- ns Serial write enable setup time t SWS 5 -- 5 -- 5 -- 5 -- ns Serial data-in setup time t SIS 0 -- 0 -- 0 -- 0 -- ns Serial data-in hold time t SIH 15 -- 15 -- 15 -- 15 -- ns 24 HM534253B Series Split Read Transfer Cycle, Split Write Transfer Cycle HM534253B -6 -7 -8 -10 Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes Split transfer setup time t STS 20 -- 20 -- 20 -- 25 -- ns Split transfer hold time referred to RAS t RST 60 -- 70 -- 80 -- 100 -- ns Split transfer hold time referred to CAS t CST 20 -- 20 -- 20 -- 25 -- ns Split transfer hold time referred to column address t AST 35 -- 35 -- 40 -- 45 -- ns SC to QSF delay time t SQD -- 30 -- 30 -- 30 -- 30 ns QSF hold time referred to SC t SQH 5 -- 5 -- 5 -- 5 -- ns Serial clock cycle time t SCC 25 -- 25 -- 30 -- 30 -- ns SC pulse width t SC 5 -- 5 -- 10 -- 10 -- ns SC precharge time t SCP 10 -- 10 -- 10 -- 10 -- ns SC access time t SCA -- 20 -- 22 -- 25 -- 25 ns Serial data-out hold time t SOH 5 -- 5 -- 5 -- 5 -- ns Serial data-in setup time t SIS 0 -- 0 -- 0 -- 0 -- ns Serial data-in hold time t SIH 15 -- 15 -- 15 -- 15 -- ns RAS to column address delay time t RAD 15 25 15 35 15 40 15 55 ns Column address to RAS lead t RAL time 35 -- 35 -- 40 -- 45 -- ns 15 15 25 HM534253B Series Serial Read Cycle, Serial Write Cycle HM534253B -6 -7 -8 -10 Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes Serial clock cycle time t SCC 25 -- 25 -- 30 -- 30 -- ns SC pulse width t SC 5 -- 5 -- 10 -- 10 -- ns SC precharge width t SCP 10 -- 10 -- 10 -- 10 -- ns Access time from SC t SCA -- 20 -- 22 -- 25 -- 25 ns 15 Access time from SE t SEA -- 20 -- 22 -- 25 -- 25 ns 15 Serial data-out hold time t SOH 5 -- 5 -- 5 -- 5 -- ns Serial output buffer turn-off time referred to SE t SEZ -- 20 -- 20 -- 20 -- 20 ns Serial data-in setup time t SIS 0 -- 0 -- 0 -- 0 -- ns Serial data-in hold time t SIH 15 -- 15 -- 15 -- 15 -- ns Serial write enable setup time t SWS 5 -- 5 -- 5 -- 5 -- ns Serial write enable hold time t SWH 15 -- 15 -- 15 -- 15 -- ns Serial write disable setup time 5 -- 5 -- 5 -- 5 -- ns 15 -- 15 -- 15 -- 15 -- ns t SWIS Serial write disable hold time t SWIH 5 Notes: 1. AC measurements assume t T = 5 ns. 2. When t RCD > tRCD (max) and tRAD > tRAD (max), access time is specified by tCAC or tAA. 3. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition time tT is measured between VIH and VIL. 4. Data input must be floating before output buffer is turned on. In read cycle, read-modify-write cycle and delayed write cycle, either tDZC (min) or tDZO (min) must be satisfied. 5. t OFF1 (max), tOFF2 (max), and tSEZ (max) are defined as the time at which the output achieves the open circuit condition (V OH - 100 mV, VOL + 100 mV). 6. Assume that tRCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 7. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 8. When t RCD tRCD (max) and tRAD tRAD (max), access time is specified by tCAC . 9. When t RCD tRCD (max) and tRAD tRAD (max), access time is specified by tAA . 10. If either tRCH or tRRH is satisfied, operation is guaranteed. 11. When t WCS tWCS (min), the cycle is an early write cycle, and I/O pins remain in an open circuit (high impedance) condition. 12. These parameters are specified by the later falling edge of CAS or WE. 13. Either t CDD (min) or tODD (min) must be satisfied because output buffer must be turned off by CAS or OE prior to applying data to the device when output buffer is on. 14. When t AWD tAWD (min) and tCWD tCWD (min) in read-modify-write cycle, the data of the selected address outputs to an I/O pin and input data is written into the selected address. t ODD (min) must be satisfied because output buffer must be turned off by OE prior to applying data to the device. 15. Measured with a load circuit equivalent to 2 TTL loads and 50 pF. 26 HM534253B Series 16. After power-up, pause for 100 s or more and execute at least 8 initialization cycle (normal memory cycle or refresh cycle), then start operation. 17. When the serial write cycle is used, at least one SC pulse is required before proper SAM operation after V CC stabilized. 18. t DTHH (min) must be satisfied only if DT/OE rises up before RAS rises in a read transfer cycle. 19. After read transfer cycle, if split read transfer cycle is executed without SC access and SC address is 254 or 510, t SDD2 (min) must be satisfied 25 ns. Except for those cases, tSDD (min) is effective and satisfied 5 ns. 20. XXX: H or L (H: VIH (min) V IN V IH (max), L: VIL (min) V IN V IL (max)) ///////: Invalid Dout Timing Waveforms*20 Read Cycle t RC t RAS t RP RAS t CRP t CSH t RSH t CAS t RCD CAS t RAD t ASR Address t RAL t RAH t ASC Row Column t RCS WE t CAL t CAH t RRH t RCH t CAC t AA I/O (Output) t CDD t OFF1 t RAC Valid Dout t OAC t DZC I/O (Input) t OFF2 t DZO t DTS t DTH t FSR t RFH DT/OE t FSC t CFH DSF 27 HM534253B Series Early Write Cycle t RC t RAS t RP RAS t CRP t CSH t RCD CAS t ASR Address t RAH Row t WS t WH t RSH t CAS t ASC t CAH Column t WCS t WCH *1 WE High-Z I/O (Output) t MH t MS I/O (Input) Mask Data t DTS t DTH t DS t DH Valid Din DT/OE t FSR t RFH t FSC t CFH DSF Note: 1. This cycle becomes a normal mode write cycle when WE is high and a mask write cycle when WE is low. Delayed Write Cycle t RC t RAS t RP RAS CAS t CAS t ASR Address t RAH Row t WS I/O (Input) DT/OE t ASC t CAH Columun t RWL t WH t MS t MH t RFH t DS t DZC Mask Data t DTH t DTS t FSR t CWL t WP *1 WE I/O (Output) t CRP t CSH t RSH t RCD t OFF2 t ODD t FSC t DH Valid Din t OEH t CFH DSF Note: 1. This cycle becomes a normal mode write cycle when WE is high and a mask write cycle when WE is low. 28 HM534253B Series Read-Modify-Write Cycle t RWC t RP t RWS RAS t CRP t RCD CAS t RAD t ASR Address t RAH t WS t CAH Columun t WH t AWD t CWD t RCS t RWL t CWL t WP t CAC t AA *1 WE I/O (Output) t ASC Row t RAC Valid Dout t MS I/O (Input) t MH Mask Data t DTS t DTH t DS t OAC t DZC Valid Din t OFF2 t ODD t DZO t DH t OEH DT/OE t RFH t FSR t FSC t CFH DSF Note: 1. This cycle becomes a normal mode write cycle when WE is high and a mask write cycle when WE is low. Page Mode Read Cycle t RC t RASP RAS t CSH t RCD t CAS CAS t RAD t ASR Address t RAH t ASC Row WE t PC t CP t CAL t CAH Columun t RCS t ASC I/O (Input) t DTS t DZO t DTH t FSR t RFH t CDD t OAC t OFF2 t CAL t CAH t ASC Columun t AA t ACP t CAC t RRH t RCH t RCS t RCH Valid Dout t DZC t OFF1 t AA t ACP t CAC Valid Dout t DZC t CRP t RAL t CAL t CAH Columun t RCH t RSH t CAS t CP t CAS t RCS t RAC t OFF1 t AA t CAC I/O (Output) t RP t OFF1 Valid Dout t CDD t OAC t OFF2 t DZC t OAC t CDD DT/OE DSF t FSC t CFH t FSC t CFH t FSC t CFH 29 HM534253B Series Page Mode Write Cycle (Early Write) t RC t RP t RASP RAS t PC t CSH t RCD CAS Address t ASR t RAH t ASC t RSH t CAS t CP t CAS t CAH t ASC Row Column t WS t WH t WCS t WCH WE I/O (Output) t CP t CAS t CAH t ASC t CRP t CAH Column Column t WCS t WCH t WCS t WCH *1 High-Z t MS I/O (Input) t MH t DS Mask Data t DH t DH t DS Valid Din t DTS t DH t DS Valid Din Valid Din t DTH DT/OE t FSR t RFH t FSC t CFH t FSC t CFH t FSC t CFH DSF Note: 1. This cycle becomes a normal mode write cycle when WE is high and a mask write cycle when WE is low. Page Mode Write Cycle (Delayed Write) t RC t RASP t RP RAS t CSH t PC t RCD CAS t ASR t RAH t ASC Address Row t WS t CAH Column t ASC t CAH Column t ASC t CRP t CAH Column t RWL t CWL t CWL t WH t RSH t CAS t CP t CAS t WP t CWL t WP t WP *1 WE I/O (Output) t CP t CAS t MH t MS I/O (Input) Mask Data t DS t DH Valid Din t DS t DH t DS Valid Din Valid Din t OEH t DTS DT/OE t FSR t DH t RFH t FSC t CFH t FSC t CFH t FSC t CFH DSF Note: 1. This cycle becomes a normal mode write cycle when WE is high and a mask write cycle when WE is low. 30 HM534253B Series RAS-Only Refresh Cycle t RC t RP t RAS RAS t RPC t CRP CAS t ASR t RAH Row Address t OFF1 I/O (Output) t CDD I/O (Input) t OFF2 t ODD t DTS t DTH t FSR t RFH DT/OE DSF CAS-Before-RAS Refresh Cycle t RC t RP RAS t RPC t CP t RP t RAS t RPC t CSR t CHR t CSR Inhibit Falling Transition CAS Address WE I/O (Output) t OFF1 High-Z DT/OE DSF 31 HM534253B Series Hidden Refresh Cycle t RC t RAS t RC t RAS t RP t RP RAS t RCD CAS t CRP t CHR t RAD t RAL t RAH t ASC t CAH t ASR Address t RSH Row Column t RCS t RRH t CAC WE t AA t RAC I/O (Output) t DZC I/O (Input) t OAC t OFF2 t DZO t DTH t DTS DT/OE t OFF1 Valid Dout t RFH t FSR t FSC t CFH DSF Color Register Set Cycle (Early Write) t RC t RP t RAS RAS t CSH t RCD CAS t ASR Address t CRP t RSH t CAS t RAH Row t WS t WH t WCS t WCH WE High-Z I/O (Output) t DS I/O (Input) Color Data t DTS t DTH t FSR t RFH DT/OE DSF 32 t DH HM534253B Series Color Register Set Cycle (Delayed Write) t RC t RP t RAS RAS t CSH t CRP t RSH t RCD t CAS CAS t ASR Address t RAH Row t RWL t CWL t WS t WP WE I/O (Output) High-Z t DS I/O (Input) t DH Color Data t DTS DT/OE t OEH t FSR t RFH DSF Color Register Read Cycle t RC t RP t RAS RAS t CSH CAS t ASR Address t CRP t RSH t CAS t RCD t RAH Row t WS t RCS t WH WE t RRH t CDD t OFF1 t CAC t RAC I/O (Output) Valid Out t DZC I/O (Input) t OAC t OFF2 t ODD t DZO t DTS DT/OE t RCH t FSR t DTH t RFH DSF 33 HM534253B Series Flash Write Cycle t RC t RAS t RP RAS t CRP CAS t RCD t ASR t RAH Row Address t WS t WH WE t OFF1 I/O (Output) t OFF2 t CDD High-Z t MS t ODD I/O (Input) t DTS DT/OE t MH Mask Data t DTH t FSR t RFH DSF Block Write Cycle t RC t RP t RAS RAS t CSH t CRP CAS t RCD Address t WS Row t WH WE I/O (Input) t ASC t CRP t CAH Column A2-A8 *1 t OFF1 I/O (Output) t RAH t ASR t RSH t OFF2 t CDD High-Z t ODD t DTS t MS t MH I/O Mask Data t DTH t DS t DH Address Mask Data DT/OE t FSR t RFH t FSC t CFH DSF Note: 1. This cycle becomes a normal block write cycle when WE is high and a mask block write cycle when WE is low. 34 HM534253B Series Page Mode Block Write Cycle t RC t RP t RASP RAS t CSH t PC t RCD t CAS t CP t RSH t CAS t CP t CAS t CRP CAS t ASR t RAH t WS t ASC t CAH t ASC Column A2-A8 t CAH Column A2-A8 t WH *1 WE I/O (Output) t CAH Column A2-A8 Row Address t ASC High-Z t MS I/O (Input) t MH t DTS t DS t DH Address Mask I/O Mask t DS t DH Address Mask t DS t DH Address Mask t DTH DT/OE t FSR t RFH t FSC t CFH t FSC t CFH t FSC t CFH DSF Note: 1. This cycle becomes a normal block write cycle when WE is high and a mask block write cycle when WE is low. 35 HM534253B Series Read Transfer Cycle (1) t RC t RP t RAS RAS t CRP t CSH t RCD t RSH t CAS CAS t RAD t RAH t ASR Address t RAL t ASC t CAH SAM Start Address Row t WS t WH WE t DTHH High-Z I/O (Output) t CDH t DTS t DRD t ADH t RDH t DTP DT/OE t FSR t RFH DSF t SCC t SCC t SC SI/O (Output) Valid Sout SDD2*3 Valid Sout t SC t SDH t SCA t SOH t SCA t SOH t SCA t SOH t SCA t SOH t SCC t SCC t SDD Valid Sout Valid Sout Previous Row SI/O (Input) t SCP t SOH Valid Sout New Row t DQD t DQH QSF *1 SAM Address MSB t RQD t RQH QSF *2 t CQD t CQH SAM Address MSB Notes: 1. This QSF timing is referred when SC is risen once or more between the previous transfer cycle and CAS falling edge of this cycle (QSF is switched by DT rising). 2. This QSF timing is referred when SC isn't risen between the previous transfer cycle and CAS falling edge of this cycle (QSF is switched by RAS or CAS falling). 3. After read transfer cycle, if split read transfer cycle is executed without SC access and SC address is 254 or 510, tSDD2 (min) must be satisfied 25 ns. Except for those cases, tSDD (min) is effective and satisfied 5 ns. 36 HM534253B Series Read Transfer Cycle (2) t RC t RAS t RP RAS t CSH t CRP t RCD t RSH t CAS CAS t ASR Address t RAD t RAH Row t WS t RAL t ASC t CAH Sam Start Address t WH WE t DTHH High-Z I/O (Output) t DTS t DTH t FSR t RFH t DRD t DTP DT/OE DSF t SRS t SC t SDH t SCP t SCC t SC t SCP Inhibit Rising Transition SC t SCA t SCA t SCH t SAH t SRH SI/O (Output) SI/O (Input) t SIS t SOH t SIH t SZS Valid Sout Valid Sin t DQD t DQH QSF SAM Address MSB t CQD t CQH t RQD t RQH 37 HM534253B Series Pseudo Transfer Cycle t RC t RAS t RP RAS t CSH t CRP t RSH t RCD t CAS CAS t ASC t RAH t ASR SAM Start Address Row Address t WS t CAH t WH WE High - Z I/O (Output) t DTS t DTH DT/OE t FSR t RFH t ES t SEZ t EH DSF t SWS SE t SRS t SRD t SCP t SC t SCA t SOH Valid Sout t SRZ Valid Sout t SIS t SID SI/O (Input) t CQD t RQD t RQH QSF 38 t SCP Inhibit Rising Transition SC SI/O (Output) t SCC t SC SAM Address MSB t CQH t SIH Valid Sin t SIS t SIH Valid Sin HM534253B Series Write Transfer Cycle t RC t RAS t RP RAS t CRP t CSH t RSH t RCD t CAS CAS t RAH t ASR Row Address t WS t ASC t CAH SAM Start Address t WH WE High-Z I/O (Output) t DTS t DTH DT/OE t FSR t RFH DSF t ES t EH t SWS SE t SRS t SRD t SWS t SC t SCP SC SI/O (Output) SI/O (Input) t SCC t SC t SCP Inhibit Rising Transition t SIS t SIH t SIS Valid Sin t SIH Valid Sin t SIS t SIH Valid Sin t CQD t RQD t CQH t RQH QSF SAM Address MSB 39 HM534253B Series Split Read Transfer Cycle t RC t RP t RAS RAS t CSH t RSH t RCD t CRP t CRP t CAS CAS t RAD t ASR Address t RAL t RAH t ASC SAM Start Address Yi Row t WS t CAH t WH WE t OFF1 High-Z I/O (Output) t DTS t DTH t FSR t RFH DT/OE DSF t CST t AST t RST Low SE t SCC t SC t STS SC SI/O (Output) 511 (255) t SCA t SOH Valid Sout t SCP n (n+255) n+1 (n+256) t SCA Valid Sout Valid Sout n+2 (n+257) 253 (509) 254 (510) 255 (511) t SOH Valid Sout Valid Sout Valid Sout SI/O (Input) t SQD t SQD t SQH t SQH QSF 40 SAM Address MSB Yi+255 (Yi) HM534253B Series Split Write Transfer Cycle t RC t RP t RAS RAS t CSH t RSH t RCD t CAS CAS t ASR Address t RAL t RAH SAM Start Address Yi Row t WS t CAH t ASC t WH WE t OFF1 High-Z I/O (Output) t DTS t DTH t FSR t RFH DT/OE DSF t CST t AST t RST Low SE t SCC t SC t STS SC 511 (255) SI/O (Output) SI/O (Input) n (n+255) t SIS n+1 (n+256) t SIH Valid Sin Valid Sin t SCP n+2 (n+257) t SIS Valid Sin n+3 (n+258) t SIH Valid Sin 255 (511) t SIS Valid Sin Yi+255 (Yi) t SIH Valid Sin Valid Sin t SQD t SQD t SQH t SQH QSF 254 (510) SAM Address MSB 41 HM534253B Series Serial Read Cycle SE tSCC SC SI/O (Output) tSCC tSC tSCP tSC tSCA tSOH tSCP tSC tSCA Valid Sout Valid Sout Serial Write Cycle tSWIS tSWH tSWIH tSWS SE tSCC tSC tSCP SC tSIS SI/O (Input) 42 tSIH Valid Sin tSC tSCA tSOH tSEA tSEZ Valid Sout tSCC tSCP tSCC tSC tSCC tSC tSCP tSIS tSC tSCP tSIH Valid Sin tSIS tSIH Valid Sin Valid Sout HM534253B Series Package Dimensions HM534253BJ Series (CP-28D) Unit: mm 18.17 18.54 Max 10.16 0.13 1 11.18 0.13 15 28 0.80 +0.25 -0.17 3.50 0.26 1.30 Max 1.27 0.43 0.10 0.21 2.40 +- 0.24 14 0.74 9.40 0.25 0.10 HM534253BZ Series (ZP-28) Unit: mm 1 28 1.27 0.3 M 1.045 Max 10.16 Max 0.10 0.25 +- 0.05 2.54 2.85 + 0.08 0.50 - 0.12 2.80 Min 8.71 35.58 36.57 Max 43