1. General description
The CBTL06122 is a six-channel (‘hex’) multiplexer for DisplayPort and PCI Express Gen2
applications. It provides four differential channels capable of switching or multiplexing
(bidirectional and AC-coupled) PCI Express Gen2 or DisplayPort signals, using
high-bandwidth pass-gate technology. Additionally, it provides for switching/multiplexing of
the Hot Plug Detect signal as well as the AUX or DDC (Direct Display Control) signals, for
a total of six channels.
The CBTL06122 is designed for high-performance PCI Express Gen2 and DisplayPort
applications. The device is available in two different pinouts (A and B, orderable as
separate part numbers) to suit different motherboard layout requirements.
The typical application of CBTL06122 is on motherboards, docking stations or add-in
cards where the graphics and I/O system controller chip utilizes I/O pins that are
configurable for either PCI Express or DisplayPort operation. The hex display MUX can be
used in such applications to route the signal from the controller chip to either a physical
DisplayPort connector or a PCI Express connector using its 1 : 2 multiplexer topology. The
controller chip selects which path to use by setting a select signal (which can be latched)
HIGH or LOW.
Optionally, the hex MUX device can be used in conjunction with an HDMI/DVI level shifter
device (PTN3300A, PTN3300B or PTN3301) to allow for DisplayPort as well as HDMI/DVI
connectivity.
CBTL06122
High-performance DisplayPort/PCIe Gen2 hex display
multiplexer
Rev. 02 — 16 April 2009 Product data sheet
CBTL06122_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 16 April 2009 2 of 19
NXP Semiconductors CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
Fig 1. Intended usage 1: DisplayPort docking solution for mobile platform
Fig 2. Intended usage 2: HDMI/DVI docking solution for mobile platform
DP
HPD
AUX
CBTL06122
docking connector
DisplayPort
connector
DisplayPort
REPEATER
DisplayPort
connector
MULTI-MODE
DISPLAY SOURCE
PEG
002aad649
44
4
HPD
DDC
docking connector
HDMI/DVI
connector
PTN3300A/B or
PTN3301
HDMI/DVI
connector
MULTI-MODE
DISPLAY SOURCE
PEG
002aad650
HDMI/DVI
dock
PTN3300A/B
or
PTN3301
CBTL06122
44
4
CBTL06122_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 16 April 2009 3 of 19
NXP Semiconductors CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
2. Features
n1 : 2 multiplexing of DisplayPort (v1.1 - 2.7 Gbit/s) or PCI Express (Gen2 - 5.0 Gbit/s)
signals
u4 high-speed differential channels
u1 channel for AUX differential signals or DDC clock and data
u1 channel for HPD
nHigh-bandwidth analog pass-gate technology
nVery low intra-pair differential skew (< 5 ps)
nVery low inter-pair skew (< 180 ps)
nAll path delays matched including between RX1− to X− and RX1+ to X+
nSwitch/MUX position select with latch function
nShutdown mode CMOS input
nShutdown mode minimizes power consumption while switching all channels off
nVery low operation current of 0.2 mA typ
nVery low shutdown current of < 10 µA
nStandby mode minimizes power consumption while switching all channels off
nSingle 3.3 V power supply
nESD 4 kV HBM, 1 kV CDM
nTwo pinouts (A and B) available as separate ordering part numbers
nAvailable in 11 mm ×5 mm HWQFN56R package
Fig 3. Intended usage 3: Digital display + external graphics solution for desktop
platform
HPD/PEG RX
AUX/PEG RX
DP/
HDMI/
DVI
connector
x16 PEG connector
MULTI-MODE
DISPLAY SOURCE
PEG
002aad651
DP/HDMI/
DVI/PEG PTN3300A/B
or
PTN3301
DDC
CBTL06122
44
4
CBTL06122_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 16 April 2009 4 of 19
NXP Semiconductors CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
3. Applications
nMotherboard applications requiring DisplayPort and PCI Express Gen 2
switching/multiplexing
nDocking stations
nNotebook computers
nChip sets requiring flexible allocation of PCI Express or DisplayPort I/O pins to board
connectors
4. Ordering information
[1] The A and B suffix in the part number correspond to the A and B pinouts, respectively (see Figure 5 and Figure 6).
[2] HF is the package designator for the HWQFN package.
[3] Total height after printed-circuit board mounting = 0.8 mm (max.).
Table 1. Ordering information
Type number Package
Name Description Version
CBTL06122AHF[1][2] HWQFN56R plastic thermal enhanced very very thin quad flat package; no leads;
56 terminals; resin based; body 11 ×5×0.7 mm[3] SOT1033-1
CBTL06122BHF[1][2]
CBTL06122_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 16 April 2009 5 of 19
NXP Semiconductors CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
5. Functional diagram
Fig 4. Functional diagram
002aad652
D0−
D0+
IN_0−
IN_0+
CBTL06122
SEL
DP CONNECTOR
DATA LANE
AC-coupled
differential pair
MULTI-MODE
DISPLAY SOURCE
TX
PCIe PHY
ELECTRICAL
PCIe
output buffer
MUX
LOGIC
LE_N
TX0−
TX0+
D1−
D1+
IN_1−
IN_1+
DATA LANE
AC-coupled
differential pair
TX
PCIe
output buffer
TX1−
TX1+
D2−
D2+
IN_2−
IN_2+
DATA LANE
AC-coupled
differential pair
TX
PCIe
output buffer
TX2−
TX2+
D3−
D3+
IN_3−
IN_3+
DATA LANE
AC-coupled
differential pair
TX
PCIe
output buffer
TX3−
TX3+
HPD
RX1+
X+
X−
X− to RX1− path matches
X+ to RX1+ path
RX1−
RX
PCIe
input buffer
AUX−
AUX+
OUT−
OUT+
RX0−
RX0+
AUX DATA
RX
PCIe
input buffer
TX
PEG CONNECTOR
OR
DOCKING CONNECTOR
SPARE
XSD
CBTL06122_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 16 April 2009 6 of 19
NXP Semiconductors CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
6. Pinning information
6.1 Pinning
Fig 5. Pin configuration for HWQFN56R, A pinout Fig 6. Pin configuration for HWQFN56R, B pinout
GND
VDD
SPARE
HPD
AUX−
AUX+
VDD
GND
GND
D3−
D3+
D2−
D2+
D1−
D1+
D0−
D0+
TX3−
TX3+
TX2−
TX2+
GND
GND
RX1−
RX1+
RX0−
RX0+
VDD
GND
VDD
TX0+
TX0−
TX1+
TX1−
XSD
GND
OUT−
OUT+
GND
IN_3−
IN_3+
VDD
IN_1−
IN_1+
IN_0−
IN_0+
GND
IN_2−
IN_2+
X+
LE_N
SEL
VDD
GND
X−
GND
terminal 1
index area
4
1
2
3
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
45
48
47
46
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
21
22
23
24
25
26
27
28 49
50
51
52
53
54
55
56
002aad653
Transparent top view
CBTL06122AHF
A pinout
GND
TX3−
TX3+
TX2−
TX2+
TX1−
TX1+
TX0−
TX0+
D3−
D3+
D2−
D2+
GND
GND
SPARE
HPD
AUX−
AUX+
VDD
GND
VDD
D0+
D0−
D1+
D1−
GND
XSD
GND
VDD
RX1−
RX1+
RX0−
RX0+
VDD
GND
IN_3−
IN_3+
GND
IN_2−
IN_2+
VDD
IN_0−
IN_0+
LE_N
SEL
GND
IN_1−
IN_1+
OUT+
X−
X+
VDD
GND
OUT−
GND
terminal 1
index area
4
1
2
3
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
45
48
47
46
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
21
22
23
24
25
26
27
28 49
50
51
52
53
54
55
56
002aad654
Transparent top view
CBTL06122BHF
B pinout
CBTL06122_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 16 April 2009 7 of 19
NXP Semiconductors CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
6.2 Pin description
Table 2. Pin description
Symbol Pin Type Description
Pinout A Pinout B
SEL 18 2 3.3 V low-voltage CMOS
single-ended input SEL controls the MUX through a flow-through latch.
LE_N 19 3 3.3 V low-voltage CMOS
single-ended input The latch gate is controlled by LE_N.
XSD 50 50 3.3 V low-voltage CMOS
single-ended input Optional shutdown pin. Should be driven HIGH or
connected to VDD for normal operation. When LOW, all
paths are switched off (non-conducting) and supply current
consumption is minimized.
RX0+ 33 26 differential input Differential input from PCIe connector or device. RX0+
makes a differential pair with RX0−. RX0+ is passed
through to the OUT+ pin when SEL = 0.
RX0−32 25 differential input Differential input from PCIe connector or device. RX0−
makes a differential pair with RX0+. RX0− is passed
through to the OUT− pin when SEL = 0.
RX1+ 31 24 differential input Differential input from PCIe connector or device. RX1+
makes a differential pair with RX1−. RX1+ is passed
through to the X+ pin when SEL = 0.
RX1−30 23 differential input Differential input from PCIe connector or device. RX1−
makes a differential pair with RX1+. RX1− is passed
through to the X− pin on a path that matches the RX1+ to
X+ path.
IN_0+ 2 4 differential input Differential input from display source PCIe outputs.
IN_0+ makes a differential pair with IN_0−.
IN_0−3 5 differential input Differential input from display source PCIe outputs.
IN_0−makes a differential pair with IN_0+.
IN_1+ 4 7 differential input Differential input from display source PCIe outputs.
IN_1+ makes a differential pair with IN_1−.
IN_1−5 8 differential input Differential input from display source PCIe outputs.
IN_1−makes a differential pair with IN_1+.
IN_2+ 7 9 differential input Differential input from display source PCIe outputs.
IN_2+ makes a differential pair with IN_2−.
IN_2−8 10 differential input Differential input from display source PCIe outputs.
IN_2−makes a differential pair with IN_2+.
IN_3+ 9 12 differential input Differential input from display source PCIe outputs.
IN_3+ makes a differential pair with IN_3−.
IN_3−10 13 differential input Differential input from display source PCIe outputs.
IN_3−makes a differential pair with IN_3+.
HPD 24 31 high-voltage
single-ended input Low frequency, 0 V to 5 V/3.3 V (nominal) input signal. This
signal comes from the HDMI/DP connector. Voltage HIGH
indicates a ‘plugged’ state; voltage LOW indicates
‘unplugged’.
X+ 14 18 (SEL = HIGH); HPD:
high-voltage single-ended
input
Low frequency, 0 V to 5 V/3.3 V (nominal) input signal. This
signal comes from the HDMI/DP connector.
(SEL = LOW); X+:
pass-through output Analog ‘pass-through’ output corresponding to RX1+.
CBTL06122_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 16 April 2009 8 of 19
NXP Semiconductors CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
[1] HWQFN56R package die supply ground is connected to both GND pins and exposed center pad. GND pins must be connected to
supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be
soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region.
X−15 19 pass-through output
from RX1− input X−is an analog ‘pass-through’ output corresponding to the
RX1−input. The path from RX1−to X−is matched with the
path from RX1+ to X+. X+ and X− form a differential pair
when the pass-through MUX mode is selected.
D0+ 43 54 pass-through output 1,
option 1 Analog ‘pass-through’ output 1 corresponding to IN_0+
and IN_0−, when SEL = 1.
D0−42 53
D1+ 41 52 pass-through output 2,
option 1 Analog ‘pass-through’ output 1 corresponding to IN_1+
and IN_1−, when SEL = 1.
D1−40 51
D2+ 39 47 pass-through output 3,
option 1 Analog ‘pass-through’ output 1 corresponding to IN_2+
and IN_2−, when SEL = 1.
D2−38 46
D3+ 37 45 pass-through output 4,
option 1 Analog ‘pass-through’ output 1 corresponding to IN_3+
and IN_3−, when SEL = 1.
D3−36 44
TX0+ 54 43 pass-through output 1,
option 2 Analog ‘pass-through’ output 2 corresponding to IN_0+
and IN_0−, when SEL = 0.
TX0−53 42
TX1+ 52 41 pass-through output 2,
option 2 Analog ‘pass-through’ output 2 corresponding to IN_1+
and IN_1−, when SEL = 0.
TX1−51 40
TX2+ 47 39 pass-through output 3,
option 2 Analog ‘pass-through’ output 2 corresponding to IN_2+
and IN_2−, when SEL = 0.
TX2−46 38
TX3+ 45 37 pass-through output 4,
option 2 Analog ‘pass-through’ output 2 corresponding to IN_3+
and IN_3−, when SEL = 0.
TX3−44 36
VDD 6, 17, 22,
27, 34,
55
6, 17, 22,
27, 34,
55
3.3 V supply Supply voltage (3.3 V ±10 %).
AUX+ 26 33 differential input High-speed differential pair for AUX signals.
AUX−25 32 differential input
OUT+ 12 14 differential input High-speed differential pair for PCIe RX0+ signal.
OUT−13 15 differential input High-speed differential pair for PCIe RX0− signal.
GND[1] 1, 11, 16,
20, 21,
28, 29,
35, 48,
49, 56
1, 11, 16,
20, 21,
28, 29,
35, 48,
49, 56
supply ground Ground.
SPARE 23 30 single-ended input Spare channel for general-purpose switch use.
Connected to pin X− when SEL = 1.
Table 2. Pin description
…continued
Symbol Pin Type Description
Pinout A Pinout B
CBTL06122_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 16 April 2009 9 of 19
NXP Semiconductors CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
7. Functional description
Refer to Figure 4 “Functional diagram”.
The CBTL06122 uses 3.3 V power supply. All signal paths are implemented using
high-bandwidth pass-gate technology, are bidirectional and no clock or reset signal is
needed for the multiplexer to function.
The switch position is selected using the select signal (SEL), which can be latched using
the latch enable pin (LE_N). The detailed operation is described in Section 7.1.
7.1 MUX select (SEL) function
The internal multiplexer switch position is controlled by two logic inputs SEL and LE_N as
described below.
The switch position select input signal SEL controls the MUX through a flow-through latch,
which is gated by the latch enable input signal LE_N (active LOW). The latch is open
when LE_N is LOW; in this state the internal switch position will respond to the state of the
SEL input signal. The latch is closed when LE_N is HIGH, and the switch position will not
respond to input state changes on the SEL input.
Table 3. MUX select control
SEL Dx TXx; RXx
0 high-impedance active; follows IN_x
1 active; follows IN_x high-impedance
Table 4. MUX select latch control
LE_N Internal MUX select
0 responds to changes on SEL
1 latched
Fig 7. MUX select function
002aad088
IN_x+ Dx+
TXx+
IN_x−Dx−
TXx−
internal
MUX select
TRANSPARENT
LATCH
SEL LE_N
CBTL06122_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 16 April 2009 10 of 19
NXP Semiconductors CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
7.2 Shutdown function
The CBTL06122 provides a shutdown function to minimize power consumption when the
application is not active but power to the CBTL06122 is provided. Pin XSD (active LOW)
puts all channels in off mode (non-conducting) while reducing current consumption to
near-zero.
8. Limiting values
[1] Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model -
Component level; Electrostatic Discharge Association, Rome, NY, USA.
[2] Charged Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged Device
Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.
9. Recommended operating conditions
Table 5. Shutdown function
XSD State
0 shutdown
1 active
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage −0.3 +5 V
Tcase case temperature for operation within
specification −40 +85 °C
Vesd electrostatic discharge
voltage HBM [1] - 4000 V
CDM [2] - 1000 V
Table 7. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VDD supply voltage 3.0 3.3 3.6 V
VIinput voltage - - 3.6 V
Tamb ambient temperature operating in free air −40 - +85 °C
CBTL06122_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 16 April 2009 11 of 19
NXP Semiconductors CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
10. Characteristics
10.1 General characteristics
10.2 DisplayPort channel characteristics
10.3 AUX and DDC ports
[1] Time from DDC/AUX input changing state to AUX output changing state. Includes DDC/AUX rise/fall time.
Table 8. General characteristics
Symbol Parameter Conditions Min Typ Max Unit
IDD supply current operating mode (XSD = HIGH); VDD = 3.3 V - 0.2 1 mA
shutdown mode (XSD = LOW); VDD = 3.3 V - - 10 µA
Ptot total power dissipation operating mode (XSD = HIGH); VDD = 3.3 V - - 5 mW
tstartup start-up time supply voltage valid or XSD going HIGH to
channel specified operating characteristics --1ms
trcfg reconfiguration time SEL state change to channel specified
operating characteristics --1ms
Table 9. DisplayPort channel characteristics
Symbol Parameter Conditions Min Typ Max Unit
VIinput voltage −0.3 - +2.6 V
VIC common-mode input voltage 0 - 2.0 V
VID differential input voltage −1.2 - +1.2 V
DDIL differential insertion loss channel is on; 0 Hz ≤f≤1.0 GHz −2.5 −1.6 - dB
channel is on; f = 2.5 GHz −4.5 - - dB
channel is off; 0 Hz ≤f≤3.0 GHz - - −20 dB
DDRL differential return loss channel is on; 0 Hz ≤f≤1.0 GHz - - −10 dB
DDNEXT differential near-end crosstalk adjacent channels are on;
0Hz≤f≤1.0 GHz --−30 dB
B bandwidth −3.0 dB intercept - 2.5 - GHz
−5.0 dB intercept - 4.0 - GHz
tPD propagation delay from left-side port to right-side port
or vice versa - 180 - ps
tsk(dif) differential skew time intra-pair - - 5 ps
tsk skew time inter-pair - - 180 ps
Table 10. AUX and DDC port characteristics
Symbol Parameter Conditions Min Typ Max Unit
VIinput voltage DDC or AUX −0.3 - +2.6 V
VIC common-mode input voltage DDC or AUX 0 - 2.0 V
VID differential input voltage −1.2 - +1.2 V
tPD propagation delay from left-side port to right-side port
or vice versa [1] - 180 - ps
CBTL06122_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 16 April 2009 12 of 19
NXP Semiconductors CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
10.4 HPD input, HPD output
[1] Low-speed input changes state on cable plug/unplug.
[2] Time from HPD_SINK changing state to HPD changing state. Includes HPD rise/fall time.
10.5 MUX select and latch input
11. Test information
11.1 Switch test fixture requirements
The test fixture for switch S-parameter measurement shall be designed and built to
specific requirements, as described below, to ensure good measurement quality and
consistency.
•The test fixture shall be a FR4-based PCB of the microstrip structure; the dielectric
thickness or stack-up shall be about 4 mils.
•The total thickness of the test fixture PCB shall be 1.57 mm (0.62 in).
•The measurement signals shall be launched into the switch from the top of the test
fixture, capturing the through-hole stub effect.
•Traces between the DUT and measurement ports (SMA or microprobe) should be
uncoupled from each other, as much as possible. Therefore, the traces should be
routed in such a way that traces will diverge from each other exiting from the switch
pin field.
•The trace lengths between the DUT and measurement port shall be minimized. The
maximum trace length shall not exceed 1000 mils. The trace lengths between the
DUT and measurement port shall be equal.
•All of the traces on the test board and add-in card must be held to a characteristic
impedance of 50 Ω with a tolerance of ±7%.
•SMA connector is recommended for ease of use. The SMA launch structure shall be
designed to minimize the connection discontinuity from SMA to the trace. The
impedance range of the SMA seen from a TDR with a 60 ps rise time should be
within 50 Ω±7Ω.
Table 11. HPD input and output characteristics
Symbol Parameter Conditions Min Typ Max Unit
VIinput voltage [1] −0.3 - 3.6 V
tPD propagation delay from HPD_SINK to HPD_SOURCE [2] - 180 - ps
Table 12. SEL, LE_N input characteristics
Symbol Parameter Conditions Min Typ Max Unit
VIH HIGH-level input voltage SEL/LE_N 2.0 - 3.6 V
VIL LOW-level input voltage SEL/LE_N 0 - 0.8 V
ILI input leakage current measured with input at
VIH(max) and VIL(min)
--10µA
CBTL06122_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 16 April 2009 13 of 19
NXP Semiconductors CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
12. Package outline
Fig 8. Package outline HWQFN56R (SOT1033-1)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT1033-1
SOT1033-1
UNIT A
max
mm 0.8 0.27
0.23 5.1
4.9 11.1
10.9
2.5
2.3 8.5
8.3 0.42
0.38 0.1
0.0
b
DIMENSIONS (mm are the original dimensions)
HWQFN56R: plastic thermal enhanced very very thin quad flat package; no leads;
56 terminals; resin based; body 11 x 5 x 0.7 mm
0 2.5 5 mm
scale
D DhEh
E e e1e2
9.53.50.5
L L1v
0.1
w y
0.050.05
y1
0.1
terminal 1
index area
B A
D
E
X
C
y
C
y1
detail X
A
e2
e
1/2 e
29
28
20
48
1
21
4956
b
e1
e
1/2 e AC B
vMCw M
Dh
Eh
L1L
- - - - - -- - - 07-09-19
07-12-01
CBTL06122_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 16 April 2009 14 of 19
NXP Semiconductors CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note
AN10365 “Surface mount reflow
soldering description”
.
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
•Through-hole components
•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•Board specifications, including the board finish, solder masks and vias
•Package footprints, including solder thieves and orientation
•The moisture sensitivity level of the packages
•Package placement
•Inspection and repair
•Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
•Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
•Solder bath specifications, including temperature and impurities
CBTL06122_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 16 April 2009 15 of 19
NXP Semiconductors CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
13.4 Reflow soldering
Key characteristics in reflow soldering are:
•Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 9) than a SnPb process, thus
reducing the process window
•Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
•Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 13 and 14
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 9.
Table 13. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350 ≥ 350
< 2.5 235 220
≥ 2.5 220 220
Table 14. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245
CBTL06122_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 16 April 2009 16 of 19
NXP Semiconductors CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
For further information on temperature profiles, refer to Application Note
AN10365
“Surface mount reflow soldering description”
.
14. Abbreviations
MSL: Moisture Sensitivity Level
Fig 9. Temperature profiles for large and small components
001aac844
temperature
time
minimum peak temperature
= minimum soldering temperature
maximum peak temperature
= MSL limit, damage level
peak
temperature
Table 15. Abbreviations
Acronym Description
AUX Auxiliary channel in DisplayPort definition
CDM Charged-Device Model
CMOS Complementary Metal-Oxide Semiconductor
DDC Direct Display Control
DP DisplayPort
DUT Device Under Test
DVI Digital Video Interface
ESD ElectroStatic Discharge
HBM Human Body Model
HDMI High-Definition Multimedia Interface
HPD Hot Plug Detect
I/O Input/Output
MUX Multiplexer
PCB Printed-Circuit Board
PCI Peripheral Component Interconnect
PCIe PCI Express
PEG PCI Express Graphics
SMA SubMiniature, version A (connector)
TDR Time-Domain Reflectometry
CBTL06122_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 16 April 2009 17 of 19
NXP Semiconductors CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
15. Revision history
Table 16. Revision history
Document ID Release date Data sheet status Change notice Supersedes
CBTL06122_2 20090416 Product data sheet - CBTL06122_1
Modifications: •Descriptive title of data sheet changed from “High-performance 4 GHz bandwidth hex display
multiplexer” to “High-performance DisplayPort/PCIe Gen2 hex display multiplexer”
•Section 1 “General description”:
–1st paragraph, 1st sentence: changed from “... and PCI Express applications.” to “... and PCI
Express Gen2 applications.”
–1st paragraph, 2nd sentence: changed from “... PCI Express or DisplayPort signals, ...”
to “... PCI Express Gen2 signals, ...”
–2nd paragraph, 1st sentence: changed from “... high-performance PCI Express and
DisplayPort applications.” to “... high-performance PCI Express and DisplayPort applications.”
•Section 2 “Features”:
–1st bullet item: changed from “... PCI Express signals” to “... PCI Express Gen2 signals”
–13th bullet item: changed from “ESD 8 kV HBM” to “ESD 4 kV HBM”
•Section 3 “Applications”, 1st bullet item: changed from “... PCI Express switching/multiplexing”
to “... PCI Express Gen2 switching/multiplexing”
•Table 6 “Limiting values”, Vesd (HBM) maximum value changed from “8000 V” to “4000 V”
•Table 9 “DisplayPort channel characteristics”:
–updated DDIL values
–updated DDRL values
–updated DDNEXT values
–updated B values
CBTL06122_1 20080523 Product data sheet - -
CBTL06122_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 16 April 2009 18 of 19
NXP Semiconductors CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
NXP Semiconductors CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
© NXP B.V. 2009. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 16 April 2009
Document identifier: CBTL06122_2
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 4
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 5
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 6
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7
7 Functional description . . . . . . . . . . . . . . . . . . . 9
7.1 MUX select (SEL) function . . . . . . . . . . . . . . . . 9
7.2 Shutdown function . . . . . . . . . . . . . . . . . . . . . 10
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10
9 Recommended operating conditions. . . . . . . 10
10 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 11
10.1 General characteristics. . . . . . . . . . . . . . . . . . 11
10.2 DisplayPort channel characteristics . . . . . . . . 11
10.3 AUX and DDC ports . . . . . . . . . . . . . . . . . . . . 11
10.4 HPD input, HPD output. . . . . . . . . . . . . . . . . . 12
10.5 MUX select and latch input. . . . . . . . . . . . . . . 12
11 Test information. . . . . . . . . . . . . . . . . . . . . . . . 12
11.1 Switch test fixture requirements . . . . . . . . . . . 12
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
13 Soldering of SMD packages . . . . . . . . . . . . . . 14
13.1 Introduction to soldering . . . . . . . . . . . . . . . . . 14
13.2 Wave and reflow soldering . . . . . . . . . . . . . . . 14
13.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 14
13.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 15
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
17 Contact information. . . . . . . . . . . . . . . . . . . . . 18
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
