ANALOG DEVICES PRELIMINARY TECHNICAL DATA FEATURES Lowest Cost 10-Bit DAC Direct AD7520 Equivalent Linearity: %, 1 or 2LSB Low Power Dissipation Full Four-Quadrant Multiplying DAC CMOS/TTL Direct Interface APPLICATIONS Digitally Controlled Attenuators Programmable Gain Amplifiers Function Generation Linear Automatic Gain Control GENERAL DESCRIPTION The AD7533 is a low cost 10-bit 4-quadrant multiplying DAC manufactured using an advanced thin-film-on-monolithic-CMOS wafer fabrication process. Pin and function equivalent to the industry standard AD7520, the AD7533 is recommended as a lower cost alternative for old AD7520 sockets or new 10-bit DAC designs. AD7533 application flexibility is demonstrated by its ability to interface to TTL or CMOS, operate or. +5V to +15V pow- er, and provide proper binary scaling for reference inputs of either positive or negative polarity. FUNCTIONAL DIAGRAM Vag 10k 10k _+ 10k 2 20k 20k 20k 20k 20k $1 $2 ) $-3 S-N aA. A A A. I I i} | | L ! I ! ? ! t O lout2 I 1 I 1 4 1 i Le -_Olouts i i 1 I L ok t \ 1 | AAO RreeDBack 6 34 6 BIT 1 (MSB) BiT 2 BIT 3 BIT 10 (LSB) DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE) Logic: A switch is closed to Igyry 1 for its digital input in a HIGH state. ORDERING INFORMATION Temperature Range and Package CMOS Low Cost 10-Bit Multiplying DAC Nonlinearity Commercial Industrial Military (Plastic) (Ceramic) (Ceramic) 0 to +70C ~25C to +85C 55C to +125C +0.2% AD7533JN AD7533AD AD7533SD AD7533AD/883B AD7533SD/883B 0.1% AD7533KN AD7533BD AD7533TD AD7533BD/883B AD7533TD/883B 0.05% AD7533LN AD7533CD AD7533UD AD7533CD/883B AD7533UD/883B PIN CONFIGURATION TOP VIEW VW out1} 4 16] Fre ouT2 | 2 15] Vace ono [s 14| Voo [J BIT 1 (MSB)| 4 ait af 5 BIT 3] 6 2)/BIT 9 "W Jair 8 BIT 4] 7 10 | BIT 7 BIT 5| 8 9 ] err 6 AD7533 13 | BIT 10 1LSB) D/A CONVERTERS 327SPECIFICATIONS (Vop =+15V; Vo UT1= VoOUT2 = OV; VREF = +10V unless otherwise noted) PARAMETER Ta = 25C Ta = Operating Range Test Conditions STATIC ACCURACY Resolution 10 Bits 10 Bits Nonlinearity AD7533JN, AD, SD AD7533KN, BD, TD AD7533LN, CD, UD Gain Error Supply Rejection* +0.2% FSR max +0.1% FSR max +0.05% FSR max +1.4% FS max +0.2% FSR max +0.1% FSR max +0.05% FSR max +1.5% FS max Digital Inputs = Vinu AGain/AVpp 0.005'%/% 0.008%/% Digital Inputs = Ving; Vop = +14V to +17V Output Leakage Current IouTi (pin 1) +50nA max +200nA max Digital Inputs = Vinc; Veer = +10V IouT2 (pin 2) 50nA max 200nA max Digital Inputs = Vinn; VReF = +10V DYNAMIC ACCURACY Output Current Settling Time 600ns max 800ns* To 0.05% FSR; Rigap = 1002; Digital Feedthrough Error +0.05% FSR max* +0.1% FSR max? Inputs = Ving to Vinx OF Vint to VinH Digital Inputs = Vin_; Vrer = 10V, 100kHz sinewave. REFERENCE INPUT Input Resistance (pin 15) 5kQ min, 20k922. max kQ min, 20k92 max ANALOG OUTPUTS Output Capacitance : ; 4 4 CouT1 (pin 1) 100p! max 100pF max \ Digital Inputs = Vint CouTz (pin 2) 35pF max 35pF max f . 4 4 CouT1 (pin 1) 35pF max , 35pF max . \ Digital Inputs = Vint CoutTz (pin 2) 100pF? max 100pF max J DIGITAL INPUTS Input High Voltage VINH 2.4V min 2.4V min Input Low Voltage VINL 0.8V max 0.8V max Input Leakage Current tn +1pA max +1pA max Vin = OV and Vpp Input Capacitance Cin 5pF roax* 5pF max* POWER REQUIREMENTS Vpp +15V 410% +15V +10% Rated Accuracy Vpp Range* +5V to +16V +5V to +16V Functionality with degraded performance Ipp 2mA max 2mA max Digital Inputs = Viny or VINH Ipp 100uA max 150uA max Digital Inputs = OV or Vpp NOTES: ! Plastic (JN, KN, LN versions): 0 to +70C Commercial Ceramic (AD, BD, CD versions): -25C to +85C Military Ceramic (SD, TD, UD versions): -55C to +125C 2FSR" is Full Scale Range. 3 Full Scale (FS) = -Vree( 4 Guaranteed, not tested. 1023 1024 5 AC parameter, sample tested to ensure specification compliance. 6 Absolute temperature coefficient is approximately -300ppm/C. 7100% screened to MIL-STD-883, method 5004, para. 3.1.1 through 3.1.12 for class B device. Fina! electrical tests are: Nonlinearity, Gain Error, Output Leakage Current, VinH. VINL; HN and Ipp at +25C and +125C (SD, TD, UD versions) or +25C and +85'C (AD, BD, CD versions). Specifications subject to change without notice. 328 D/A CONVERTERSABSOLUTE MAXIMUM RATINGS (Ta = +2 5C unless otherwise noted) Vpp toGND ............. Lee eee -0.3V,+17V Ceramic (Suffix D) Rrp toGND ....... 0.0.00. eee eee eee 25V TO475C. eee 450mW VREF tOGND. 2... ee en es +25V Derates above +75C a 6mW/C Digital Input Voltage Range ............. -0.3Vto Vpp Operating Temperature Range Output Voltage (pin 1, pin 2) ............ -0.3V to Vpp Commercial (JN, KN, LN versions). ........ 0 to +70C Power Dissipation (Package) Industrial (AD, BD, CD versions) ....... -25C to +85C Plastic (Suffix N) Military (SD, TD, UD versions) ....... -55C to +125C TOF7OC. oe eee 670mW Storage Temperature................ ~65C to +150C Derates above +70C by........... 0.005. 8.3mW/C Lead Temperature (Soldering, 10 seconds)........ +300C CAUTION: ductive foam or shunts. and 6. 1. ESD sensitive device. The digital control inputs are Zener protected; however, permanent damage may occur on unconnected devices subjected to high energy electrostatic fields. Unused devices must be stored in con- 2. Do not apply voltages lower taan ground or higher the Vpp to any pin except Vrgr (pin 15) and Rpg (pin 16). Pply g g 3 3. The inputs of some IC amplifiers (especially wide bandwidth types) present a low impedance to V~ during power-up or power-down sequencing. To prevent the AD7533 OUT1 or OUT2 terminals from exceeding ~300mV (which causes catastrophic substrate current) a Schottky diode (HP5082-2811 or equivalent) is recommended. The diode should be connected between OUT1 (OUT2) and ground as shown in Figures 5 TERMINOLOGY NONLINEARITY: Error contributed by deviation of the DAC transfer function from a best straight line function. Normally expressed as a percentage of full scale range. For a multiplying DAC, this should hold true over the entire VppR range. RESOLUTION: Value of the LSB. For example, a unipolar converter with n bits has a resolution of (2") (VrERF)- A bipolar converter of n bits has a resolution of [2@~1)] [Verrpl. Resolution in no way implies linearity. SETTLING TIME: Time required for the output function of the DAC to settle to within 1/2 LSB for a given digital input stimulus, i.e., 0 to Full Scale. GAIN: Ratio of the DACs operational amplifier output voltage to the input voltage. FEEDTHROUGH ERROR: Error caused by capacitive coupling from Verr to output with all switches OFF. OUTPUT CAPACITANCE: = Capacity from Igy, and Ipur2 terminals to ground. OUTPUT LEAKAGE CURRENT: Current which appears on louri terminal with all digital inputs LOW or on Ipy72 terminal when all inputs are HIGH. D/A CONVERTERS 329CIRCUIT DESCRIPTION GENERAL CIRCUIT INFORMATION The AD7533, a 10-bit multiplying D/A converter, consists of a highly stable thin film R-2R ladder and tea CMOS current switches on a monolithic chip. Most applications require the addition of only an output operational amplifier and a voltage or current reference. The simplified D/A circuit is shown in Figure 1. An inverted R-2R ladder structure is used that is, the binarily weighted currents are switched between the I9yt1 and Igyurz2 bus lines, thus maintaining a constant current in each ladder leg inde- pendent of the switch state. Vaer Jo 20k 20k SN aA 1 iT + ~Olourtz 1 T Olourt LLL | 10k $s -O Rreeopack BIT + (MSB) BIT 2 BIT 3 BIT 10 (LSB) DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBI E) Figure 1. AD7533 Functional Diagram One of the CMOS current switches is shown in Figure 2. The geometries of devices 1, 2 and 3 are optimized to make the digital control inputs DTL/TTL/CMOS compatible over the full military temperature range. The input stage drives two inverters (devices 4, 5, 6 and 7) which in turn drive the two output N-channels. The ON resistances of the switches are binarily sealed so the voltage drop across each switch is the same. For example, switch 1 of Figure 2 was designed for an ON resistance of 20 ohms, switch 2 or 40 ohms and so on. For a 10V reference input, the curreat through switch 1 is 0.5mA, the current through switch 2 is 0.25mA, and so on, thus maintaining a constant 10mV drop across each switch. It is essential that each switch voltaze drop be equal if the binarily weighted current division property of the ladder is to be maintained. DTL/TTL/CMOS | INPUT < 5 7 * Figure 2. CMOS Switch lout, lout, 330 D/A CONVERTERS Vrer 1/1024 4 1 LEAKAGE Figure 3. AD7533 Equivalent Circuit All Digital Inputs Low EQUIVALENT CIRCUIT ANALYSIS The equivalent circuits for all digital inputs high and all digital inputs low are shown in Figures 3 and 4. In Figure 3 with all digital inputs low, the reference current is switched to Iour2. The current source ILEAKAGE is composed of surface and junction leakages to the substrate while the saat current source represents a constant 1-bit current drain through the termination resistor on the R-2R ladder. The ON capacitance of the output N channel switch is 120pF, as shown on the lour2 terminal. The OFF switch capacitance is 30pF, as shown on the Ignyr1 terminal. Analysis of the circuit for all digital ir.puts high, as shown in Figure 4, is similar to Figure 3, however, the ON switches are now on terminal Iout1, hence the 100pF at that terminal. OR EEOBACK ' R~ 10K82 REF ok Ve ce + + > &O lout R L wioea le iLeakaGe = O lourz 35pF | "LEAKAGE L Figure 4. AD7533 Equivalent Circuit All Digital Inputs HighOPERATION UNIPOLAR BINARY OPERATION (2-QUADRANT MULTIPLICATION) BIPOLAR ANALOG INPUT +10V Fl 2k _. VRE Rep R2 1k MSB 15 14 16 1 ouT1 cr US UNIPOLAR 4 1 DIGITAL | AD7533 CRI Vout INPUT 2 Lour2 "sp + OF eY413 L. 3__ GND NOTES: 1. R1AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. 2. SCHCTTKY DIODE CR1 (HP50822811 OR EQUIV) PROTECTS OUT? TERMINAL AGAINST NEGATIVE TRANSIENTS. SEE CAUTION NOTE 3, 3. C1PFASE COMPENSATION (5 15pF) MAY BE REQUIRED WHEN USING HIGH SPEED AMPLIFIER. Figure 5. Unipolar Binary Operation (2-Quadrant Multiplication) DIGITAL INPUT NOMINAL ANALOG OUTPUT (Vout as shown in Figure 1) MSB LSB 1114111111 ~Vrer (4033) 1000000001 -VREF a 1000000000 -VREF (fey ~YREE 0111111111 -VREF i024) 0000000001 ~VREF (i024) 0000000000 -VREF (rox) = 0 NOTES: 1. Nominal Full Scale for the circuit of Figure 5 is given by FS = -Vrgr (1633) 2. Nominal LSB magnitude for the circuit of Figure 5 is given by LSB = Vegr Tema Table 1. Unipolar Binary Code Table BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION) ANALOG INPUT +10 9 Vood RI 2k x VREF A R2 1k > MSB | 15 1416 WA Noun C1 BIPOLAR T ~ DIGITAL AD7533 R32 -O INPUT 2 CouTe 5k $ CRI + Vout o-4 3 R4 5k > RS _ GND > 100k p___1 f? | h7 1MQ | AN > > R6 J 10k L cr $e NOTES: 1. R3/R4 MATCH 0.05% OR BETTER. 2. R1,R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED 3. 1,C2 PHASE COMPENSATION (5 - 15pF) MAY BE REQUIRED WHEN USING HIGH SPEED AMPLIFIERS. 4, SCHOTTKY DIODES CR1 AND CR2 {HP5082-2811 OR EQUIV} PROTECT OUT? AND OUT2 TERMINALS FROM WEGATIVE TRANSIENTS. SEE CAUTION NOTE 3. Figure 6. Bipolar Operation (4-Quadrant Multiplication) DIGITAL INPUT NOMINAL ANALOG OUTPUT (Vout as shown in Figure 2) MSB LSB 5 1111111111 -V (25) REF 512 1000000001 -Vree ( 5) 512 1000000000 0 1 1 a 011111111 +VREF (=) 511 0000000001 +VREF (5) 0000000000 +VREP Ee 512 NOTES: 1. Nominal Full Scale Range for the circuit of yA Figure 6 is given by FSR = Vrer (3) 2. Nominal LSB magnitude for the circuit of Figure 6 is given by LSB = Vrgr (sn ) Table 2. Bipolar (Offset Binary) Code Table APPLICATIONS 10-BIT AND SIGN MULTIPLYING DAC +40V ANALOG INPUT Vou VReF 10k 10k MsB 15 14 4 1 x out MN AD7512DJN macnituoel BITS 1 AD7533 L. 5k 1 LSB OuT2. + Vour Om113 3 ! OIGITAL INPUT GND | SIGNBIT PROGRAMMABLE FUNCTION GENERATOR CALIBRATE 47k 10K Kk = az | ~L = SQUARE + WAVE 10k 1% 10k 1% FA c CI Po a { van TS NAF ! ' 2 TRIANGULAR, be] 19 WAVE Re, DIGITAL FREQUENCY CONTROL WwoRD Ry = 10kS2 O<Ne(1-2%) DIGITALLY PROGRAMMABLE LIMIT DETECTOR TEST INPUT Veer +15V (0 TO -VpeF! mse 15 74 AD311 oe T4 16 COMPARATOR ! 1 rr DIGITAL AD7533 ey > FAIL/PASS TEST INPUT (TEST Limit)! tsp be LY D/A CONVERTERS 331OUTLINE DIMENSIONS Dimensions shown in inches and (mm). APPLICATIONS (continued) DIVIDER (DIGITALLY CONTROLLED GAIN) 16 PIN PLASTIC DIP +15V Vin O Rre MSB e ) 16 4 4 | o wit 1 0.26 (6.61) OUT2 ' 0.24 (6.1) AD7533 | INPUT 4 outa \a tsa! > PWV SN \ os 13}- BIT 10 0.755 (19.18) fe: 306 (7.78) mf + 18 t 0.745 (18.93) 0298 747 en Wace -VIN 0.17 (4.32. ones vy Vout = 5 ae 0.12 (3.05) Tm ~ where: _ 0: _t_ \ F >_+ Vout 5 BITI, BIT2, BITI0 ovens 1 Is sar tg t He 0.2 (3.05) = oc p< 1028 >| | a I 0.12(3.05)__ ve 9024 0.065 (1.66} 0.02 {0.508} in (2.67) 0.008 (2.03) 0.045 (1.15} 0.015 (0.381) 0.095 (2.42) LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH LEADS ARE SOLDER PLATED KOVAR MODIFIED SCALE FACTOR AND OFFSET 16 PIN CERAMIC DIP 0.3 (7.62) Veer 0.28 (7.12) 9 + +1BV 3 ~ f R19 Oo + Vout ree ao oe 0.81 {20.58} 0.12 {3.05} 0.06 (1.53) MSB \ sitio, 1 4 16 | piciTaAL | 1 PN vy 2 R2 0.77 (19.56) INPUT | AD7533 > r -VR=FD L _ oN + _ 0.17 (4.32) MAX j O17 (4.45) | o.o12 (0.208) |" 0.008 (0.203) mevr | ! isp 2 BIT 10 Gage] 3 / R: RiD } - Your = Vrer [Ca 2%e,)- | is 78 Was 25 (3.18) a i tk; where: lo. | |e, 0.06 (1.53) 0.02 (0.508) 0.105 (2.67) 0.306 (7.78) 0.15 (0.381) 0.095 (2.42) 02 294 (7.47) 0.045 (1.15} LEAD NO. 1 IDENTIFIED BY DOT OAR NOTCH BIT] , BIT2 , BIT10 i 210 LEADS ARE GOLD-PLATED (50 MICROINCHES MIN.) KOVAR BONDING DIAGRAM Dimensions shown in inches and (mm). BIT 1 (MEB) GND _ BIT 3 BIT 2 BIT 4] OuT2 BIT 5 0.068(1.73) BIT 6 Rep VnerF BIT 7 10 1 AD7533 a a BIT 10 Vo (LSB) BIT 8 BIT 9 0,067(1.70) 332 D/A CONVERTERS