CD40174BCJ - National Semiconductor

TL/F/5987

CD40174BM/CD40174BC Hex D Flip-Flop

CD40175BM/CD40175BC Quad D Flip-Flop

February 1988

CD40174BM/CD40174BC Hex D Flip-Flop

CD40175BM/CD40175BC Quad D Flip-Flop

General Description

The CD40174B consists of six positive-edge triggered

D-type flip-flops; the true outputs from each flip-flop are ex-

ternally available. The CD40175B consists of four positive-

edge triggered D-type flip-flops; both the true and comple-

ment outputs from each flip-flop are externally available.

All flip-flops are controlled by a common clock and a com-

mon clear. Information at the D inputs meeting the set-up

time requirements is transferred to the Q outputs on the

positive-going edge of the clock pulse. The clearing opera-

tion, enabled by a negative pulse at Clear input, clears all Q

outputs to logical ‘‘0’’ and Qs (CD40175B only) to logical ‘‘1’’.

All inputs are protected from static discharge by diode

clamps to VDD and VSS.

Features

YWide supply voltage range 3V to 15V

YHigh noise immunity 0.45 VDD (typ.)

YLow power TTL fan out of 2 driving 74L

compatibility or 1 driving 74 LS

YEquivalent to MC14174B, MC14175B

YEquivalent to MM74C174, MM74C175

Connection Diagrams

CD40174B

Dual-In-Line Package

TL/F/5987–1

Top View

Order Number CD40174B or CD40175B

Truth Table

Inputs Outputs

Clear Clock D Q Q*

LXXLH

HH L

LL H

HHXNCNC

HLXNCNC

High level

LeLow level

XeIrrelevant

eTransition from low to high level

NC eNo change

*eQ for CD40175B only

CD40175B

Dual-In-Line Package

TL/F/5987–2

Top View

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Notes1&2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

DC Supply Voltage (VDD)b0.5V to a18V

Input Voltage (VIN)b0.5V to VDD a0.5VDC

Storage Temperature Range (TS)b65§Ctoa

150§C

Power Dissipation (PD)

Dual-In-Line 700 mW

Small Outline 500 mW

Lead Temperature (TL)

(Soldering, 10 seconds) 260§C

Recommended Operating

Conditions (Note 2)

DC Supply Voltage (VDD) 3Vto15V

Input Voltage (VIN) 0VtoV

DD VDC

Operating Temperature Range (TA)

CD40XXXBM b55§Ctoa

125§C

CD40XXXBC b40§Ctoa

85§C

DC Electrical Characteristics CD40174BM/CD40175BM (Note 2)

Symbol Parameter Conditions b55§Ca25§Ca125§CUnits

Min Max Min Typ Max Min Max

IDD Quiescent Device Current VDD e5V, VIN eVDD or VSS 1.0 1.0 30 mA

VDD e10V, VIN eVDD or VSS 2.0 2.0 60 mA

VDD e15V, VIN eVDD or VSS 4.0 4.0 120 mA

VOL Low Level Output Voltage

k1mA

VDD e5V 0.05 0.05 0.05 V

VDD e10V 0.05 0.05 0.05 V

VDD e15V 0.05 0.05 0.05 V

VOH High Level Output Voltage

k1mA

VDD e5V 4.95 4.95 5 4.95 V

VDD e10V 9.95 9.95 10 9.95 V

VDD e15V 14.95 14.95 15 14.95 V

VIL Low Level Input Voltage VDD e5V, VOe0.5V or 4.5V 1.5 1.5 1.5 V

VDD e10V, VOe1V or 9V 3.0 3.0 3.0 V

VDD e15V, VOe1.5V or 13.5V 4.0 4.0 4.0 V

VIH High Level Input Voltage VDD e5V, VOe0.5V or 4.5V 3.5 3.5 3.5 V

VDD e10V, VOe1V or 9V 7.0 7.0 7.0 V

VDD e15V, VOe1.5V or 13.5V 11.0 11.0 11.0 V

IOL Low Level Output Current VDD e5V, VOe0.4V 0.64 0.51 0.88 0.36 mA

(Note 3) VDD e10V, VOe0.5V 1.6 1.3 2.25 0.9 mA

VDD e15V, VOe1.5V 4.2 3.4 8.8 2.4 mA

IOH High Level Output Current VDD e5V, VOe4.6V b0.64 b0.51 b0.8.8 b0.36 mA

(Note 3) VDD e10V, VOe9.5V b1.6 b1.3 b2.25 b0.9 mA

VDD e15V, VOe13.5V b4.2 b3.4 b8.8 b2.4 mA

IIN Input Current VDD e15V, VIN e0V b0.1 b10b5b0.1 b1.0 mA

VDD e15V, VIN e15V 0.1 10b50.1 1.0 mA

DC Electrical Characteristics CD40174BC/CD40175BC (Note 2)

Symbol Parameter Conditions b40§Ca25§Ca85§CUnits

Min Max Min Typ Max Min Max

IDD Quiescent Device Current VDD e5V, VIN eVDD or VSS 4430mA

DD e10V, VIN eVDD or VSS 8860mA

DD e15V, VIN eVDD or VSS 16 16 120 mA

Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices

should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual device

operation.

Note 2: VSS e0V unless otherwise specified.

Note 3: IOH and IOL are tested one output at a time.

DC Electrical Characteristics CD40174BC/CD40175BC (Note 2) (Continued)

Symbol Parameter Conditions b40§Ca25§Ca85§CUnits

Min Max Min Typ Max Min Max

VOL Low Level Output Voltage VDD e5V 0.05 0.05 0.05 V

VDD e10V 0.05 0.05 0.05 V

VDD e15V 0.05 0.05 0.05 V

VOH High Level Output Voltage VDD e5V 4.95 4.95 5 4.95 V

VDD e10V 9.95 9.95 10 9.95 V

VDD e15V 14.95 14.95 15 14.95 V

VIL Low Level Input Voltage VDD e5V, VOe0.5V or 4.5V 1.5 1.5 1.5 V

VDD e10V, VOe1V or 9V 3.0 3.0 3.0 V

VDD e15V, VOe1.5V or 13.5V 4.0 4.0 4.0 V

VIH High Level Input Voltage VDD e5V, VOe0.5V or 4.5V 3.5 3.5 3.5 V

VDD e10V, VOe1V or 9V 7.0 7.0 7.0 V

VDD e15V, VOe1.5V or 13.5V 11.0 11.0 11.0 V

IOL Low Level Output Current VDD e5V, VOe0.4V 0.52 0.44 0.88 0.36 mA

(Note 3) VDD e10V, VOe0.5V 1.3 1.1 2.25 0.9 mA

VDD e15V, VOe1.5V 3.6 3.0 8.8 2.4 mA

IOH High Level Output Current VDD e5V, VOe4.6V b0.52 b0.44 b0.88 b0.36 mA

(Note 3) VDD e10V, VOe9.5V b1.3 b1.1 b2.25 b0.9 mA

VDD e15V, VOe13.5V b3.6 b3.0 b8.8 b2.4 mA

IIN Input Current VDD e15V, VIN e0V b0.30 b10b5b0.30 b1.0 mA

VDD e15V, VIN e15V 0.30 10b50.30 1.0 mA

AC Electrical Characteristics*

TAe25§C, CLe50 pF, RLe200k and tretfe20 ns, unless otherwise specified

Symbol Parameter Conditions Min Typ Max Units

tPHL,t

PLH Propagation Delay Time to a VDD e5V 190 300 ns

Logical ‘‘0’’ or Logical ‘‘1’’ from VDD e10V 75 110 ns

Clock to Q or Q (CD40175 Only) VDD e15V 60 90 ns

tPHL Propagation Delay Time to a VDD e5V 180 300 ns

Logical ‘‘0’’ from Clear to Q VDD e10V 70 110 ns

VDD e15V 60 90 ns

tPLH Propagation Delay Time to a Logical VDD e5V 230 400 ns

‘‘1’’ from Clear to Q (CD40175 Only) VDD e10V 90 150 ns

VDD e15V 75 120 ns

tSU Time Prior to Clock Pulse that VDD e5V 45 100 ns

Data must be Present VDD e10V 15 40 ns

VDD e15V 13 35 ns

tHTime after Clock Pulse that VDD e5V b11 0 ns

Data Must be Held VDD e10V b40 ns

DD e15V b30 ns

THL,t

TLH Transition Time VDD e5V 100 200 ns

VDD e10V 50 100 ns

VDD e15V 40 80 ns

tWH,t

WL Minimum Clock Pulse Width VDD e5V 130 250 ns

VDD e10V 45 100 ns

VDD e15V 40 80 ns

AC Electrical Characteristics*

TAe25§C, CLe50 pF, RLe200k and tretfe20 ns, unless otherwise specified (Continued)

Symbol Parameter Conditions Min Typ Max Units

tWL Minimum Clear Pulse Width VDD e5V 120 250 ns

VDD e10V 45 100 ns

VDD e15V 40 80 ns

tRCL Maximum Clock Rise Time VDD e5V 15 ms

VDD e10V 5.0 ms

VDD e15V 5.0 ms

tfCL Maximum Clock Fall Time VDD e5V 15 50 ms

VDD e10V 5.0 50 ms

VDD e15V 5.0 50 ms

fCL Maximum Clock Frequency VDD e5V 2.0 3.5 MHz

VDD e10V 5.0 10 MHz

VDD e15V 6.0 12 MHz

CIN Input Capacitance Clear Input 10 15 pF

Other Input 5.0 7.5 pF

CPD Power Dissipation Per Package (Note 4) 130 pF

*AC Parameters are guaranteed by DC correlated testing.

Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the

devices should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual

device operation.

Note 2: VSS e0V unless otherwise specified.

Note 3: IOH and IOL are tested one output at a time.

Note 4: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see 54C/74C Family Characteristics application

note, AN-90.

Switching Time Waveforms

TL/F/5987–3

tretfe20 ns

Physical Dimensions inches (millimeters)

Ceramic Dual-In-Line Package (J)

Order Number CD40174BMJ, CD40174BCJ, CD40175BMJ or CD40175BCJ

NS Package Number J16A

CD40174BM/CD40174BC Hex D Flip-Flop

CD40175BM/CD40175BC Quad D Flip-Flop

Physical Dimensions inches (millimeters) (Continued)

Molded Dual-In-Line Package (N)

Order Number CD40174BMN, CD40174BCN, CD40174BMN or CD40175BCN

NS Package Number N16E

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SEMICONDUCTOR CORPORATION. As used herein:

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into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life

failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

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