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LM139JAN Low Power Low Offset Voltage Quad Comparators
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1FEATURES DESCRIPTION
The LM139 consists of four independent precision
2• Wide Supply Voltage Range 5V to 36 VDCor voltage comparators with an offset voltage
±2.5V to ±18 VDC specification as low as 2 mV max for all four
• Very Low Supply Current Drain (0.8 mA) - comparators. These were designed specifically to
Independent of Supply Voltage operate from a single power supply over a wide range
of voltages. Operation from split power supplies is
• Low Input Biasing Current: 25 nA also possible and the low power supply current drain
• Low Input Offset Current: ±5 nA is independent of the magnitude of the power supply
• Offset Voltage: ±3 mV voltage. These comparators also have a unique
• Input Common-Mode Voltage Range Includes characteristic in that the input common-mode voltage
range includes ground, even though operated from a
GND single power supply voltage.
• Differential Input Voltage Range Equal to the
Power Supply Voltage Application areas include limit comparators, simple
analog to digital converters; pulse, squarewave and
• Low Output Saturation Voltage: 250 mV at 4 time delay generators; wide range VCO; MOS clock
mA timers; multivibrators and high voltage digital logic
• Output Voltage Compatible with TTL, DTL, gates. The LM139 was designed to directly interface
ECL, MOS and CMOS Logic Systems with TTL and CMOS. When operated from both plus
and minus power supplies, they will directly interface
ADVANTAGES with MOS logic— where the low power drain of the
LM139 is a distinct advantage over standard
• High Precision Comparators comparators.
• Reduced VOS Drift Over Temperature
• Eliminates Need for Dual Supplies
• Allows Sensing Near GND
• Compatible with All Forms of Logic
• Power Drain Suitable for Battery Operation
Connection Diagrams
Figure 1. See Package Number NAD0014B
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2005–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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Schematic Diagram
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings(1)
Supply Voltage, V+(2) 36 VDC or ±18 VDC
Differential Input Voltage(3) 36 VDC
Output Voltage 36 VDC
Input Voltage −0.3 VDC to +36 VDC
Input Current (VIN <−0.3 VDC)(4)(5) 50 mA
Power Dissipation(6)(7) CLGA 350 mW @ TA= 125°C
Output Short-Circuit to GND,(8) Continuous
Storage Temperature Range −65°C ≤TA≤+150°C
Maximum Junction Temperature (TJ) +175°C
Lead Temperature (Soldering, 10 seconds) 260°C
Operating Temperature Range −55°C ≤TA≤+125°C
Thermal Resistance θJA CLGA (Still Air) 183°C/W
CLGA (500LF / Min Air flow) 120°C/W
θJC CLGA 23°C/W
Package Weight (typical) CLGA 460mg
ESD rating(9) 600V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see, the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) Short circuits from the output to V+can cause excessive heating and eventual destruction. When considering short circuits to ground,
the maximum output current is approximately 20mA independent of the magnitude of V+
(3) Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode
range, the comparator will provide a proper output state. The low input voltage state must not be less than −0.3 VDC (or 0.3 VDCbelow
the magnitude of the negative power supply, if used) (at 25°C).
(4) This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of
the input PNP transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is
also lateral NPN parasitic transistor action on the IC chip. This transistor action can cause the output voltages of the comparators to go
to the V+voltage level (or to ground for a large overdrive) for the time duration that an input is driven negative. This is not destructive
and normal output states will re-establish when the input voltage, which was negative, again returns to a value greater than −0.3 VDC (at
25°)C.
(5) The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the
state of the output so no loading change exists on the reference or input lines.
(6) The low bias dissipation and the ON-OFF characteristics of the outputs keeps the chip dissipation very small (PD≤100mW), provided
the output transistors are allowed to saturate.
(7) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature),
θJA (Package junction to ambient thermal resistance), and TA(ambient temperature). The maximum allowable power dissipation at any
temperature is PDmax = (TJmax — TA) / θJA or the number given in the Absolute Maximum Ratings, whichever is lower.
(8) Short circuits from the output to V+can cause excessive heating and eventual destruction. When considering short circuits to ground,
the maximum output current is approximately 20 mA independent of the magnitude of V+.
(9) Human Body model, 1.5 KΩin series with 100 pF
Quality Conformance Inspection
Mil-Std-883, Method 5005 - Group A
Subgroup Description Temp (°C)
1 Static tests at +25
2 Static tests at +125
3 Static tests at -55
4 Dynamic tests at +25
5 Dynamic tests at +125
6 Dynamic tests at -55
7 Functional tests at +25
8A Functional tests at +125
8B Functional tests at -55
9 Switching tests at +25
10 Switching tests at +125
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Quality Conformance Inspection (continued)
Mil-Std-883, Method 5005 - Group A
Subgroup Description Temp (°C)
11 Switching tests at -55
LM139 JAN Electrical Characteristics DC Parameters
The following conditions apply, unless otherwise specified. −VCC = 0V Sub-
Symbol Parameters Conditions Notes Min Max Unit groups
VIO Input Offset Voltage +VCC = 30V, VO= 15V -5.0 5.0 mV 1
-7.0 7.0 mV 2, 3
+VCC = 2V, -VCC = -28V, -5.0 5.0 mV 1
VO= -13V -7.0 7.0 mV 2, 3
+VCC = 5V, VO= 1.4V -5.0 5.0 mV 1
-7.0 7.0 mV 2, 3
+VCC = 2V, -VCC = -3V, -5.0 5.0 mV 1
VO= -1.6V -7.0 7.0 mV 2, 3
IIO Input Offset Current +VCC = 30V, RS= 20KΩ, See(1) -25 25 nA 1, 2
VO= 15V See(1) -75 75 nA 3
+VCC = 2V, -VCC = -28V, See(1) -25 25 nA 1, 2
RS= 20KΩ, VO= -13V See(1) -75 75 nA 3
+VCC = 5V, RS= 20KΩ, See(1) -25 25 nA 1, 2
VO= 1.4V See(1) -75 75 nA 3
+VCC = 2V, -VCC = -3V, See(1) -25 25 nA 1, 2
RS= 20KΩ, VO= -1.6V See(1) -75 75 nA 3
±IIB Input Bias Current +VCC = 30V, RS= 20KΩ, See(1) -100 +0.1 nA 1, 2
VO= 15V See(1) -200 +0.1 nA 3
+VCC = 2V, -VCC = -28V, See(1) -100 +0.1 nA 1, 2
RS= 20KΩ, VO= -13V See(1) -200 +0.1 nA 3
+VCC = 5V, RS= 20KΩ, See(1) -100 +0.1 nA 1, 2
VO= 1.4V See(1) -200 +0.1 nA 3
+VCC = 2V, -VCC = -3V, See(1) -100 +0.1 nA 1, 2
RS= 20KΩ, VO= -1.6V See(1) -200 +0.1 nA 3
CMRR Input Voltage Common Mode +VCC = 30V 76 dB 1, 2, 3
Rejection +VCC = 5V 70 dB 1, 2, 3
ICEX Output Leakage +VCC = 30V, VO= +30V 1.0 µA 1, 2, 3
+IIL Input Leakage Current +VCC = 36V, V + i = 34V, -500 500 nA 1, 2, 3
V−i = 0V
-IIL Input Leakage Current +VCC = 36V, V + i = 0V, -500 500 nA 1, 2, 3
V−i = 34V
VOL Logical "0" Output Voltage +VCC = 4.5V, IO= 4mA 0.4 V 1
0.7 V 2, 3
+VCC = 4.5V, IO= 8mA 1.5 V 1
2.0 V 2, 3
ICC Power Supply Current +VCC = 5V, VID = 15mV 2.0 mA 1, 2
3.0 mA 3
+VCC = 30V, VID = 15mV 3.0 mA 1, 2
4.0 mA 3
(1) S/S RS= 20KΩ, tested at RS= 10KΩas equivalent test.
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LM139 JAN Electrical Characteristics DC Parameters (continued)
The following conditions apply, unless otherwise specified. −VCC = 0V Sub-
Symbol Parameters Conditions Notes Min Max Unit groups
ΔVIO /ΔT Temperature Coefficient of Input 25°C ≤TA≤125°C See(2) -25 25 µV/°C 2
Offset Voltage -55°C ≤TA≤25°C See(2) -25 25 µV/°C 3
ΔIIO /ΔT Temperature Coefficient of Input 25°C ≤TA≤125°C See(2) -300 300 pA/°C 2
Offset Current -55°C ≤TA≤25°C See(2) -400 400 pA/°C 3
AVS Open Loop Voltage Gain +VCC = 15V, RL=15KΩ, See(3) 50 V/mV 4
1V ≤VO≤11V See(3) 25 V/mV 5, 6
VIO Tempco Screen 4.0 mV
CMRR Tempco Screen 70 dB
IIO Tempco Screen 13 nA
IIB Tempco Screen 12 nA
(2) Calculated parameter; for Delta VIO / Delta T use VIO test at +VCC = 30V, −VCC = 0V, VO= 15V; and for Delta IIO / Delta T use IIB test at
+VCC = 30V, −VCC = 0V, VO= 15V
(3) Datalog of K = V/mV.
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LM139 JAN Electrical Characteristics AC Parameters Sub-
Symbol Parameters Conditions Notes Min Max Unit groups
tRLH Response Time: Low-to-High +VCC = 5V, VI= 100mV, 5.0 µS 7, 8B
RL= 5.1KΩ, VOD = 5mV 7.0 µS 8A
+VCC = 5V, VI= 100mV, 0.8 µS 7, 8B
RL= 5.1KΩ, VOD = 50mV 1.2 µS 8A
tRHL Response Time: High-to-Low +VCC = 5V, VI= 100mV, 2.5 µS 7, 8B
RL= 5.1KΩ, VOD = 5mV 3.0 µS 8A
+VCC = 5V, VI= 100mV, 0.8 µS 7, 8B
RL= 5.1KΩ, VOD = 50mV 1.0 µS 8A
CSChannel Separation +VCC = 20V, -VCC = -10V, 80 dB 7
A to B
+VCC = 20V, -VCC = -10V, 80 dB 7
A to C
+VCC = 20V, -VCC = -10V, 80 dB 7
A to D
+VCC = 20V, -VCC = -10V, 80 dB 7
B to A
+VCC = 20V, -VCC = -10V, 80 dB 7
B to C
+VCC = 20V, -VCC = -10V, 80 dB 7
B to D
+VCC = 20V, -VCC = -10V, 80 dB 7
C to A
+VCC = 20V, -VCC = -10V, 80 dB 7
C to B
+VCC = 20V, -VCC = -10V, 80 dB 7
C to D
+VCC = 20V, -VCC = -10V, 80 dB 7
D to A
+VCC = 20V, -VCC = -10V, 80 dB 7
D to B
+VCC = 20V, -VCC = -10V, 80 dB 7
D to C
VLAT Voltage Latch (Logical "1" Input) +VCC = 5V, VI= 10V, 0.4 V 9
IO= 4mA
LM139 JAN Electrical Characteristics DC Parameters Drift Values
The following conditions apply, unless otherwise specified. −VCC = 0V
Delta calculations performed on JAN S product at Group B, Subgroup 5. Sub-
Symbol Parameters Conditions Notes Min Max Unit groups
VIO Input Offset Voltage VCC = 30V,VO= 15V -1.0 1.0 mV 1
±IBias Input Bias Current VCC = 30V,RS= 20KΩ,-15 15 nA 1
VO= 15V
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Typical Performance Characteristics
Supply Current Input Current
Figure 2. Figure 3.
Response Time for Various Input Overdrives
Output Saturation Voltage —Negative Transition
Figure 4. Figure 5.
Response Time for Various Input Overdrives
—Positive Transition
Figure 6.
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APPLICATION HINTS
The LM139 is a high gain, wide bandwidth device which, like most comparators, can easily oscillate if the output
lead is inadvertently allowed to capacitively couple to the inputs via stray capacitance. This shows up only during
the output voltage transition intervals as the comparator changes states. Power supply bypassing is not required
to solve this problem. Standard PC board layout is helpful as it reduces stray input-output coupling. Reducing the
input resistors to < 10 kΩreduces the feedback signal levels and finally, adding even a small amount (1 to 10
mV) of positive feedback (hysteresis) causes such a rapid transition that oscillations due to stray feedback are
not possible. Simply socketing the IC and attaching resistors to the pins will cause input-output oscillations during
the small transition intervals unless hysteresis is used. If the input signal is a pulse waveform, with relatively fast
rise and fall times, hysteresis is not required.
All pins of any unused comparators should be tied to the negative supply.
The bias network of the LM139 establishes a drain current which is independent of the magnitude of the power
supply voltage over the range of from 5 VDC to 30 VDC.
It is usually unnecessary to use a bypass capacitor across the power supply line.
The differential input voltage may be larger than V+without damaging the device. Protection should be provided
to prevent the input voltages from going negative more than −0.3 VDC (at 25°C). An input clamp diode can be
used as shown in the applications section.
The output of the LM139 is the uncommitted collector of a grounded-emitter NPN output transistor. Many
collectors can be tied together to provide an output OR'ing function. An output pull-up resistor can be connected
to any available power supply voltage within the permitted supply voltage range and there is no restriction on this
voltage due to the magnitude of the voltage which is applied to the V+terminal of the LM139 package. The
output can also be used as a simple SPST switch to ground (when a pull-up resistor is not used). The amount of
current which the output device can sink is limited by the drive available (which is independent of V+) and the β
of this device. When the maximum current limit is reached (approximately 16 mA), the output transistor will come
out of saturation and the output voltage will rise very rapidly. The output saturation voltage is limited by the
approximately 60ΩRSAT of the output transistor. The low offset voltage of the output transistor (1 mV) allows the
output to clamp essentially to ground level for small load currents.
Typical Applications
(V+= 5.0 VDC)
Figure 7. Basic Comparator
Figure 8. Driving CMOS
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Figure 18. Time Delay Generator
Figure 19. Non-Inverting Comparator with Figure 20. Inverting Comparator with Hysteresis
Hysteresis
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Figure 21. Squarewave Oscillator Figure 22. Basic Comparator
Figure 23. Limit Comparator Figure 24. Comparing Input Voltages of Opposite
Polarity
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* Or open-collector logic gate without pull-up resistor
Figure 25. Output Strobing Figure 26. Crystal Controlled Oscillator
Figure 27. Transducer Amplifier Figure 28. Zero Crossing Detector (Single Power
Supply)
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Split-Supply Applications
(V+= +15 VDC and V−=−15 VDC)
Figure 30. MOS Clock Driver
Figure 31. Zero Crossing Detector Figure 32. Comparator With a Negative Reference
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REVISION HISTORY
Date Released Revision Section Changes
02/15/05 A New Release to corporate format 1 MDS datasheet converted into Corp. datasheet
format. MJLM139-X rev 0D0. MDS datasheet will be
archived.
10/26/2010 B Order Information, Connection Diagrams, Update with current device information and format.
Absolute Ratings, Physical Dimensions Deleted J and WG pkg references. Revision A will be
drawings, Archived
03/20/2013 B All Changed layout of National Data Sheet to TI format
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
JL139BDA ACTIVE CFP NAD 14 19 TBD Call TI Call TI -55 to 125 JL139BDA Q
JM38510/
11201BDA ACO
11201BDA >T
JM38510/11201BDA ACTIVE CFP NAD 14 19 TBD Call TI Call TI -55 to 125 JL139BDA Q
JM38510/
11201BDA ACO
11201BDA >T
M38510/11201BDA ACTIVE CFP NAD 14 19 TBD Call TI Call TI -55 to 125 JL139BDA Q
JM38510/
11201BDA ACO
11201BDA >T
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM139JAN, LM139JAN-SP :
•Military: LM139JAN
•Space: LM139JAN-SP
NOTE: Qualified Version Definitions:
•Military - QML certified for Military and Defense Applications
•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
MECHANICAL DATA
NAD0014B
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W14B (Rev P)
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