LMC660AIM/NOPB - NATIONAL SEMICONDUCTOR

LMC660

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LMC660 CMOS Quad Operational Amplifier

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1FEATURES DESCRIPTION

The LMC660 CMOS Quad operational amplifier is

2• Rail-to-Rail Output Swing ideal for operation from a single supply. It operates

• Specified for 2 kΩand 600ΩLoads from +5V to +15.5V and features rail-to-rail output

• High Voltage Gain: 126 dB swing in addition to an input common-mode range

that includes ground. Performance limitations that

• Low Input Offset Voltage: 3 mV have plagued CMOS amplifiers in the past are not a

• Low Offset Voltage Drift: 1.3 μV/°C problem with this design. Input VOS, drift, and

• Ultra Low Input Bias Current: 2 fA broadband noise as well as voltage gain into realistic

loads (2 kΩand 600Ω) are all equal to or better than

• Input Common-Mode Range Includes V−

widely accepted bipolar equivalents.

• Operating Range from +5V to +15.5V Supply This chip is built with TI's advanced Double-Poly

• ISS = 375 μA/Amplifier; Independent of V+Silicon-Gate CMOS process.

• Low Distortion: 0.01% at 10 kHz See the LMC662 datasheet for a dual CMOS

• Slew Rate: 1.1 V/μsoperational amplifier with these same features.

APPLICATIONS

• High-Impedance Buffer or Preamplifier

• Precision Current-to-Voltage Converter

• Long-Term Integrator

• Sample-and-Hold Circuit

• Peak Detector

• Medical Instrumentation

• Industrial Controls

• Automotive Sensors

Connection Diagrams

Figure 1. 14-Pin SOIC/PDIP Figure 2. LMC660 Circuit Topology (Each

Amplifier)

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LMC660

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings(1)

Differential Input Voltage ±Supply Voltage

Supply Voltage 16V

Output Short Circuit to V+See(2)

Output Short Circuit to V−See(3)

Lead Temperature (Soldering, 10 sec.) 260°C

Storage Temp. Range −65°C to +150°C

Voltage at Input/Output Pins (V+) + 0.3V, (V−)−0.3V

Current at Output Pin ±18 mA

Current at Input Pin ±5 mA

Current at Power Supply Pin 35 mA

Power Dissipation See(4)

Junction Temperature 150°C

ESD tolerance(5) 1000V

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test

conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.

(2) Do not connect output to V+when V+is greater than 13V or reliability may be adversely affected.

(3) Applies to both single supply and split supply operation. Continuous short circuit operation at elevated ambient temperature and/or

multiple Op Amp shorts can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30

mA over long term may adversely affect reliability.

(4) The maximum power dissipation is a function of TJ(MAX),θJA, and TA. The maximum allowable power dissipation at any ambient

temperature is PD= (TJ(MAX) −TA)/θJA.

(5) Human Body Model is 1.5 kΩin series with 100 pF.

Operating Ratings

Temperature Range

LMC660AI −40°C ≤TJ≤+85°C

LMC660C 0°C ≤TJ≤+70°C

Supply Voltage Range 4.75V to 15.5V

Power Dissipation See(1)

Thermal Resistance (θJA)(2)

14-Pin SOIC 115°C/W

14-Pin PDIP 85°C/W

(1) For operating at elevated temperatures the device must be derated based on the thermal resistance θJA with PD= (TJ−TA)/θJA.

(2) All numbers apply for packages soldered directly into a PC board.

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DC Electrical Characteristics

Unless otherwise specified, all limits ensured for TJ= 25°C. Boldface limits apply at the temperature extremes. V+= 5V, V−=

0V, VCM = 1.5V, VO= 2.5V and RL> 1MΩunless otherwise specified. LMC660AI LMC660C

Parameter Test Conditions Typ(1) Units

Limit(1) Limit(1)

Input Offset Voltage 1 3 6 mV

3.3 6.3 max

Input Offset Voltage Average Drift 1.3 μV/°C

Input Bias Current 0.002 pA

4 2 max

Input Offset Current 0.001 pA

2 1 max

Input Resistance >1 TeraΩ

Common Mode 0V ≤VCM ≤12.0V 83 70 63 dB

Rejection Ratio V+= 15V 68 62 min

Positive Power Supply 5V ≤V+≤15V 83 70 63 dB

Rejection Ratio VO= 2.5V 68 62 min

Negative Power Supply 0V ≤V−≤ −10V 94 84 74 dB

Rejection Ratio 83 73 min

Input Common-Mode V+= 5V & 15V −0.4 −0.1 −0.1 V

Voltage Range For CMRR ≥50 dB 0 0 max

V+−1.9 V+−2.3 V+−2.3 V

V+−2.5 V+−2.4 min

Large Signal RL= 2 kΩ(2) 2000 440 300 V/mV

Voltage Gain Sourcing 400 200 min

Sinking 500 180 90 V/mV

120 80 min

RL= 600Ω(2) 1000 220 150 V/mV

Sourcing 200 100 min

Sinking 250 100 50 V/mV

60 40 min

Output Swing V+= 5V 4.87 4.82 4.78 V

RL= 2 kΩto V+/2 4.79 4.76 min

0.10 0.15 0.19 V

0.17 0.21 max

V+= 5V 4.61 4.41 4.27 V

RL= 600Ωto V+/2 4.31 4.21 min

0.30 0.50 0.63 V

0.56 0.69 max

V+= 15V 14.63 14.50 14.37 V

RL= 2 kΩto V+/2 14.44 14.32 min

0.26 0.35 0.44 V

0.40 0.48 max

V+= 15V 13.90 13.35 12.92 V

RL= 600Ωto V+/2 13.15 12.76 min

0.79 1.16 1.45 V

1.32 1.58 max

(1) Typical values represent the most likely parametric norm. Limits are specified by testing or correlation.

(2) V+= 15V, VCM = 7.5V and RLconnected to 7.5V. For Sourcing tests, 7.5V ≤VO≤11.5V. For Sinking tests, 2.5V ≤VO≤7.5V.

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DC Electrical Characteristics (continued)

Unless otherwise specified, all limits ensured for TJ= 25°C. Boldface limits apply at the temperature extremes. V+= 5V, V−=

0V, VCM = 1.5V, VO= 2.5V and RL> 1MΩunless otherwise specified. LMC660AI LMC660C

Parameter Test Conditions Typ(1) Units

Limit(1) Limit(1)

Output Current Sourcing, VO= 0V 22 16 13 mA

V+= 5V 14 11 min

Sinking, VO= 5V 21 16 13 mA

14 11 min

Output Current Sourcing, VO= 0V 40 28 23 mA

V+= 15V 25 21 min

Sinking, VO= 13V(3) 39 28 23 mA

24 20 min

Supply Current All Four Amplifiers 1.5 2.2 2.7 mA

VO= 1.5V 2.6 2.9 max

(3) Do not connect output to V+when V+is greater than 13V or reliability may be adversely affected.

AC Electrical Characteristics

Unless otherwise specified, all limits ensured for TJ= 25°C. Boldface limits apply at the temperature extremes. V+= 5V, V−=

0V, VCM = 1.5V, VO= 2.5V and RL> 1MΩunless otherwise specified. LMC660AI LMC660C

Parameter Test Conditions Typ(1) Units

Limit(1) Limit(1)

Slew Rate See(2) 1.1 0.8 0.8 V/μs

0.6 0.7 min

Gain-Bandwidth Product 1.4 MHz

Phase Margin 50 Deg

Gain Margin 17 dB

Amp-to-Amp Isolation See(3) 130 dB

Input Referred Voltage Noise F = 1 kHz 22 nV/√Hz

Input Referred Current Noise f = 1 kHz 0.0002 pA//√Hz

Total Harmonic Distortion f = 10 kHz, AV=−10 0.01 %

RL= 2 kΩ, VO= 8 VPP

V+= 15V

(1) Typical values represent the most likely parametric norm. Limits are specified by testing or correlation.

(2) V+= 15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of the positive and negative slew rates.

(3) Input referred. V+= 15V and RL= 10 kΩconnected to V+/2. Each amp excited in turn with 1 kHz to produce VO= 13 VPP.

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Typical Performance Characteristics

VS= ±7.5V, TA= 25°C unless otherwise specified.

Supply Current

vs.

Supply Voltage Offset Voltage

Figure 3. Figure 4.

Input Bias Current Output Characteristics Current Sinking

Figure 5. Figure 6.

Input Voltage Noise

vs.

Output Characteristics Current Sourcing Frequency

Figure 7. Figure 8.

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Typical Performance Characteristics (continued)

VS= ±7.5V, TA= 25°C unless otherwise specified.

CMRR

vs.

Frequency Open-Loop Frequency Response

Figure 9. Figure 10.

Frequency Response

vs.

Capacitive Load Non-Inverting Large Signal Pulse Response

Figure 11. Figure 12.

Stability Stability

vs. vs.

Capacitive Load Capacitive Load

Figure 13. Figure 14.

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APPLICATION INFORMATION

AMPLIFIER TOPOLOGY

The topology chosen for the LMC660, shown in Figure 15, is unconventional (compared to general-purpose op

amps) in that the traditional unity-gain buffer output stage is not used; instead, the output is taken directly from

the output of the integrator, to allow rail-to-rail output swing. Since the buffer traditionally delivers the power to

the load, while maintaining high op amp gain and stability, and must withstand shorts to either rail, these tasks

now fall to the integrator.

As a result of these demands, the integrator is a compound affair with an embedded gain stage that is doubly fed

forward (via Cfand Cff) by a dedicated unity-gain compensation driver. In addition, the output portion of the

integrator is a push-pull configuration for delivering heavy loads. While sinking current the whole amplifier path

consists of three gain stages with one stage fed forward, whereas while sourcing the path contains four gain

stages with two fed forward.

Figure 15. LMC660 Circuit Topology (Each Amplifier)

The large signal voltage gain while sourcing is comparable to traditional bipolar op amps, even with a 600Ωload.

The gain while sinking is higher than most CMOS op amps, due to the additional gain stage; however, under

heavy load (600Ω) the gain will be reduced as indicated in DC Electrical Characteristics. Avoid resistive loads of

less than 500Ω, as they may cause instability.

COMPENSATING INPUT CAPACITANCE

The high input resistance of the LMC660 op amps allows the use of large feedback and source resistor values

without losing gain accuracy due to loading. However, the circuit will be especially sensitive to its layout when

these large-value resistors are used.

Every amplifier has some capacitance between each input and AC ground, and also some differential

capacitance between the inputs. When the feedback network around an amplifier is resistive, this input

capacitance (along with any additional capacitance due to circuit board traces, the socket, etc.) and the feedback

resistors create a pole in the feedback path. In the following General Operational Amplifier circuit, Figure 16 the

frequency of this pole is:

(1)

where CSis the total capacitance at the inverting input, including amplifier input capacitance and any stray

capacitance from the IC socket (if one is used), circuit board traces, etc., and RPis the parallel combination of RF

and RIN. This formula, as well as all formulae derived below, apply to inverting and non-inverting op amp

configurations.

When the feedback resistors are smaller than a few kΩ, the frequency of the feedback pole will be quite high,

since CSis generally less than 10 pF. If the frequency of the feedback pole is much higher than the “ideal”

closed-loop bandwidth (the nominal closed-loop bandwidth in the absence of CS), the pole will have a negligible

effect on stability, as it will add only a small amount of phase shift.

However, if the feedback pole is less than approximately 6 to 10 times the “ideal” −3 dB frequency, a feedback

capacitor, CF, should be connected between the output and the inverting input of the op amp. This condition can

also be stated in terms of the amplifier's low-frequency noise gain: To maintain stability a feedback capacitor will

probably be needed if:

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(2)

where:

(3)

is the amplifier's low-frequency noise gain and GBW is the amplifier's gain bandwidth product. An amplifier's low-

frequency noise gain is represented by the formula:

(4)

regardless of whether the amplifier is being used in inverting or non-inverting mode. Note that a feedback

capacitor is more likely to be needed when the noise gain is low and/or the feedback resistor is large.

If the above condition is met (indicating a feedback capacitor will probably be needed), and the noise gain is

large enough that:

(5)

the following value of feedback capacitor is recommended:

(6)

(7)

the feedback capacitor should be:

(8)

Note that these capacitor values are usually significant smaller than those given by the older, more conservative

formula:

(9)

CSconsists of the amplifier's input capacitance plus any stray capacitance from the circuit board and socket. CF

compensates for the pole caused by CSand the feedback resistors.

Figure 16. General Operational Amplifier Circuit

Using the smaller capacitors will give much higher bandwidth with little degradation of transient response. It may

be necessary in any of the above cases to use a somewhat larger feedback capacitor to allow for unexpected

stray capacitance, or to tolerate additional phase shifts in the loop, or excessive capacitive load, or to decrease

the noise or bandwidth, or simply because the particular circuit implementation needs more feedback

capacitance to be sufficiently stable. For example, a printed circuit board's stray capacitance may be larger or

smaller than the breadboard's, so the actual optimum value for CFmay be different from the one estimated using

the breadboard. In most cases, the values of CFshould be checked on the actual circuit, starting with the

computed value.

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CAPACITIVE LOAD TOLERANCE

Like many other op amps, the LMC660 may oscillate when its applied load appears capacitive. The threshold of

oscillation varies both with load and circuit gain. The configuration most sensitive to oscillation is a unity-gain

follower. See Typical Performance Characteristics.

The load capacitance interacts with the op amp's output resistance to create an additional pole. If this pole

frequency is sufficiently low, it will degrade the op amp's phase margin so that the amplifier is no longer stable at

low gains. As shown in Figure 17, the addition of a small resistor (50Ωto 100Ω) in series with the op amp's

output, and a capacitor (5 pF to 10 pF) from inverting input to output pins, returns the phase margin to a safe

value without interfering with lower-frequency circuit operation. Thus larger values of capacitance can be

tolerated without oscillation. Note that in all cases, the output will ring heavily when the load capacitance is near

the threshold for oscillation.

Figure 17. Rx, Cx Improve Capacitive Load Tolerance

Capacitive load driving capability is enhanced by using a pull up resistor to V+(Figure 18). Typically a pull up

resistor conducting 500 μA or more will significantly improve capacitive load responses. The value of the pull up

resistor must be determined based on the current sinking capability of the amplifier with respect to the desired

output swing. Open loop gain of the amplifier can also be affected by the pull up resistor (see DC Electrical

Characteristics).

Figure 18. Compensating for Large Capacitive Loads with a Pull Up Resistor

PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK

It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires

special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the LMC662,

typically less than 0.04 pA, it is essential to have an excellent layout. Fortunately, the techniques for obtaining

low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board, even though

it may sometimes appear acceptably low, because under conditions of high humidity or dust or contamination,

the surface leakage will be appreciable.

To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC660's inputs

and the terminals of capacitors, diodes, conductors, resistors, relay terminals, etc. connected to the op amp's

inputs. See Figure 19. To have a significant effect, guard rings should be placed on both the top and bottom of

the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifier

inputs, since no leakage current can flow between two points at the same potential. For example, a PC board

trace-to-pad resistance of 1012Ω, which is normally considered a very large resistance, could leak 5 pA if the

trace were a 5V bus adjacent to the pad of an input. This would cause a 100 times degradation from the

LMC660's actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a resistance

of 1011Ωwould cause only 0.05 pA of leakage current, or perhaps a minor (2:1) degradation of the amplifier's

performance. See Figure 20a,Figure 20b, and Figure 20cfor typical connections of guard rings for standard op

amp configurations. If both inputs are active and at high impedance, the guard can be tied to ground and still

provide some protection; see Figure 20d.

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Figure 19. Example, using the LMC660, of Guard Ring in P.C. Board Layout

(a) Inverting Amplifier

(b) Non-Inverting Amplifier

(d) Howland Current Pump

Figure 20. Guard Ring Connections

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The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few

circuits, there is another technique which is even better than a guard ring on a PC board: Don't insert the

amplifier's input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an

excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but

the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 21.

(Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board.)

Figure 21. Air Wiring

BIAS CURRENT TESTING

The test method of Figure 21 is appropriate for bench-testing bias current with reasonable accuracy. To

understand its operation, first close switch S2 momentarily. When S2 is opened, then:

(10)

Figure 22. Simple Input Bias Current Test Circuit

A suitable capacitor for C2 would be a 5 pF or 10 pF silver mica, NPO ceramic, or air-dielectric. When

determining the magnitude of Ib−, the leakage of the capacitor and socket must be taken into account. Switch S2

should be left shorted most of the time, or else the dielectric absorption of the capacitor C2 could cause errors.

Similarly, if S1 is shorted momentarily (while leaving S2 shorted):

(11)

where Cxis the stray capacitance at the + input.

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TYPICAL SINGLE-SUPPLY APPLICATIONS

(V+= 5.0 VDC)

Additional single-supply applications ideas can be found in the LM324 datasheet. The LMC660 is pin-for-pin

compatible with the LM324 and offers greater bandwidth and input resistance over the LM324. These features

will improve the performance of many existing single-supply applications. Note, however, that the supply voltage

range of the LMC660 is smaller than that of the LM324.

Figure 23. Low-Leakage Sample-and-Hold

Figure 24. Instrumentation Amplifier

If R1 = R5, R3 = R6, and R4 = R7; then

(12)

∴AV≈100 for circuit shown.

For good CMRR over temperature, low drift resistors should be used. Matching of R3 to R6 and R4 to R7 affect

CMRR. Gain may be adjusted through R2. CMRR may be adjusted through R7.

Figure 25. Sine-Wave Oscillator

Oscillator frequency is determined by R1, R2, C1, and C2:

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TYPICAL SINGLE-SUPPLY APPLICATIONS (continued)

(V+= 5.0 VDC)

fosc = 1/2πRC, where R = R1 = R2 and

C = C1 = C2.

This circuit, as shown, oscillates at 2.0 kHz with a peak-to-peak output swing of 4.5V.

Figure 26. 1 Hz Square-Wave Oscillator

Figure 27. Power Amplifier

Figure 28. 10 Hz Bandpass Filter

fO= 10 Hz

Q = 2.1

Gain = −8.8

Figure 29. 10 Hz High-Pass Filter

fc= 10 Hz

d = 0.895

Gain = 1

2 dB passband ripple

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TYPICAL SINGLE-SUPPLY APPLICATIONS (continued)

(V+= 5.0 VDC)

Figure 30. 1 Hz Low-Pass Filter

(Maximally Flat, Dual Supply Only)

fc= 1 Hz

d = 1.414

Gain = 1.57

Figure 31. High Gain Amplifier with Offset

Voltage Reduction

Gain = −46.8

Output offset voltage reduced to the level of the input offset voltage of the bottom amplifier (typically 1 mV).

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REVISION HISTORY

Changes from Revision C (March 2013) to Revision D Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 14

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PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LMC660AIM NRND SOIC D 14 55 Non-RoHS

& Green Call TI Call TI -40 to 85 LMC660AIM

LMC660AIM/NOPB ACTIVE SOIC D 14 55 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC660AIM

LMC660AIMX NRND SOIC D 14 2500 Non-RoHS

& Green Call TI Call TI -40 to 85 LMC660AIM

LMC660AIMX/NOPB ACTIVE SOIC D 14 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC660AIM

LMC660AIN/NOPB ACTIVE PDIP NFF 14 25 RoHS & Green SN Level-1-NA-UNLIM -40 to 85 LMC660AIN

LMC660CM NRND SOIC D 14 55 Non-RoHS

& Green Call TI Call TI 0 to 70 LMC660CM

LMC660CM/NOPB ACTIVE SOIC D 14 55 RoHS & Green SN Level-1-260C-UNLIM 0 to 70 LMC660CM

LMC660CMX/NOPB ACTIVE SOIC D 14 2500 RoHS & Green SN Level-1-260C-UNLIM 0 to 70 LMC660CM

LMC660CN/NOPB ACTIVE PDIP NFF 14 25 RoHS & Green SN Level-1-NA-UNLIM 0 to 70 LMC660CN

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

PACKAGE OPTION ADDENDUM

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Addendum-Page 2

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LMC660AIMX SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1

LMC660AIMX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1

LMC660CMX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

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Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LMC660AIMX SOIC D 14 2500 367.0 367.0 35.0

LMC660AIMX/NOPB SOIC D 14 2500 367.0 367.0 35.0

LMC660CMX/NOPB SOIC D 14 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

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Pack Materials-Page 2

MECHANICAL DATA

N0014A

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N14A (Rev G)

NFF0014A

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