IR22141SSTRPBF - International Rectifier

1

HALF-BRIDGE GATE DRIVER IC

Features

• Floating channel up to 600 V or 1200 V

• Soft over-current shutdown

• Synchronization signal to synchronize shutdown with the other phases

• Integrated desaturation detection circuit

• Two stage turn on output for di/dt control

• Separate pull-up/pull-down output drive pins

• Matched delay outputs

• Undervoltage lockout with hysteresis band

• Lead free

Description

The IR21141/IR22141 gate driver family is suited to drive a single half bridge

in power switching applications. These drivers provide high gate driving

capability (2 A source, 3 A sink) and require low quiescent current, which

allows the use of bootstrap power supply techniques in medium power

systems. These drivers feature full short circuit protection by means of power

transistor desaturation detection and manage all half-bridge faults by

smoothly turning off the desaturated transistor through the dedicated soft

shutdown pin, therefore preventing over-voltages and reducing

electromagnetic emissions. In multi-phase systems, the IR21141/IR22141

drivers communicate using a dedicated local network (SY_FLT and

FAULT/SD signals) to properly manage phase-to-phase short circuits. The

system controller may force shutdown or read device fault state through the

3.3 V compatible CMOS I/O pin (FAULT/SD). To improve the signal immunity

from DC-bus noise, the control and power ground use dedicated pins

enabling low-side emitter current sensing as well. Undervoltage conditions in

floating and low voltage circuits are managed independently.

Product Summary

V

OFFSET

600 V or

1200 V max.

I

O

+/- (min) 1.0 A / 1.5 A

V

OUT

10.4 V – 20 V

Deadtime matching (max) 75 ns

Deadtime (typ) 330 ns

Desat blanking time (typ) 3 µs

DSH, DSL input voltage

threshold (typ) 8.0 V

Soft shutdown time (typ) 9.25 µs

Package

24-Lead SSOP

Typical connection

IR21141SSPbF/IR22141SSPbF

Data Sheet

No. PD60

349

r

evL

IR21141/IR22141SSPbF

2

Recommended Operating Conditions

For proper operation the devi

ce should be used within the recommended conditions. All voltage parameters are absolute

voltages referenced to V

SS

. The V

S

offset rating is tested with all supplies biased at a 15 V differential.

Symbol

Definition Min. Max. Units

V

B

High side floating supply voltage

†

V

S

+ 11.5 V

S

+ 20

IR21141 V

SS

600

V

S

High side floating supply offset voltage

††

IR22141 V

SS

1200

V

HO

High side output voltage (HOP, HON and SSDH) V

S

V

S

+ 20

V

LO

Low side output voltage (LOP, LON and SSDL) V

COM

V

CC

V

CC

Low side and logic fixed supply voltage (Note 1) 11.5 20

COM Power ground -5 5

V

IN

Logic input voltage (HIN, LIN and FLT_CLR) V

SS

V

CC

V

FLT

Fault input/output voltage (FAULT/SD and SY_FLT) V

SS

V

CC

V

DSH

High side DS pin input voltage V

S

- 2.0 V

B

V

DSL

Low side DS pin input voltage V

COM

- 2.0 V

CC

V

t

PWHIN

High side pulse width for HIN input 1 µs

T

A

Ambient temperature -40 125 °C

† While internal circuitry is operational below the indicated supply voltages, the UV lockout disables the output

drivers if the UV thresholds are not reached. A minimum supply voltage of 8V is recommended for the driver

to operate safely under switching conditions at VS pin (please refer to the “start-up sequence” in application

section of this document)

†† Logic operational for V

S

from V

SS

-5 V to V

SS

+600 V or 1200 V. Logic state held for V

S

from V

SS

-5 V to V

SS

-

V

BS

. For a negative spike on V

B

(referenced to V

SS

) of less than 200ns the IC will withstand a sustained peak

of -40V under normal operation and an isolated event of up to -70V peak spike (please refer to the Design

Tip DT97-3 for more details).

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage

parameters are absolute voltages referenced to V

SS

, all currents are defined positive into any lead The thermal resistance

and power dissipation ratings are measured under board mounted and still air conditions.

Symbol

Definition Min. Max. Units

V

S

High side offset voltage V

B

- 25 V

B

+ 0.3

IR21141 -0.3 625

V

B

High side floating supply voltage IR22141 -0.3 1225

V

HO

High side floating output voltage (HOP, HON and SSDH) V

S

- 0.3 V

B

+ 0.3

V

CC

Low side and logic fixed supply voltage -0.3 25

COM Power ground V

CC

- 25 V

CC

+ 0.3

V

LO

Low side output voltage (LOP, LON and SSDL) V

COM

-0.3 V

CC

+ 0.3

V

IN

Logic input voltage (HIN, LIN and FLT_CLR) -0.3 V

CC

+ 0.3

V

FLT

Fault input/output voltage (FAULT/SD and SY_FLT) -0.3 V

CC

+ 0.3

V

DSH

High side DS input voltage V

S

-3 V

B

+ 0.3

V

DSL

Low side DS input voltage V

COM

-3 V

CC

+ 0.3

V

dVs/dt Allowable offset voltage slew rate — 50 V/ns

P

D

Package power dissipation @ T

A

≤ 25 °C — 1.5 W

Rth

JA

Thermal resistance, junction to ambient — 65 °C/W

T

J

Junction temperature — 150

T

S

Storage temperature -55 150

T

L

Lead temperature (soldering, 10 seconds) — 300

°C

IR21141/IR22141SSPbF

3

Static Electrical Characteristics

V

CC

= 15 V, V

SS

= COM = 0 V, V

S

= 600 V or 1200 V and T

A

= 25 °C unless otherwise specified.

Pins: V

CC

, V

SS

, V

B

, V

S

(refer to Fig. 1)

Symbol

Definition Min

Typ Max

Units

Test Conditions

V

CCUV+

V

CC

supply undervoltage positive going threshold 9.3 10.2 11.4

V

CCUV-

V

CC

supply undervoltage negative going threshold 8.7 9.3 10.3

V

CCUVH

V

CC

supply undervoltage lockout hysteresis — 0.9 —

V

BSUV+

(V

B

-V

S

) supply undervoltage positive going threshold 9.3 10.2 11.4

V

BSUV-

(V

B

-V

S

) supply undervoltage negative going threshold 8.7 9.3 10.3

V

S

= 0 V, V

S

= 600 V

or 1200 V

V

BSUVH

(V

B

-V

S

) supply undervoltage lockout hysteresis — 0.9 —

V

I

LK

Offset supply leakage current — — 50 V

B

= V

S

= 600 V or

1200 V

I

QBS

Quiescent V

BS

supply current — 400 800

µA

V

IN

= 0 V or 3.3 V

I

QCC

Quiescent V

CC

supply current — 0.7 2.5 mA no load

Pins: HIN, LIN, FLTCLR, FAULT/SD, SY_FLT (refer to Fig. 2, 3)

Symbol

Definition Min

Typ Max Units

Test Conditions

V

IH

Logic "1" input voltage 2.0 — —

V

IL

Logic "0" input voltage — — 0.8

V

IHSS

Logic input hysteresis 0.2 0.4 —

V V

CC

= V

CCUV-

to 20 V

Logic “1” input bias current (HIN, LIN, FLTCLR) — 330 —

I

IN+

Logic “0” input bias current (FAULT/SD, SY_FLT) 0 — 1

V

IN

= 3.3 V

Logic “0” input bias current -1 — 0

I

IN-

Logic “1” input bias current (FAULT/SD, SY_FLT) -1 — 0

µA

V

IN

= 0 V

R

ON,FLT

FAULT/SD open drain resistance — 60 —

R

ON,SY

SY_FLT open drain resistance — 60 —

Ω PW≤ 7 µs

Pins: DSL, DSH (refer to Fig. 4)

The active bias is present only the IR21141and IR22141. V

DESAT

, I

DS

and I

DSB

parameters are referenced to COM and V

S

respectively for DSL and DSH.

Symbol

Definition Min

Typ

Max

Units

Test Conditions

V

DESAT+

High desat input threshold voltage 7.2

8.0

8.8

V

DESAT-

Low desat input threshold voltage 6.3

7.0

7.7

V

DSTH

Desat input voltage hysteresis —

1.0

—

V See Figs. 4,16

I

DS+

High DSH or DSL input bias current —

21 — V

DESAT

= V

CC

or V

BS

I

DS

- Low DSH or DSL input bias current —

-160

— µA V

DESAT

= 0 V

I

DSB

DSH or DSL input bias current

(IR21141 and IR22141 only) —

-20

— mA V

DESAT

= (V

CC

or V

BS

) – 2 V

IR21141/IR22141SSPbF

4

Pins: HOP, LOP (refer to Fig. 5)

Symbol

Definition Min

Typ Max

Units

Test Conditions

V

OH

High level output voltage, V

B

– V

HOP

or V

CC

–V

LOP

— 40 300 mV I

O

= 20 mA

I

O1+

Output high first stage short circuit pulsed current 1 2 —

V

HOP/LOP

= 0 V, H

IN

or L

IN

= 1, PW≤

200 ns, resistive

load, see Fig. 8

I

O2+

Output high second stage short circuit pulsed current

0.5

1 —

A

V

HOP/LOP

= 0 V, H

IN

or L

IN

= 1,

400 ns ≤PW≤ 10

µs, resistive load,

see Fig. 8

Pins: HON, LON, SSDH, SSDL (refer to Fig. 6)

Symbol

Definition Min

Typ Max

Units

Test Conditions

V

OL

Low level output voltage, V

HON

or V

LON

— 45 300 mV I

O

= 20 mA

R

ON,SSD

Soft Shutdown on resistance

†

— 90 — Ω PW≤ 7 µs

I

O-

Output low short circuit pulsed current 1.5

3 — A

V

HOP/LOP

= 15 V,

H

IN

or L

IN

= 0, PW≤

10 µs

† SSD operation only

IR21141/IR22141SSPbF

5

AC Electrical Characteristics

V

CC

= V

BS

= 15 V, V

S

= V

SS

and T

A

= 25 °C unless otherwise specified.

Symbol

Definition Min. Typ.

Max.

Units

Test Conditions

t

on

Turn on propagation delay 220 440 660

t

off

Turn off propagation delay 220 440 660

t

r

Turn on rise time (C

LOAD

=1 nF) — 24 —

t

f

Turn off fall time (C

LOAD

=1 nF) — 7 —

V

IN

= 0 & 1, V

S

= 0 V to 600 V

or 1200 V,

HOP shorted to HON, LOP

shorted to LON, Fig. 7

t

on1

Turn on first stage duration time 120 200 280 Fig. 8

t

DESAT1

DSH to HO soft shutdown propagation delay at HO

turn on 2000 3300

4600

V

HIN

= 1 V

t

DESAT2

DSH to HO soft shutdown propagation delay after

blanking 1050 — — V

DESAT

= 15 V, Fig. 10

t

DESAT3

DSL to LO soft shutdown propagation delay at LO

turn on 2000 3300

4600

V

LIN

= 1 V

t

DESAT4

DSL to LO soft shutdown propagation delay after

blanking 1050 — — V

DESAT

= 15 V, Fig. 10

t

DS

Soft shutdown minimum pulse width of desat 1000 — — Fig. 9

t

SS

Soft shutdown duration period 5700 9250

13500

V

DS

=15 V, Fig. 9

t

SY_FLT,

DESAT1

DSH to SY_FLT propagation delay at HO turn on — 3600

— V

HIN

= 1 V

t

SY_FLT,

DESAT2

DSH to SY_FLT propagation delay after blanking 1300 — — V

DS

= 15 V, Fig. 10

t

SY_FLT

,

DESAT3

DSL to SY_FLT propagation delay at LO turn on — 3050

— V

LIN

= 1 V

t

SY_FLT

,

DESAT4

DSL to SY_FLT propagation delay after blanking 1050 — — V

DESAT

=15 V, Fig. 10

t

BL

DS blanking time at turn on — 3000

— V

HIN

= V

LIN

= 1 V, V

DESAT

=15 V,

Fig. 10

Deadtime/Delay Matching Characteristics

DT Deadtime — 330 — Fig. 11

MDT Deadtime matching, MDT=DTH-DTL — — 75 External DT = 0 s, Fig. 11

PDM Propagation delay matching,

Max (ton, toff) – Min (ton, toff) — — 75

ns

External DT > 500 ns, Fig. 7

IR21141/IR22141SSPbF

6

Figure 1: Undervoltage Diagram Figure 2: HIN, LIN and FLTCLR Diagram

Figure 3: FAULT/SD and SY_FLT Diagram Figure 4: DSH and DSL Diagram

Figure 5: HOP and LOP Diagram Figure 6: HON, LON, SSDH and SSDL Diagram

V

CC

/V

B

V

CCUV

/V

BSUV

V

SS

/V

S

comparator

UV internal

signal

HIN/LIN/

FLTCLR

V

SS

schmitt

trigger

10k

internal

signal

DSL/DSH

V

DESAT

COM/V

S

comparator

100k

700k

V

CC

/V

BS

SSD internal

signal

active

bias

LOP/HOP

V

CC

/V

B

on/off

internal signal

V

OH

200ns

oneshot

SSDL/SSDH

COM/V

S

on/off

internal signal

R

ON,SSD

LON/HON

desat

internal signal

V

OL

FAULT/SD

SY_FLT

V

SS

schmitt

tr

igger

R

ON

fault/hold

internal signal

IR21141/IR22141SSPbF

7

HIN

LIN

HO (HOP=HON)

LO (LOP=LON)

10%

3.3V

PW

in

PW

out

10%

90% 90%

50% 50%

t

on

t

r

t

off

t

f

Figure 7: Switching Time Waveforms

Ton1

Io1+

Io2+

Figure 8:

Output Source Current

HIN/LIN

HO/LO

8V 8V

t

SS

t

DESAT

3.3V

DSH/DSL

t

DS

SSD Driver Enable

Figure 9:

Soft Shutdown Timing Waveform

IR21141/IR22141SSPbF

8

HIN

DSH

SY_FLT

t

DESAT1

8V

50%

t

SY_FLT,DESAT1

HON

90%

50%

t

BL

FAULT/SD

FLTCLR

SoftShutdown

LIN

LON

90%

SoftShutdown

t

DESAT2

8V

t

SY_FLT,DESAT2

50%

t

BL

DSL

90%

50%

t

BL

SoftShutdown

90%

SoftShutdown

50%

t

BL

8V 8V

50%

t

SY_FLT,DESAT3

t

SY_FLT,DESAT4

t

DESAT3

t

DESAT4

50%

Turn-On Propagation Delay

90%

Turn_Off propagation Delay

50%

90%

50%

10%

Figure 10:

Desat Timing

HIN

LIN

HO (HOP=HON)

LO (LOP=LON)

DTH DTL

50%

MDT=DTH-DTL

Figure 11:

Internal Deadtime Timing

IR21141/IR22141SSPbF

9

Lead Assignments

24-Lead SSOP

Lead Definitions

Symbol Description

V

CC

Low side gate driver supply

V

SS

Logic ground

HIN Logic input for high side gate driver outputs (HOP/HON)

LIN Logic input for low side gate driver outputs (LOP/LON)

FAULT/SD

Dual function (in/out) active low pin. Refer to Figs. 15, 17, and 18. As an output, indicates fault condition.

As an input, shuts down the outputs of the gate driver regardless H

IN

/L

IN

status.

SY_FLT

Dual function (in/out) active low pin. Refer to Figs. 15, 17, and 18. As an output, indicates SSD sequence

is occurring. As an input, an active low signal freezes both output status.

FLT_CLR Fault clear active high input. Clears latched fault condition (see Fig. 17)

LOP Low side driver sourcing output

LON Low side driver sinking output

DSL Low side IGBT desaturation protection input

SSDL Low side soft shutdown

COM Low side driver return

V

B

High side gate driver floating supply

HOP High side driver sourcing output

HON High side driver sinking output

DSH High side IGBT desaturation protection input

SSDH High side soft shutdown

V

S

High side floating supply return

SSOP24

1

12

24

13

SSDL

FLT_CLR

HIN

COM

SY_FLT

LON

FAULT/SD

VSS

LOP

VCC

DSL

HOP

SSDH

HON

N.C.

VS

N.C.

DSH

VB

N.C.

LIN

IR21141/IR22141SSPbF

10

SCHMITT

TRIGGER

INPUT

SHOOT

THROUGH

PREVENTION

(DT) Deadtime

LEVEL

SHIFTERS

LATCH

LOCAL DESAT

PROTECTION

SOFT SHUTDOWN

UV_VBS DETECT

di/dt control

Driver

UV_VCC

DETECT

LOCAL DESAT

PROTECTION

SOFTSHUTDOWN

di/dt control

Driver

on/off

desat

soft

shutdown

on/off

soft

shutdown

on/off (HS)

DesatHS

DesatLS

on/off (LS)

Hard ShutDown

internal Hold

SD

FAULT LOGIC

managemend

(See figure 14)

UV_VCC

VB

HOP

HON

SSDH

DSH

VS

LOP

LON

SSDL

DSL

COM

VSS

FLT_CLR

FAULT/SD

SY_FLT

LIN

HIN

VCC

FAULT

HOLDSSD

INPUT

HOLD

LOGIC

OUTPUT

SHUTDOWN

LOGIC

FUNCTIONAL BLOCK DIAGRAM

Start-Up

Sequence

FAULT

HO/LO=1

HO=LO=0

UnderVoltage

V

CC

HO=LO=0

Freeze

ShutDown

SY_FLT

FLT_CLR

HIN/LIN

UV_VCC

UV_VBS

FAULT/SD

DSH/L

FAULT/SD

UV_VBS

UV_VCC

DESAT

EVENT

UnderVoltage

V

BS

HO=0, LO=LIN

Soft

ShutDown

STATE DIAGRAM

Stable State

−

FAULT

−

HO=LO=0 (Normal operation)

−

HO/LO=1 (Normal operation)

−

UNDERVOLTAGE V

CC

−

SHUTDOWN (SD)

−

UNDERVOLTAGE V

BS

−

FREEZE

Temporary State

−

SOFT SHUTDOWN

−

START UP SEQUENCE

System Variable

−

FLT_CLR

−

HIN/LIN

−

UV_VCC

−

UV_VBS

−

DSH/L

−

SY_FLT

−

FAULT/SD

NOTE 1: A change of logic value of the signal labeled on lines (system variable) generates a state transition.

NOTE 2: Exiting from UNDERVOLTAGE V

BS

state, the HO goes high only if a rising edge event happens in

H

IN

.

IR21141/IR22141SSPbF

11

HO/LO Status HOP/LOP HON/LON SSDH/SSDL

0

HiZ 0 HiZ

1

1 HiZ HiZ

SSD

HiZ HiZ 0

LO/HO

Output follows inputs (in=1->out=1, in=0->out=0)

LO

n-1

/HO

n-1

Output keeps previous status

Logic Table: Output Drivers Status Description

INPUTS

INPUT/OUTPUT

Undervoltage

Yes: V< UV

threshold

No : V> UV

threshold

X: don’t care

OUTPUTS

Operation

Hin

Lin

FLT_CLR

______

SY_FLT

SSD: desat (out)

HOLD: freezing

(in)

_________

FAULT/SD

SD: shutdown (in)

FAULT: diagnostic

(out)

V

CC

V

BS

HO LO

Shutdown

X X X X 0 (SD) X X 0 0

Fault Clear

H

IN

L

IN

X

†

(FAULT) No No HO LO

Fault Cleared

H

IN

L

IN

1 X 1

††

No No HO LO

1 0 0 1 1 No No 1 0

0 1 0 1 1 No No 0 1

Normal

Operation

0 0 0 1 1 No No 0 0

Anti Shoot

Through

1 1 0 1 1 No No 0 0

1 0 0 (SSD) 1 No No SSD 0

Soft

Shutdown

(entering)

0 1 0 (SSD) 1 No No 0 SSD

X X 0 (SSD) (FAULT) No No 0 0

Soft

Shutdown

(finishing)

X X 0 (SSD) (FAULT) No No 0 0

Freeze

X X X 0 (HOLD) 1 No No HO

n-1

LO

n-1

X L

IN

X 1 1 No Yes 0 LO

Undervoltage

X X X 1 0 (FAULT) Yes X 0 0

† SY_FLT automatically resets after the SSD event is over, without requiring FLT_CLR to be asserted. To

avoid FLT_CLR conflicting with the SSD sequence of operations, in the event of a SSD during normal

operation it is recommended not to apply FLT_CLR while SY_FLT is active. At power supply start-up

instead, it is recommended to keep FLT_CLR active to prevent spurious diagnostic signals being

generated, as described in section 1.1 Start-Up Sequence and in section 1.4.5 Fault Management at

Start-up.

†† Holding FLT_CLR high all time will not allow the gate driver to latch the FAULT status and migth

compromise power system protection.

IR21141/IR22141SSPbF

12

1 Features Description

1.1 Start-Up Sequence

At power supply start-up, it is recommended to keep the

FLT_CLR pin active until the supply voltages are

properly established. This prevents spurious diagnostic

signals being generated.

When the bootstrap supply topology is used for

supplying the floating high side stage, the following start-

up sequence is recommended (see also Fig. 12):

1. Set V

CC

,

2. Set FLT_CLR pin to HIGH level,

3. Set LIN pin to HIGH level and charge the

bootstrap capacitor,

4. Release LIN pin to LOW level,

5. Release FLT_CLR pin to LOW level.

VCC

FLT_CLR

LIN

LO

Figure 12

Start-Up Sequence

A minimum 15 µs LIN and FLT-CLR pulse is required.

A minimum supply voltage of 8V is recommended for the

driver to operate safely under switching conditions at VS

pin. At lower supply the gate driving capability decreases

and might become not sufficient to counteract switching

charge injected to the outputs.

1.2 Normal Operation Mode

After the start-up sequence has completed, the device

becomes fully operative (see grey blocks in the State

Diagram).

HIN and LIN produce driver outputs to switch

accordingly, while the input logic monitors the input

signals and deadtime (DT) prevent shoot-through events

from occurring.

1.3 Shutdown

The system controller can asynchronously command the

Hard Shutdown (HSD) through the 3.3 V compatible

CMOS I/O FAULT/SD pin. This event is not latched.

In a multi-phase system, FAULT/SD signals are or-ed so

the controller or one of the gate drivers can force the

simultaneous shutdown of the other gate drivers through

the same pin.

1.4 Fault Management

The IR21141/IR22141 is able to manage supply failure

(undervoltage lockout) and transistor desaturation (on

both the low and high side switches).

1.4.1 Undervoltage (UV)

The undervoltage protection function disables the

driver’s output stage which prevents the power device

from being driven when the input voltage is less than the

undervoltage threshold. Both the low side (V

CC

supplied)

and the floating side (V

BS

supplied) are controlled by a

dedicate undervoltage function.

An undervoltage event on the V

CC

pin (when

V

CC

< UV

VCC-

) generates a diagnostic signal by forcing

the FAULT/SD pin low (see FAULT/SD section and Fig.

14). This event disables both the low side and floating

drivers and the diagnostic signal holds until the

undervoltage condition is over. The fault condition is not

latched and the FAULT/SD pin is released once V

CC

becomes higher than UV

VCC+

.

The V

BS

undervoltage protection works by disabling only

the floating driver. Undervoltage on V

BS

does not prevent

the low side driver from activating its output nor does it

generate diagnostic signals. The V

BS

undervoltage

condition (V

BS

< UV

VBS-

) latches the high side output

stage in the low state. V

BS

must exceed the UV

VBS+

threshold to return the device to its normal operating

mode. To turn on the floating driver, H

IN

must be re-

asserted high (rising edge event on H

IN

is required).

1.4.2 Power Devices Desaturation

Different causes can generate a power inverter failure

(phase and/or rail supply short-circuit, overload

conditions induced by the load, etc.). In all of these fault

conditions, a large increase in current results in the

IGBT.

The IR21141/IR22141 fault detection circuit monitors the

IGBT emitter to collector voltage (V

CE

) (an external high

voltage diode is connected between the IGBT’s collector

and the ICs DSH or DSL pins). A high current in the

IGBT may cause the transistor to desaturate; this

condition results in an increase of V

CE

.

Once in desaturation, the current in the power transistor

can be as high as 10 times the nominal current.

Whenever the transistor is switched off, this high current

generates relevant voltage transients in the power stage

that need to be smoothed out in order to avoid

destruction (by over-voltage). The gate driver is able to

control the transient condition by smoothly turning off the

desaturated transistor with its integrated soft shutdown

(SSD) protection.

1.4.3 Desaturation Detection: DSH/L Function

Figure 13 shows the structure of the desaturation

sensing and soft shutdown block. This configuration is

the same for both the high and low side output stages.

IR21141/IR22141SSPbF

13

Ron,ss

RDSH/L

Figure 13: High and Low Side Output Stage

FLTCLR

Q

SET

CLR

S

R

FAULT/SD

SY_FLT

internal

HOLD

(external

hold)

(external hard

shutdown)

internal FAULT

(hard shutdown)

UVCC

DesatHS

DesatLS

Figure 14: Fault Management Diagram

The external sensing diode should have breakdown

voltage greater than 600 V (IR21141) or 1200 V

(IR22141), and low stray capacitance (in order to

minimize noise coupling and switching delays). The

diode is biased by an internal pull-up resistor R

DSH/L

(equal to V

CC

/I

DS-

or V

BS

/I

DS-

) or by a dedicated circuit

(see the active-bias section). To limit the current flowing

through DSH and DSL in case of desaturation an

external Schottky diode is required, as shown in Fig. 13.

When V

CE

increases, the voltage at the DSH or DSL pin

increases too. Being internally biased to the local supply,

the DSH/DSL voltage is automatically clamped. When

DSH/DSL exceeds the V

DESAT+

threshold, the

comparator triggers (see Fig. 13). The comparator’s

output is filtered in order to avoid false desaturation

detection by externally induced noise; pulses shorter

than t

DS

are filtered out. To avoid detecting a false

desaturation event during IGBT turn on, the desaturation

circuit is disabled by a blanking signal (T

BL

, see blanking

block in Fig. 13). This time is the estimated maximum

IGBT turn on time and must be not exceeded by proper

gate resistance sizing. When the IGBT is not completely

saturated after T

BL

, desaturation is detected and the

driver will turn off.

Eligible desaturation signals initiate the SSD sequence.

While in SSD, the driver’s output goes to a high

impedance state and the SSD pull-down is activated to

turn off the IGBT through the SSDH/SSDL pin. The

SY_FLT output pin (active low, see Fig. 14) reports the

gate driver status during the SSD sequence (t

SS

). Once

the SSD has finished, SY_FLT releases, and the gate

driver generates a FAULT signal (see the FAULT/SD

section) by activating the FAULT/SD pin. This generates

a hard shutdown for both the high and low output stages

(HO=LO=low). Each driver is latched low until the fault is

cleared (see FLT_CLR).

Figure 14 shows the fault management circuit. In this

diagram DesatHS and DesatLS are two internal signals

that come from the output stages (see Fig. 13).

It must be noted that while in SSD, both the

undervoltage fault and external SD are masked until the

end of SSD. Desaturation protection is working

independently by the other control pin and it is disabled

only when the output status is off.

1.4.4 Fault Management in Multi-Phase Systems

In a system with two or more gate drivers the

IR21141/IR22141 devices must be connected as shown

in Fig. 15.

IR21141/IR22141SSPbF

14

VCC

LIN

HIN

FLT_CLR

VB

HOP

HON

SSH

DSH

VS

LOP

LON

SSL

DSL

COMVSS

SY_FLT

FAULT/SD

IR2214

VCC

LIN

HIN

FLT_CLR

VB

HOP

HON

SSH

DSH

VS

LOP

LON

SSL

DSL

COMVSS

SY_FLT

FAULT/SD

IR2214

VCC

LIN

HIN

FLT_CLR

VB

HOP

HON

SSH

DSH

VS

LOP

LON

SSL

DSL

COMVSS

SY_FLT

FAULT/SD

IR2214

phase U phase V phase W

FAULT

Figure 15:

IR22141 used in a 3 phase application

SY_FLT:

The bi-directional SY_FLT pins communicate

each other through a local network. The logic signal is

active low. The device that detects the IGBT

desaturation activates the SY_FLT, which is then read

by the other gate drivers. When SY_FLT is active all the

drivers hold their output state regardless of the input

signals (H

IN

, L

IN

) they receive from the controller (freeze

state). This feature is particularly important in phase-to-

phase short circuit where two IGBTs are involved; in

fact, while one is softly shutting-down, the other must be

prevented from hard shutdown to avoid exiting SSD. In

the freeze state, the frozen drivers are not completely

inactive because desaturation detection still takes the

highest priority. SY_FLT communication has been

designed for creating a local network between the

drivers.

FAULT/SD:

The bi-directional FAULT/SD pins

communicate with each other and with the system

controller. The logic signal is active low. When low, the

FAULT/SD signal commands the outputs to go off by

hard shutdown. There are three events that can force

FAULT/SD low:

1. Desaturation detection event: the FAULT/SD

pin is

latched

low when SSD is over, and only a

FLT_CLR signal can reset it;

2. Undervoltage on V

CC

: the FAULT/SD pin is

forced low and held until the undervoltage is

active. This event is not latched;

3. FAULT/SD is externally driven low either from

the controller or from another IR21141/IR22141

device. This event is not latched; therefore the

FLT_CLR cannot disable it. Only when

FAULT/SD becomes high the device returns to

its normal operating mode.

1.4.5 Fault Management at Start-up

When the bootstrap supply topology is used for

supplying the floating high side and the recommended

power supply start-up sequence is followed, FLT_CLR

pin must be kept active to prevent spurious diagnostic

signals being generated.

In the event of power inverter failure already present or

occurring during start-up (phase and/or rail supply short-

circuit, overload conditions induced by the load, etc.),

keeping the FLT_CLR pin active will also prevent the

real fault condition to be detected with the FAULT/SD

pin. In such a condition a large current increase in the

IGBT will desaturate the transistor, allowing the gate

driver to detect and turn-off the desaturated transistor

with the integrated soft shutdown (SSD) protection.

As with a normal SSD sequence, during SSD the

SY_FLT output pin (active low, see Fig. 14) will report

the gate driver status. But now, being the FLT_CLR pin

already active, the gate driver will not generate a FAULT

signal by activating the FAULT/SD pin and it will not

enter hard shutdown.

To prevent the driver to resume charging the bootstrap

capacitor, therefore re-establishing the condition that will

determine again the occurrence of the large current

increase in the IGBT, it is recommended to monitor the

SY_FLT output pin. Should the SY_FLT output pin go

low during the start-up sequence, the controller must

interpret a power inverter failure is present, and stop the

start-up sequence.

1.5 Active Bias

For the purpose of sensing the power transistor

desaturation, the collector voltage is monitored (an

external high voltage diode is connected between the

IGBT’s collector and the IC’s DSH or DSL pin). The

diode is normally biased by an internal pull up resistor

connected to the local supply line (V

B

or V

CC

). When the

transistor is “on” the diode is conducting and the amount

of current flowing in the circuit is determined by the

internal pull up resistor value.

In the high side circuit, the desaturation biasing current

may become relevant for dimensioning the bootstrap

capacitor (see Fig. 19). In fact, a pull up resistor with a

low resistance may result in a high current that

significantly discharges the bootstrap capacitor. For that

reason, the internal pull up resistor typical value is of the

order of 100 k

Ω

.

While the impedance of the DSH/DSL pins is very low

when the transistor is on (low impedance path through

the external diode down to the power transistor), the

impedance is only controlled by the pull up resistor when

the transistor is off. In that case, relevant dV/dt applied

by the power transistor during the commutation at the

output results in a considerable current injected through

the stray capacitance of the diode into the desaturation

detection pin (DSH/DSL). This coupled noise may be

easily reduced by using an active bias structure for the

sensing diode.

In IR21141/IR22141 the DSH/DSL pins integrate an

active pull-up structure respectively to V

B

/V

CC,

and a pull-

down structure to V

S

/COM.

The dedicated biasing circuit reduces the impedance on

the DSH/DSL pin when the voltage exceeds the V

DESAT

threshold (see Fig. 16). This low impedance helps

rejecting the noise current injected by the parasitic

capacitance. When the power transistor is fully on, the

sensing diode is forward biased and the voltage at the

DSH/DSL pin decreases. At this point the biasing circuit

deactivates, to reduce the bias current of the diode as

shown in Fig. 16.

In certain switching conditions (short pulses, high

temperature) the recovery current of the external de-

saturation sensing diode might reach levels beyond the

capability of the active bias circuit. In order to avoid

malfunctions and damage for the IC an external Schottky

IR21141/IR22141SSPbF

15

diode is required between DSH and VB and between

DSL and Vcc, as shown in Fig 13. A diode similar to the

1N5818 is good enough to protect DSH and DSL.

V

DSH/L

V

DESAT-

V

DESAT+

100 ohm

100K ohm

R

DSH/L

Figure 16:

R

DSH/L

Active Biasing

1.6 Output Stage

The structure is shown in Fig. 13 and consists of two

turn on stages and one turn off stage. When the driver

turns on the IGBT (see Fig. 8), a first stage is activated

while an additional stage is maintained in the active state

for a limited time (t

on1

). This feature boosts the total

driving capability in order to accommodate both a fast

gate charge to the plateau voltage and dV/dt control in

switching.

At turn off, a single n-channel sinks up to 3 A (I

O-

) and

offers a low impedance path to prevent the self-turn on

due to the parasitic Miller capacitance in the power

switch.

1.7 Timing and Logic State Diagrams Description

The following figures show the input/output logic

diagram. Figure 17 shows the SY_FLT and FAULT/SD

signals as outputs, whereas Fig. 18 shows them as

inputs.

HIN

LIN

FAULT/SD

LO(LO P/LO N)

DSH

FLT_CLR

SY_FLT

HO(HOP/HON)

DSL

A B C D E F G

Figure 17:

I/O Timing Diagram with SY_FLT and FAULT/SD as Output

A B C D E F

HIN

LIN

SY_FLT

FAULT/SD

FLT_CLR

HO (HOP/HON)

LO (LOP/LON)

Figure 18:

I/O Logic Diagram with SY_FLT and FAULT/SD as Input

IR21141/IR22141SSPbF

16

Referred to the timing diagram of Fig. 17:

A. When the input signals are on together the

outputs go off (anti-shoot through),

B. The HO signal is on and the high side IGBT

desaturates, the HO turn off softly while the

SY_FLT stays low. When SY_FLT goes high

the FAULT/SD goes low. While in SSD, if LIN

goes up, LO does not change (freeze),

C. When FAULT/SD is latched low (see

FAULT/SD section) FLT_CLR can disable it

and the outputs go back to follow the inputs,

D. The DSH goes high but this is not read

because HO is off,

E. The LO signal is on and the low side IGBT

desaturates, the low side behaviour is the

same as described in point B,

F. The DSL goes high but this is not read as LO

is off,

G.

As point A (anti-shoot through

).

Referred to the timing diagram Fig. 18:

A. The device is in the hold state, regardless of

input variations. The hold state results as

SY_FLT is forced low externally,

B. The device outputs go off by hard shutdown,

externally commanded. A through B is the

same sequence adopted by another IR2x14x

device in SSD procedure.

C. Externally driven low FAULT/SD (shutdown

state) cannot be disabled by forcing FLT_CLR

(see FAULT/SD section),

D. The FAULT/SD is released and the outputs go

back to follow the inputs,

E. Externally driven low FAULT/SD: outputs go

off by hard shutdown (like point B),

F. As point A and B but for the low side output.

IR21141/IR22141SSPbF

17

2 Sizing Tips

2.1 Bootstrap Supply

The V

BS

voltage provides the supply to the high side

driver circuitry of the gate driver. This supply sits on top

of the V

S

voltage and so it must be floating. The

bootstrap method is used to generate the V

BS

supply

and can be used with any of the IR211(4,41)/

IR221(4,41) drivers. The bootstrap supply is formed by

a diode and a capacitor as connected in Fig. 19.

bootstrap

diode

IR2214

bootstrap

capacitor

VB

VS

VCC

HOP

HON

SSDH

DC+

bootstrap

resistor

COM

V

CC

V

BS

V

F

V

GE

V

CEon

V

FP

I

LOAD

motor

R

boot

Figure 19: Bootstrap Supply Schematic

This method has the advantage of being simple and low

cost but may force some limitations on duty-cycle and

on-time since they are limited by the requirement to

refresh the charge in the bootstrap capacitor. Proper

capacitor choice can reduce drastically these

limitations.

2.2 Bootstrap Capacitor Sizing

To size the bootstrap capacitor, the first step is to

establish the minimum voltage drop (

∆V

BS

) that we

have to guarantee when the high side IGBT is on.

If

V

GEmin

is the minimum gate emitter voltage we want

to maintain, the voltage drop must be:

CEonGEFCCBS VVVVV

−

≤

∆

min

under the condition,

−

>

BSUVGE VV min

where

V

CC

is the IC voltage supply,

V

F

is bootstrap

diode forward voltage,

V

CEon

is emitter-collector voltage

of low side IGBT, and

V

BSUV-

is the high-side supply

undervoltage negative going threshold.

Now we must consider the influencing factors

contributing V

BS

to decrease:

−

IGBT turn on required gate charge (

Q

G

),

−

IGBT gate-source leakage current (

I

LK_GE

),

−

Floating section quiescent current (

I

QBS

),

−

Floating section leakage current (

I

LK

),

−

Bootstrap diode leakage current (

I

LK_DIODE

),

−

Desat diode bias when on (

I

DS

),

−

Charge required by the internal level shifters

(

Q

LS

); typical 20 nC,

−

Bootstrap capacitor leakage current (

I

LK_CAP

),

−

High side on time (

T

HON

).

I

LK_CAP

is only relevant when using an electrolytic

capacitor and can be ignored if other types of

capacitors are used. It is strongly recommend using at

least one low ESR ceramic capacitor (paralleling

electrolytic and low ESR ceramic may result in an

efficient solution).

Then we have:

+

=

QBSGELKLSGTOT

IIQQQ

_

(

HONDSCAPLKDIODELKLK

TIIII ⋅++++

−

)

__

The minimum size of bootstrap capacitor is:

BS

TOT

BOOT

V

Q

C∆

=

min

An example follows using IR2214SS or IR22141SS:

a) using a 25 A @ 125 °C 1200 V IGBT

(IRGP30B120KD):

•

I

QBS

= 800 µA (datasheet IR2214);

•

I

LK

= 50 µA (see Static Electrical Characteristics);

•

Q

LS

= 20 nC

•

Q

G

= 160 nC (datasheet IRGP30B120KD);

•

I

LK_GE

= 100 nA (datasheet IRGP30B120KD);

•

I

LK_DIODE

= 100 µA (reverse recovery <100 ns);

•

I

LK_CAP

= 0 (neglected for ceramic capacitor);

•

I

DS-

=

150 µA (see Static Electrical Characteristics);

•

T

HON

= 100 µs.

And:

•

V

CC

= 15 V

•

V

F

= 1 V

•

V

CEonmax

= 3.1 V

•

V

GEmin

= 10.5 V

the maximum voltage drop

∆V

BS

becomes

=−−−≤∆

CEonGEFCCBS

VVVVV

min

And the bootstrap capacitor is:

nF

V

nC

C

BOOT

725

4.0

290 =≥

NOTICE:

V

CC

has been chosen to be 15 V. Some

IGBTs may require a higher supply to work correctly

with the bootstrap technique. Also V

CC

variations

must be accounted in the above formulas.

IR21141/IR22141SSPbF

18

2.3 Some Important Considerations

Voltage Ripple: There are three different cases to

consider (refer to Fig. 19).



I

LOAD

< 0 A; the load current flows in the low side

IGBT (resulting in V

CEon

).

CEonFCCBS

VVVV

−

=

In this case we have the lowest value for V

BS

. This

represents the worst case for the bootstrap capacitor

sizing. When the IGBT is turned off, the V

s

node is

pushed up by the load current until the high side

freewheeling diode is forwarded biased.



I

LOAD

= 0 A; the IGBT is not loaded while being on

and V

CE

can be neglected

FCCBS

VVV

−

=



I

LOAD

> 0 A; the load current flows through the

freewheeling diode

FPFCCBS

VVVV

+

−

=

In this case we have the highest value for V

BS

. Turning

on the high side IGBT, I

LOAD

flows into it and V

S

is

pulled up. To minimize the risk of undervoltage, the

bootstrap capacitor should be sized according to the

I

LOAD

< 0 A case.

Bootstrap Resistor: A resistor (R

boot

) is placed in series

with the bootstrap diode (see Fig. 19) in order to limit

the current when the bootstrap capacitor is initially

charged. We suggest not exceeding 10

Ω

to avoid

increasing the V

BS

time-constant. The minimum on time

for charging the bootstrap capacitor or for refreshing its

charge must be verified against this time-constant.

Bootstrap Capacitor: For high

t

HON

designs where an

electrolytic capacitor is used, its ESR must be

considered. This parasitic resistance forms a voltage

divider with R

boot

, which generats a voltage step on V

BS

at the first charge of bootstrap capacitor. The voltage

step and the related speed (dV

BS

/dt) should be limited.

As a general rule, ESR should meet the following

constraint.

A parallel combination of a small ceramic capacitor and

a large electrolytic capacitor is normally the best

compromise, the first capacitor posses a fast time

constant and limits the dV

BS

/dt by reducing the

equivalent resistance. The second capacitor provides a

large capacitance to maintain the V

BS

voltage drop

within the desired

∆V

BS

.

Bootstrap Diode: The diode must have a BV > 600 V or

1200 V and a fast recovery time (t

rr

< 100 ns) to

minimize the amount of charge fed back from the

bootstrap capacitor to V

CC

supply.

2.4 Gate Resistances

The switching speed of the output transistor can be

controlled by properly sizing the resistors controlling the

turn-on and turn-off gate currents. The following section

provides some basic rules for sizing the resistors to

obtain the desired switching time and speed by

introducing the equivalent output resistance of the gate

driver (

R

DRp

and

R

DRn

).

The example shown uses IGBT power transistors and

Figure 20 shows the nomenclature used in the following

paragraphs. In addition, V

ge*

indicates the plateau

voltage,

Q

gc

and

Q

ge

indicate the gate to collector and

gate to emitter charge respectively.

V

ge

*

10%

t

1

,Q

GE

C

RESoff

C

RESon

V

CE

I

C

V

GE

C

RES

10%

90%

C

RES

t

Don

V

GE

dV/dt

I

C

t

2

,Q

GC

t,Q

t

R

t

SW

Figure 20:

Nomenclature

2.5 Sizing The Turn-On Gate Resistor

Switching-Time: For the matters of the calculation

included hereafter, the switching time t

sw

is defined

as the time spent to reach the end of the plateau

voltage (a total

Q

gc

+

Q

ge

has been provided to the

IGBT gate). To obtain the desired switching time the

gate resistance can be sized starting from

Q

ge

and

Q

gc

,

Vcc

,

V

ge*

(see Fig. 21):

sw

gegc

avg

t

QQ

I

+

=

and

avg

ge

TOT

I

VVcc

R

*

−

=

IR21141/IR22141SSPbF

19

Vcc/Vb

R

DRp

R

Gon

C

RES

COM/Vs

I

avg

Figure 21:

R

Gon

Sizing

where

GonDRpTOT

RRR +=

R

Gon

= gate on-resistor

R

DRp

= driver equivalent on-resistance

R

DRp

is approximately given by











≤

>

−

+

=

+

++

1

211

onSW

o

onSW

SW

onSW

oon

SW

o

DRp

ttfor

I

Vcc

ttfor

t

tt

I

Vcc

t

I

Vcc

R

(I

O1+

,I

O2+

and t

on1

from “Static Electrical

Characteristics”).

Table 1 reports the gate resistance size for two

commonly used IGBTs (calculation made using typical

datasheet values and assuming V

CC

= 15 V).

Output Voltage Slope: The turn-on gate resistor

R

Gon

can be sized to control the output slope

(dV

OUT

/dt). While the output voltage has a non-

linear behaviour, the maximum output slope can be

approximated by:

RESoff

avg

out

C

I

dt

dV =

inserting the expression yielding I

avg

and rearranging:

dt

dV

C

VVcc

R

out

RESoff

ge

TOT

⋅

−

=

*

As an example, table 2 shows the sizing of gate

resistance to get

dV

out

/dt= 5 V/ns

when using two

popular IGBTs (typical datasheet values are used and

V

CC

= 15 V

is assumed).

NOTICE

: Turn on time must be lower than T

BL

to avoid

improper desaturation detection and SSD triggering.

2.6 Sizing the Turn-Off Gate Resistor

The worst case in sizing the turn-off resistor R

Goff

is

when the collector of the IGBT in the off state is forced

to commutate by an external event (e.g., the turn-on of

the companion IGBT). In this case the dV/dt of the

output node induces a parasitic current through C

RESoff

flowing in R

Goff

and R

DRn

(see Fig. 22). If the voltage

drop at the gate exceeds the threshold voltage of the

IGBT, the device may self turn on, causing large

oscillation and relevant cross conduction.

OFF

HS Turning ON

ON

dV/dt

R

Goff

C

RESoff

R

DRn

C

IES

Figure 22:

R

Goff

Sizing: Current Path When Low Side is

Off and High Side Turns On

The transfer function between the IGBT collector and

the IGBT gate then becomes:

)()(1

)(

IESRESoffDRnGoff

RESoffDRnGoff

de

ge

CCRRs

CRRs

V

+⋅+⋅+

⋅

+

⋅

=

which yields to a high pass filter with a pole at:

)()(

1

/1

IESRESoffDRnGoff CCRR +⋅+

=

τ

As a result, when

τ

is faster than the collector rise time

(to be verified after calculation) the transfer function can

be approximated by:

RESoffDRnGoff

de

ge CRRs

V

V⋅+⋅= )(

so that

dt

dV

CRRV

de

RESoffDRnGoffge

⋅⋅+= )(

in the time domain. Then the condition:

(

)

dt

dV

CRRVV

out

RESoffDRnGoffgeth

⋅+=>

must be verified to avoid spurious turn on.

Rearranging the equation yields:

DRn

RESoff

th

Goff

R

dt

dV

C

V

R−

⋅

<

R

DRn

is approximately given by

IR21141/IR22141SSPbF

20

−

=

o

DRn

I

Vcc

R

In any case, the worst condition for unwanted turn on is

with very fast steps on the IGBT collector.

In that case, the collector to gate transfer function can

be approximated with the capacitor divider:

)(

IESRESoff

RESoff

dege

CC

C

VV +

⋅=

which is driven only by IGBT characteristics.

As an example, table 3 reports R

Goff

(calculated with the

above mentioned disequation) for two popular IGBTs to

withstand

dV

out

/dt = 5 V/ns

.

NOTICE:

The above-described equations are intended

to approximate a way to size the gate resistance. A

more accurate sizing may provide more precise device

and PCB (parasitic) modelling.

IGBT Qge Qgc Vge* tsw Iavg Rtot RGon

→

std commercial value Tsw

IRGP30B120K(D) 19 nC 82 nC 9 V 400 ns 0.25 A 24

Ω

RTOT - RDRp = 12.7

Ω

→

10

Ω

→

420 ns

IRG4PH30K(D) 10 nC 20 nC 9 V 200 ns 0.15 A 40

Ω

RTOT - RDRp = 32.5

Ω

→

33

Ω

→

202 ns

Table 1: t

sw

Driven R

Gon

Sizing

IGBT Qge Qgc Vge* CRESoff Rtot RGon

→

std commercial value dVout/dt

IRGP30B120K(D) 19 nC 82 nC 9 V 85 pF 14

Ω

RTOT - RDRp = 6.5

Ω

→

8.2

Ω

→

4.5 V/ns

IRG4PH30K(D) 10 nc 20 nC 9 V 14 pF 85

Ω

RTOT - RDRp = 78

Ω

→

82

Ω

→

5 V/ns

Table 2: dV

OUT

/dt Driven R

Gon

Sizing

IGBT Vth(min) CRESoff RGoff

IRGP30B120K(D) 4 85 pF RGoff

≤

4

Ω

IRG4PH30K(D) 3 14 pF RGoff

≤

35

Ω

Table 3: R

Goff

Sizing

IR21141/IR22141SSPbF

21

3 PCB Layout Tips

3.1 Distance from High to Low Voltage

The IR2x14x pinout maximizes the distance between

floating (from DC- to DC+) and low voltage pins. It’s

strongly recommended to place components tied to

floating voltage on the high voltage side of device (V

B

,

V

S

side) while the other components are placed on the

opposite side.

3.2 Ground Plane

To minimize noise coupling, the ground plane must not

be placed under or near the high voltage floating side.

3.3 Gate Drive Loops

Current loops behave like antennas and are able to

receive and transmit EM noise. In order to reduce the

EM coupling and improve the power switch turn on/off

performances, gate drive loops must be reduced as

much as possible. Figure 23 shows the high and low

side gate loops.

Moreover, current can be injected inside the gate drive

loop via the IGBT collector-to-gate parasitic

capacitance. The parasitic auto-inductance of the gate

loop contributes to developing a voltage across the

gate-emitter, increasing the possibility of self turn-on.

For this reason, it is strongly recommended to place the

three gate resistances close together and to minimize

the loop area (see Fig. 23).

gate

resistance

VS/COM

VB/ VCC

H/LOP

H/LON

SSDH/L

V

GE

Gate Drive

Loop

C

GC

I

GC

Figure 23:

gate drive loop

3.4 Supply Capacitors

The IR2x14x output stages are able to quickly turn on

an IGBT, with up to 2 A of output current. The supply

capacitors must be placed as close as possible to the

device pins (V

CC

and V

SS

for the ground tied supply, V

B

and V

S

for the floating supply) in order to minimize

parasitic inductance/resistance.

3.5 Routing and Placement Example

Figure 24 shows one of the possible layout solutions

using a 3 layer PCB. This example takes into account

all the previous considerations. Placement and routing

for supply capacitors and gate resistances in the high

and low voltage side minimize the supply path loop and

the gate drive loop. The bootstrap diode is placed under

the device to have the cathode as close as possible to

the bootstrap capacitor and the anode far from high

voltage and close to V

CC

.

R2

R3

R4

R5

R6

R7

C2

D3

D2

IR2214

V

GH

V

GL

DC+

Phase

a) Top Layer

D1

R1

C1

V

EH

V

EL

V

CC

b) Bottom Layer

c) Ground Plane

Figure 24:

layout example

Information below refers to Fig. 24:

Bootstrap section: R1, C1, D1

High side gate: R2, R3, R4

High side Desat: D2

Low side supply: C2

Low side gate: R5, R6, R7

Low side Desat: D3

IR21141/IR22141SSPbF

22

Figures 25-83 provide information on the experimental performance of the IR21141/IR22141SSPbF HVIC. The line

plotted in each figure is generated from actual lab data. A large number of individual samples from multiple wafer lots

were tested at three temperatures (-40 ºC, 25 ºC, and 125 ºC) in order to generate the experimental (Exp.) curve. The

line labeled Exp. consist of three data points (one data point at each of the tested temperatures) that have been

connected together to illustrate the understood trend. The individual data points on the curve were determined by

calculating the averaged experimental value of the parameter (for a given temperature).

9.95

10.00

10.05

10.10

10.15

10.20

10.25

10.30

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

V

CCUV+

Threshold (V)

Figure 25. V

CCUV+

Threshold vs. Temperature

Exp.

0

100

200

300

400

500

600

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

V

BS

Quiescent Current (uA)

Figure 29. V

BS

Quiescent Current vs. Temperature

Exp.

0.00

0.10

0.20

0.30

0.40

0.50

0.60

0.70

0.80

0.90

1.00

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

V

CC

Quiescent Current (mA)

Figure 30. V

CC

Quiescent Current vs. Temperature

Exp.

10.00

10.05

10.10

10.15

10.20

10.25

10.30

10.35

10.40

10.45

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

V

BSUV+

Threshold Threshold (V)

Figure 27. V

BSUV+

Threshold vs. Temperature

Exp.

9.25

9.30

9.35

9.40

9.45

9.50

9.55

9.60

9.65

9.70

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

V

BSUV-

ThresholdThreshold (V)

Figure 28. V

BSUV-

Threshold vs. Temperature

Exp.

9.15

9.20

9.25

9.30

9.35

9.40

9.45

9.50

9.55

9.60

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

V

CCUV-

Threshold (V)

Figure 26. V

CCUV-

Threshold vs. Temperature

Exp.

IR21141/IR22141SSPbF

23

1.10

1.50

1.90

2.30

2.70

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

V

IH

Logic Input Voltage (V)

Figure 31. V

IH

Logic Input Voltage vs. Temperature

Exp.

0.90

1.20

1.50

1.80

2.10

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

V

IL

Logic Input Voltage (V)

Figure 32. V

IL

Logic Input Voltage vs. Temperature

Exp.

0.00

0.10

0.20

0.30

0.40

0.50

0.60

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

V

IHSS

HIN Logic Input Hysteresis (V)

Figure 33. V

IHSS

HIN Logic Input Hysteresis vs.

Temperature

Exp.

1.00

1.30

1.60

1.90

2.20

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

LIN Logic "1" Input Voltage (V)

Figure 34. LIN Logic "1" Input Voltage vs. Temperature

Exp.

0.70

1.00

1.30

1.60

1.90

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

LIN Logic "0" Input Voltage (V)

Figure 35. LIN Logic "0" Input Voltage vs. Temperature

Exp.

0.10

0.30

0.50

0.70

0.90

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

V

IHSS

LIN Logic Input Hysteresis (V)

Figure 36. V

IHSS

LIN Logic Input Hysteresis vs.

Temperature

Exp.

IR21141/IR22141SSPbF

24

1.10

1.40

1.70

2.00

2.30

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

V

IH

FLTCLR Logic Input Voltage (V)

Figure 37. V

IH

FLTCLR Logic Input Voltage vs.

Temperature

Exp.

0.80

1.10

1.40

1.70

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

V

IL

FLTCLR Logic Input Hysteresis (V)

Figure 38. V

IL

FLTCLR Logic Input Voltage vs.

Temperature

Exp.

0.20

0.30

0.40

0.50

0.60

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

V

IHSS

FLTCLR Logic Input Hysteresis (V)

Figure 39. V

IHSS

FLTCLR Logic Input Hysteresis vs.

Temperature

Exp.

0.50

0.90

1.30

1.70

2.10

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

V

IH

SD Logic Input Voltage (V)

Figure 40. V

IH

SD Logic Input Voltage vs. Temperature

Exp.

0.50

0.90

1.30

1.70

2.10

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

V

IL

SD Logic Input Voltage (V)

Figure 41. V

IL

SD Logic Input Voltage vs. Temperature

Exp.

0.20

0.30

0.40

0.50

0.60

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

V

IHSS

SD Logic Input Hysteresis (V)

Figure 42. V

IHSS

SD Logic Input Hysteresis vs. Temperature

Exp.

IR21141/IR22141SSPbF

25

0.80

1.20

1.60

2.00

2.40

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

V

IH

SYFLT Logic Input Voltage (V)

Figure 43. V

IH

SYFLT Logic Input Voltage vs. Temperature

Exp.

20

30

40

50

60

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

V

OL

LO (mV)

Figure 46. V

OL

LO vs. Temperature

Exp.

200

375

550

725

900

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

V

OH

LO (mV)

Figure 47. V

OH

LO vs. Temperature

Exp.

25

35

45

55

65

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

V

OL

HO (mV)

Figure 48. V

OL

HO vs. Temperature

Exp.

0.80

1.20

1.60

2.00

2.40

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

V

IL

SYFLT Logic Input Voltage (V)

Figure 44. V

IL

SYFLT Logic Input Voltage vs. Temperature

Exp.

0.20

0.30

0.40

0.50

0.60

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

VIHSS SYFLT Logic Input Hysteresis (V)

Figure 45. V

IHSS

SYFLT Logic Input Hysteresis vs.

Temperature

Exp.

IR21141/IR22141SSPbF

26

200

375

550

725

900

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

VOH HO (mV)

Figure 49. V

OH

HO vs. Temperature

Exp.

5

6

7

8

9

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

VDSH+ DSH

Input Voltage (V)

Figure 50. V

DSH+

DSH Input Voltage vs. Temperature

Exp.

7

8

9

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

VDSL+ DSL Input Voltage (V)

Figure 51. V

DSL+

DSL Input Voltage vs. Temperature

Exp.

5.50

6.20

6.90

7.60

8.30

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

VDSH- DSH Input Voltage (V)

Figure 52. V

DSH-

DSH Input Voltage vs. Temperature

Exp.

6.00

6.50

7.00

7.50

8.00

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

V

DSL-

DSL Input Voltage (V)

Figure 53. V

DSL-

DSL Input Voltage vs. Temperature

Exp.

30

45

60

75

90

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

FAULT/SD Open Drain Resistance (Ω)

Figure 54. FAULT/SD Open Drain Resistance vs.

Temperature

Exp.

IR21141/IR22141SSPbF

27

30

55

80

105

130

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

SY_FLT Open Drain Resistance (Ω)

Figure 55. SY_FLT Open Drain Resistance vs. Temperature

Exp.

250

310

370

430

490

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

DTL Off Deadtime (ns)

Figure 56. DTL Off Deadtime vs. Temperature

Exp.

250

310

370

430

490

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

DTH Off Deadtime (ns)

Figure 57. DTH Off Deadtime vs. Temperature

Exp.

300

420

540

660

780

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

TonH Propagation Delay (ns)

Figure 58. TonH Propagation Delay vs. Temperature

Exp.

300

420

540

660

780

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

ToffH Propagation Delay (ns)

Figure 59. ToffH Propagation Delay vs. Temperature

Exp.

12

16

20

24

28

32

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

TrH Turn On Rise Time (ns)

Figure 60. TrH Turn On Rise Time vs. Temperature

Exp.

IR21141/IR22141SSPbF

28

6

9

12

15

18

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

TfH Turn Off Fall Time (ns) )

Figure 61. TfH Turn Off Fall Time vs. Temperature

Exp.

300

420

540

660

780

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

TonL Propagation Delay (ns)

Figure 62. TonL Propagation Delay vs. Temperature

Exp.

300

420

540

660

780

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

ToffL Propagation Delay (ns)

Figure 63. ToffL Propagation Delay vs. Temperature

Exp.

12

19

26

33

40

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

TrL Turn On Rise Time (ns)

Figure 64. TrL Turn On Rise Time vs. Temperature

Exp.

4

8

12

16

20

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

TfL Turn Off Fall Time (ns)

Figure 65. TfL Turn Off Fall Time vs. Temperature

Exp.

2

3

4

5

6

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

t

DSAT1

(us)

Figure 66. t

DSAT1

vs. Temperature

Exp.

IR21141/IR22141SSPbF

29

1

2

3

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

t

DSAT2

(us)

Figure 67. t

DSAT2

vs. Temperature

Exp.

2

3

4

5

6

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

t

DSAT3

(us)

Figure 68. t

DSAT3

vs. Temperature

Exp.

0.50

1.50

2.50

3.50

4.50

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

t

DSAT4

(us)

Figure 69. t

DSAT4

vs. Temperature

Exp.

5

8

11

14

17

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

t

SSH

(us)

Figure 70. t

SSH

vs. Temperature

Exp.

5

8

11

14

17

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

t

SSL

(us)

Figure 71. t

SSL

vs. Temperature

Exp.

0.40

0.75

1.10

1.45

1.80

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

IO2+H SC Pulsed Current (A)

Figure 72. IO2+H SC Pulsed Current vs. Temperature

Exp.

IR21141/IR22141SSPbF

30

0.40

0.75

1.10

1.45

1.80

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

IO2+L SC Pulsed Current (A)

Figure 73. IO2+L SC Pulsed Current vs. Temperature

Exp.

1.45

1.90

2.35

2.80

3.25

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

IO-H SC Pulsed Current (A)

Figure 74. IO-H SC Pulsed Current vs. Temperature

Exp.

1.25

1.70

2.15

2.60

3.05

3.50

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

IO-L SC Pulsed Current (A)

Figure 75. IO-L SC Pulsed Current vs. Temperature

Exp.

100

300

500

700

900

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

t

ON1H

(ns)

Figure 76. t

ON1H

vs. Temperature

Exp.

100

200

300

400

500

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

t

ON1L

(ns)

Figure 77. t

ON1L

vs. Temperature

Exp.

1.00

1.50

2.00

2.50

3.00

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

IO1+H SC Pulsed Current (A)

Figure 78. IO1+H SC Pulsed Current vs. Temperature

Exp.

IR21141/IR22141SSPbF

31

0

1

2

3

4

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

IO1+L SC Pulsed Current (ns)

Figure 79. IO1+L SC Pulsed Current vs. Temperature

Exp.

100

300

500

700

900

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

IHIN+ Logic "1" Input Bias Current (uA)

Figure 80. I

HIN+

Logic "1" Input Bias Current vs.

Temperature

Exp.

-0.28

-0.23

-0.18

-0.13

-0.08

-0.03

0.02

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

IHIN- Logic "0" Input Bias Current (uA)

Figure 81. I

HIN-

Logic "0" Input Bias Currentvs.

Temperature

Exp.

100

300

500

700

900

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

ILIN+ Logic "1" Input Bias Current (uA)

Figure 82. I

LIN+

Logic "1" Input Bias Current vs.

Temperature

Exp.

-0.28

-0.23

-0.18

-0.13

-0.08

-0.03

0.02

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

ILIN- Logic "0" Input Bias Current (uA)

Figure 83. I

LIN-

Logic "0" Input Bias Current vs.

Temperature

Exp.

IR21141/IR22141SSPbF

32

Case Outline

IR21141/IR22141SSPbF

33

CARRIER TAPE DIMENSION FOR 24SSOP:2000 units per reel

Code Min Max Min Max

A 11.90 12.10 0.468 0.476

B 3.90 4.10 0.153 0.161

C 15.70 16.30 0.618 0.641

D 7.40 7.60 0.291 0.299

E 8.30 8.50 0.326 0.334

F 8.50 8.70 0.334 0.342

G 1.50 n/a 0.059 n/a

H 1.50 1.60 0.059 0.062

Metric Imperial

REEL DIMENSIONS FOR 24SSOP

Code Min Max Min Max

A 329.60 330.25 12.976 13.001

B 20.95 21.45 0.824 0.844

C 12.80 13.20 0.503 0.519

D 1.95 2.45 0.767 0.096

E 98.00 102.00 3.858 4.015

F n/a 22.40 n/a 0.881

G 18.50 21.10 0.728 0.830

H 16.40 18.40 0.645 0.724

Metric Imperial

E

F

A

C

D

G

A

B

H

NOTE : CONTROLLING

DIMENSION IN MM

LOADED TAPE FEED DIRECTION

A

H

F

E

G

D

B

C

IR21141/IR22141SSPbF

34

WORLDWIDE HEADQUARTERS: 233 Kansas Street, El Segundo, CA 90245 Tel: (310) 252-7105

This part has been qualified per industrial level

http://www.irf.com

Data and specifications subject to change without notice. 5/18/2006

ORDER INFORMATION

24-Lead SSOP IR21141SSPbF

24-Lead SSOP IR22141SSPbF

24-Lead SSOP Tape & Reel IR21141SSPbF

24-Lead SSOP Tape & Reel IR22141SSPbF